阅读说明：本技术 光半导体元件 (Optical semiconductor element ) 是由 山根贵好 于 2019-07-12 设计创作，主要内容包括：提供一种光半导体元件,光半导体芯片与子安装件之间的未接合部少,散热效率高且长寿命。光半导体元件具有：平板状的子安装件,其具有搭载面；子安装电极,其设置在所述子安装件的所述搭载面上,作为整体具有矩形形状；以及半导体芯片,其包括元件基板、形成在所述元件基板上的半导体结构层以及经由接合层与所述子安装电极接合的芯片电极,所述芯片电极具有缺少与所述子安装电极的四角对应的角部的形状,所述子安装电极在所述四角具有从所述芯片电极露出的部分即露出面,与所述芯片电极相匹配地接合,所述接合层延伸到所述四角中的所有的角的所述露出面。(Provided is an optical semiconductor element having a high heat dissipation efficiency and a long life, with few unjoined portions between an optical semiconductor chip and a submount. The optical semiconductor element includes: a flat plate-like sub-mount having a mounting surface; a sub mount electrode provided on the mounting surface of the sub mount and having a rectangular shape as a whole; and a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the sub-mount electrode via a bonding layer, the chip electrode having a shape lacking corners corresponding to four corners of the sub-mount electrode, the sub-mount electrode having exposed surfaces at the four corners, which are portions exposed from the chip electrode, and being bonded to the chip electrode so as to match the chip electrode, the bonding layer extending to the exposed surfaces of all of the four corners.)

1. An optical semiconductor element, comprising:

a flat plate-like sub-mount having a mounting surface;

a sub mount electrode provided on the mounting surface of the sub mount and having a rectangular shape as a whole; and

a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the sub-mount electrode via a bonding layer,

the chip electrode has a shape lacking corners corresponding to four corners of the sub-mount electrode,

the sub-mount electrode has exposed surfaces at the four corners, which are exposed from the chip electrodes, and is bonded to the chip electrodes so as to match the chip electrodes,

the joining layer extends to the exposed surface of all of the four corners.

2. The optical semiconductor element according to claim 1,

the sub-mount electrode has 2 sub-mount electrode pieces, the 2 sub-mount electrode pieces having rectangular shapes, respectively, and being arranged separately from each other,

the chip electrode has 2 chip electrode pieces, the 2 chip electrode pieces having shapes and configurations respectively matching the corresponding sub-mount electrode pieces except for the four corners of the sub-mount electrode, lacking corners corresponding to the four corners of the sub-mount electrode,

the 2 sub-mount electrode pads and the 2 chip electrode pads are matingly joined to each other except for the four corners.

3. The optical semiconductor element according to claim 2,

the 2 chip electrode pieces lack corner portions corresponding to respective four corners of the 2 sub-mount electrode pieces,

the 2 sub-mount electrode pads have the exposed surfaces at the respective four corners,

the joining layer extends to the exposed surfaces of all of the respective four corners.

4. The optical semiconductor element according to claim 1,

the sub-mount electrodes include 1 st to nth sub-mount electrode sheets, the 1 st to nth sub-mount electrode sheets having stripe shapes and being disposed separately from each other, where n is not less than 2,

the chip electrodes have 1 st to nth chip electrode pads, the 1 st to nth chip electrode pads have shapes and arrangements respectively matching the corresponding sub-mount electrode pads except for four corners of the sub-mount electrode, lack end portions corresponding to both end portions of the 1 st and nth sub-mount electrode pads,

except for the four corners, the sub-mount electrode pads and the chip electrode pads are matingly engaged with each other.

5. The optical semiconductor element according to claim 1,

the sub-mount electrodes include 1 st to nth sub-mount electrode sheets, the 1 st to nth sub-mount electrode sheets having stripe shapes and being disposed separately from each other, where n is not less than 2,

the chip electrodes have 1 st to nth chip electrode pads, the 1 st to nth chip electrode pads having shapes and arrangements respectively matching the corresponding sub-mount electrode pads except for respective ends of the sub-mount electrode pads, lacking ends corresponding to both ends of the respective sub-mount electrode pads,

each of the sub-mount electrode pads has an exposed surface at each of the two end portions, the exposed surface being a portion exposed from each of the chip electrode pads,

the joining layer extends to the exposed surface of each of the sub-mount electrode pads.

6. The optical semiconductor element according to claim 4 or 5,

the long sides of the stripe shapes of the 1 st to n-th sub-mount electrode pads are arranged parallel to each other to form an n-row arrangement,

the semiconductor chip has a chip-side opposite electrode provided separately from the 1 st to nth chip electrode pads,

the submount has a submount-side counter electrode, and the submount-side counter electrode is provided on the mounting surface separately from the submount electrode and is bonded to the chip-side counter electrode via the bonding layer.

7. The optical semiconductor element according to claim 6,

the semiconductor structure layer includes a1 st conductive type semiconductor layer, an active layer, and a2 nd conductive type semiconductor layer,

the 1 st to nth chip electrode pads are electrically connected to the 1 st conductive type semiconductor layer,

the 1 st conductive semiconductor layer has a1 st electrode layer formed in a comb-tooth shape, the 1 st electrode layer being composed of comb-tooth portions having shapes and arrangements corresponding to the 1 st to nth chip pads, respectively, and base portions connecting one-side end portions of the comb-tooth portions,

the 2 nd conductive semiconductor layer has a2 nd electrode layer formed in a comb shape, and the 2 nd electrode layer is composed of a base portion electrically connected to the chip side counter electrode and a comb portion extending to a gap between the 1 st chip electrode pad and the n-th chip electrode pad.

8. The optical semiconductor element according to any one of claims 1 to 7,

the bonding layer extends to cover the entire exposed surface.

9. The optical semiconductor element according to any one of claims 1 to 8,

the element substrate has optical transparency to light having a predetermined wavelength.

10. The optical semiconductor element according to any one of claims 1 to 9,

the element substrate has optical transparency to light having a wavelength in the visible light region.

11. An optical semiconductor element, comprising:

a flat plate-like sub-mount having a mounting surface;

a sub-mount electrode provided on the mounting surface of the sub-mount;

a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the submount electrode via a bonding layer and having a rectangular shape as a whole,

the sub-mount electrodes have a shape lacking corners corresponding to four corners of the chip electrodes,

the chip electrode has exposed surfaces at the four corners, which are exposed portions from the sub-mount electrodes, and is bonded to the sub-mount electrodes so as to match the sub-mount electrodes,

the joining layer extends to the exposed surface of all of the four corners.

12. The optical semiconductor element according to claim 11,

the sub-mount has optical transparency to light of a predetermined wavelength.

Technical Field

The present invention relates to an optical semiconductor element such as a Light Emitting Diode (LED).

Background

An optical semiconductor element such as an LED is known in which an optical semiconductor chip is bonded and mounted to a submount for heat dissipation. In this bonding, a conductive Die attach (Die attach) material such as AuSn is used, and the semiconductor structure layer and the submount are bonded via this Die attach material.

For example, patent document 1 discloses an LED in which an LED chip is bonded to a submount via a pad (claim 12 and the like). It is also disclosed that the pad is made of Au or an appropriate metal alloy such as Au/Sn, Pb/Sn, Sn/Ag (paragraph [0017], etc.).

Disclosure of Invention

Problems to be solved by the invention

In the above-described bonding of the optical semiconductor layer and the submount, there are problems as follows: that is, the efficiency of heat dissipation may be reduced due to voids generated in the bonding layer made of the patch material, uneven spreading of the patch material, or the like.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an optical semiconductor element having few unbonded portions between an optical semiconductor chip and a submount, high heat dissipation efficiency, and a long life.

Means for solving the problems

The optical semiconductor element of the present invention includes: a flat plate-like sub-mount having a mounting surface; a sub mount electrode provided on the mounting surface of the sub mount and having a rectangular shape as a whole; and a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the sub-mount electrode via a bonding layer, the chip electrode having a shape lacking corners corresponding to four corners of the sub-mount electrode, the sub-mount electrode having exposed surfaces at the four corners, which are portions exposed from the chip electrode, and being bonded to the chip electrode so as to match the chip electrode, the bonding layer extending to the exposed surfaces of all of the four corners.

Further, an optical semiconductor device of the present invention includes: a flat plate-like sub-mount having a mounting surface; a sub-mount electrode provided on the mounting surface of the sub-mount; a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the submount electrode via a bonding layer and having a rectangular shape as a whole, the submount electrode having a shape lacking corners corresponding to four corners of the chip electrode, the chip electrode having exposed surfaces at the four corners, which are portions exposed from the submount electrode, and being bonded so as to match the submount electrode, the bonding layer extending to the exposed surfaces of all of the four corners.

Drawings

Fig. 1 is a plan view of a light-emitting device according to example 1.

Fig. 2A is a sectional view of a light-emitting device according to embodiment 1.

Fig. 2B is a partially enlarged sectional view of the light-emitting device according to embodiment 1.

Fig. 3A is a plan view showing an example of the steps of manufacturing the optical semiconductor element according to example 1.

Fig. 3B is a cross-sectional view showing an example of a process for manufacturing the optical semiconductor element according to example 1.

Fig. 4A is a plan view showing an example of the steps of manufacturing the optical semiconductor element according to example 1.

Fig. 4B is a cross-sectional view showing an example of the manufacturing process of the optical semiconductor element according to example 1.

Fig. 5A is a plan view showing an example of the steps of manufacturing the optical semiconductor element according to example 1.

Fig. 5B is a cross-sectional view showing an example of the manufacturing process of the optical semiconductor element according to example 1.

Fig. 6A is a plan view showing a modification of the optical semiconductor element according to example 1.

Fig. 6B is a cross-sectional view showing a modification of the optical semiconductor element according to example 1.

Fig. 6C is a bottom view showing a modified example of the optical semiconductor element according to embodiment 1.

Fig. 6D is a cross-sectional view showing a modification of the optical semiconductor element according to example 1.

Fig. 7 is a plan view of the light-emitting device according to example 2.

Fig. 8 is a sectional view of a light-emitting device according to example 2.

Fig. 9 is a plan view showing a modification of the optical semiconductor element according to example 2.

Fig. 10 is a plan view showing the optical semiconductor element according to example 3.

Fig. 11 is a cross-sectional view showing the optical semiconductor device according to example 3.

Fig. 12A is a plan view showing an example of the steps of manufacturing the optical semiconductor element according to example 3.

Fig. 12B is a plan view showing an example of the steps for manufacturing the optical semiconductor element according to example 3.

Fig. 13 is a plan view showing the optical semiconductor device according to example 4.

Fig. 14A is a plan view showing the optical semiconductor element according to example 4.

Fig. 14B is a plan view showing the optical semiconductor element according to example 4.

Fig. 15 is a plan view of a light-emitting device according to example 5.

Fig. 16 is a sectional view of a light-emitting device according to example 5.

Fig. 17 is a cross-sectional view of a semiconductor chip according to example 5.

Fig. 18 is a top view of a semiconductor structure layer according to example 5.

Description of reference numerals:

10. 30, 50 light emitting device

11. 31, 51 optical semiconductor element

12. 52 sub-mount

13. 33, 53 sub-mount electrode

Exposed surfaces of 13S, 33S and 53S

15. 35, 55 bonding layer

17. 37, 57 chip electrode

18. 38 element substrate

19. 59 semiconductor structure layer

20. 40, 60 semiconductor chip

21. 61A, 61B power feeding adhesive

23A, 23B energizing pad

24 bond wire

25 reflecting body

26 cavity

Detailed Description

The following provides a detailed description of examples of the present invention. In the following description and the drawings, the same reference numerals are given to substantially the same or equivalent portions. In the top view of the drawings, a part of the constituent elements is shown with appropriate hatching for clarity.

[ example 1 ]

The structure of the light-emitting device 10 according to the present embodiment will be described with reference to fig. 1, 2A, and 2B. The light-emitting device 10 includes the optical semiconductor element 11 of the present invention. Fig. 1 is a plan view showing the structure of a light-emitting device 10. Fig. 2A is a cross-sectional view taken along line 2A-2A in fig. 1 of the light-emitting device 10. In fig. 1, a part of the member is shown with hatching for the convenience of explanation.

First, the structure of the optical semiconductor element 11 will be described. The submount 12 is a flat plate-like substrate having a mounting surface. The submount 12 is made of, for example, a substrate of alumina, AlN ceramic, SiC, or the like. In this embodiment, a case where the submount 12 is AlN ceramic having high thermal conductivity will be described.

As shown in fig. 2A, the sub mount electrode 13 is an electrode pattern formed on the mounting surface of the sub mount 12. As shown in fig. 1, the sub mount electrode 13 has a rectangular shape in plan view. For example, the sub-mount electrode 13 is made of metal such as Ti, Pt, Au, Pd, Cr, Ni, Cu, W, and Al.

As shown in fig. 2A, the bonding layer 15 is a conductive bonding material formed on the submount electrode 13. For example, as the bonding layer 15, a conductive material such as a conductive paste (paste), a solder material, a sintered Ag particle paste, or an anisotropic conductive paste can be used. In the present embodiment, for example, the bonding layer 15 is AuSn.

The chip electrode 17 is an electrode pattern provided on the bonding layer 15. That is, the chip electrode 17 is bonded to the sub-mount electrode 13 via the bonding layer 15. For example, the chip electrode 17 may be formed by combining metals such as Ti, Al, Fe, and Ni, and the chip electrode 17 may be formed by using metals such as Pt, W, Pd, Cr, and Cu.

In fig. 1, the bonding layer 15 and the chip electrode 17 are shown with hatching. As shown in fig. 1, the chip electrode 17 has a shape matching the mount electrode 13 except for four corners of the sub-mount electrode 13 in a plan view, and has a shape lacking corners corresponding to the four corners. In other words, the chip electrode 17 has a planar shape matching the sub-mount electrode 13 except for the lack of four corners. The sub-mount electrodes 13 are bonded to the chip electrodes 17 in a matching manner except for the four corners.

The element substrate 18 is a flat plate-like substrate, and is formed on the chip electrode 17 as shown in fig. 2A. For example, the element substrate 18 is a substrate having transparency to visible light, such as sapphire, SiC, or AlN. For example, the element substrate 18 may have a through hole (not shown) connected to the chip electrode 17. The element substrate 18 may be a substrate having conductivity such as ITO, or may be a substrate composed of a plurality of layers.

The semiconductor structure layer 19 is formed on the element substrate 18. The semiconductor structure layer 19 is formed by sequentially stacking a p-type semiconductor layer 19A, an active layer (i.e., a light-emitting layer) 19B, and an n-type semiconductor layer 19C on the element substrate 18. In the optical semiconductor element 11, light from the light-emitting layer 19B is emitted from the upper surface of the n-type semiconductor layer 10C. That is, the upper surface of the n-type semiconductor layer 19C constitutes a light emitting surface.

The wavelength of the outgoing light emitted from the light-emitting layer 19B is a wavelength corresponding to the material and composition of the semiconductor structure layer 19. For example, the wavelength of the light emitted from the light-emitting layer 19B may be in the infrared region or in the deep ultraviolet region.

As shown in fig. 2A, the chip electrode 17, the element substrate 18, and the semiconductor structure layer 19 constitute a semiconductor chip 20. The optical semiconductor element 11 has a semiconductor chip 20 bonded to the sub-mount electrode 13 via a bonding layer 15. In the present embodiment, the semiconductor chip 20 is an element having a Thin-film type adhesive structure (or a metal adhesive structure (MB structure)).

The power supply adhesive 21 is formed on the surface of the submount 12 opposite to the mounting surface, and is an adhesive having conductivity. Power feed adhesive 21 is made of a conductive material such as AuSn. The package substrate 22 has a mounting surface on which an element such as an LED can be mounted. The package substrate 22 is a ceramic substrate such as AlN or alumina. In addition, a substrate such as a glass epoxy substrate may be used as the package substrate 22. Thus, the optical semiconductor element 11 is mounted on the package substrate 21 via the feed adhesive 21.

The current-carrying pads 23A and 23B are electrodes provided on the mounting surface of the package substrate 22, and are connection electrodes for connection to an external circuit and receiving supply of current. The current-carrying pads 23A are electrically connected to the sub-mount electrodes 13 via wiring (not shown) provided in the sub-mount 12. Therefore, the current-carrying pad 23A is electrically connected to the p-type semiconductor layer 19A via the submount electrode 13, the bonding layer 15, and the chip electrode 17. The power-on pad 23B is electrically connected to the n-type semiconductor layer 19C via a bonding wire 24.

The reflector 25 is a frame provided on the package substrate 22. The reflector 25 has an inner wall 25A. For example, the inner wall 25A has a shape of a side face of an inverted truncated pyramid expanding in a direction away from the upper surface of the package substrate 22. The upper surface of the package substrate 22 and the inner wall 25A form a cavity 26 in the shape of an inverted truncated pyramid. That is, the optical semiconductor element 11 is housed and packaged in the cavity 26. For example, the reflector 25 may be made of ceramic integrated with the package substrate 22.

Fig. 2B is an enlarged view of a portion 2B surrounded by a broken line of fig. 2A. As described above, the sub-mount electrode 13 is bonded to the chip electrode 17 via the bonding layer 15. Further, the chip electrode 17 has a shape lacking corners corresponding to the four corners of the sub-mount electrode. Therefore, the sub-mount electrode 13 has exposed surfaces 13S, which are portions exposed from the chip electrodes 17, at the four corners.

As shown in fig. 2B, the bonding layer 15 extends to the exposed surface 13S of the submount electrode 13. In the present embodiment, the bonding layer 15 extends to cover the entire exposed surface 13S. As shown in fig. 1, the bonding layer 15 extends to the exposed surface 13S of all the four corners of the submount electrode 13.

An example of a method for manufacturing the optical semiconductor element 11 will be described with reference to fig. 3A to 5B. Fig. 3A is a top view of the semiconductor chip 20. Fig. 3B is a cross-sectional view taken along line 3B-3B of fig. 3A.

As shown in fig. 3A and 3B, the semiconductor chip 20 is configured such that a semiconductor structure layer 19 is formed on the uppermost layer, an element substrate 18 is formed on the lower layer, and a chip electrode 17 is formed on the lower layer. As shown in fig. 3A, the chip electrode 17 has a shape lacking four corners of the rectangular shape.

For example, the n-type semiconductor layer 19C, the light-emitting layer 19B, and the p-type semiconductor layer 19A are grown by MOCVD (Metal organic chemical Vapor Deposition) or the like on a growth substrate that is a different substrate from the element substrate 18, the grown semiconductor layers are bonded to the element substrate 18, and the growth substrate is removed to form the semiconductor structure layer 19.

On the surface of the element substrate 18 opposite to the surface to which the semiconductor structure layer 19 is bonded, an electrode pattern is formed by a process such as metal deposition, photolithography, sputtering, or etching, thereby forming the chip electrode 17.

Fig. 4A is a plan view showing a patch material (DA material) 15L arranged on the sub-mount 12, the sub-mount electrode 13, and the sub-mount electrode 13. Fig. 4B is a cross-sectional view taken along line 4B-4B of fig. 4A.

As described above, the DA material 15L is a conductive material such as a conductive paste or a solder material, and in the present embodiment, AuSn is used as an example. The DA material 15L is disposed in the central portion of the sub-mount electrode 13 using Dispensing (Dispensing), for example. For example, the appropriate discharge amount of the DA material 15L may be set to a volume calculated from the desired thickness of the bonding layer 15 and the area of the submount electrode 13. For example, the volume of the DA material is calculated so that the thickness of the bonding layer 15 is about 10-20 μm. Further, flux (flux) may be applied as necessary to improve wettability of the bonding object.

The DA material 15L is preferably disposed at a position farthest from the four corners of the ion-mounting electrode 13, and centered at a position equidistant from the four corners. The DA material 15L is preferably disposed to have a spherical shape. With such a configuration, air is less likely to be involved when the DA material 15L expands, and an unbonded portion such as a void is less likely to be generated in the bonding layer 15.

After that, the semiconductor chip 20 is placed on the sub-mount electrode 13 in a direction in which the chip electrode 17 is in contact with the DA material 15L. At this time, the semiconductor chip 20 is mounted so that the sub-mount electrodes 13 and the chip electrodes 17 are aligned except for four corners of the sub-mount electrodes 13.

After the DA material 15L is disposed, when a load is applied to a position of the semiconductor chip 20 corresponding to the center of the DA material 15L, the DA material 15L spreads along the sub-mount electrode 13 and the chip electrode 17. When a uniform load is applied to the DA material 15L, the DA material 15L spreads to the four corners of the sub-mount electrode 13. Thereby, the sub-mount electrode 13 and the chip electrode 17 are bonded via the DA material 15L.

Fig. 5A is a plan view of a state where the sub-chip electrode 17 is bonded to the mount electrode 13. Fig. 5B is a cross-sectional view taken along line 5B-5B of fig. 5A. After the bonding, it is determined whether or not the DA material 15L spreads to the four corners of the sub-mount electrode 13. Specifically, it is determined whether or not the DA material 15L extends to the exposed surface 13S of the sub-mount electrode 13 exposed from the chip electrode 17.

In this determination, it is determined that the DA material 15L extends to the exposed surface 13S of all of the four corners. If the DA material 15L does not extend to any 1 or more exposed surfaces of the 4 exposed surfaces 13S at the four corners, it is determined to be defective.

This determination is performed, for example, by visual confirmation. In the case where the semiconductor structure layer 19 and the element substrate 18 have optical transparency to visible light as in this embodiment, whether or not the DA material 15L extends to the exposed surface 13S can be confirmed via the semiconductor structure layer 19 and the element substrate 18 as shown in fig. 5A.

For example, the determination may be performed by a method other than visual confirmation. For example, it is possible to determine whether or not the DA material 15L extends to the exposed surface 13S by using light in a wavelength region other than visible light as inspection light. In this case, the semiconductor structure layer 19 and the element substrate 18 may be transparent to the inspection light. Thereafter, a satisfactory product (a satisfactory product) is hardened in a reflow furnace (reflow furnace) to produce the optical semiconductor element 11 having the bonding layer 15.

As a non-defective product of this determination, it can be said that the DA material 15L spreads uniformly with a more uniform thickness between the sub-mount electrode 13 and the chip electrode 17. Therefore, the non-defective product suppresses the occurrence of voids and the like, and suppresses the occurrence of unbonded portions between the sub-mount electrodes 13 and the chip electrodes 17. In addition, it can be said that the non-defective product can ensure the flatness of the DA material 15L.

With reference to fig. 6A and 6B, another example of the manner in which the bonding layer 15 in the optical semiconductor element 11 extends to the exposed surface 13S of the submount electrode 13 will be described. Fig. 6A is a plan view of the optical semiconductor element 11. Fig. 6B is a cross-sectional view taken along line 6B-6B of fig. 6A.

In fig. 6A, the bonding layer 15 covers a part of the exposed surface 13S. The other part of the exposed surface 13S is exposed from the bonding layer 15. Referring to fig. 6B, the bonding layer 15 extends between the sub-mount electrode 13 and the chip electrode 17, and further extends toward the end of the sub-mount electrode 13 on the exposed surface 13S, but does not reach the end.

Thereby, the bonding layer 15 can partially extend to each exposed surface 13S of the exposed surfaces 13S of all the four corners. More specifically, in the optical semiconductor element 11, the adhesive layer 15 may extend to all of the four corners regardless of whether it extends to the entire exposed surface 13S or partially.

Therefore, the adhesive layer 15 may extend entirely on the exposed surfaces 13S of the four corners, and partially on the remaining exposed surfaces 13S. Further, it is more preferable that the exposed surface 13S of all the four corners extend entirely or partially.

Further, when the adhesive layer is partially extended, the extension degree, that is, the amount of the adhesive layer 15 extending from the chip electrode 17 is preferably equal for all four corners. That is, the adhesive layer 15 preferably extends uniformly on the exposed surface 13S of all the four corners.

The ease of spreading of the DA material 15L to the exposed surface 13S varies depending on the properties such as surface tension and viscosity at the time of manufacturing the DA material 15L. In consideration of this property, the allowable form of the adhesive layer 15 extending on the exposed surface 13S is preferably determined.

As described above, the optical semiconductor element 11 of the light emitting device 10 of the present embodiment has a structure in which the sub-mount electrode 13 having a rectangular shape and the chip electrode 17 of the semiconductor chip 20 are bonded via the bonding layer 15. The chip electrode 17 has a shape matching the sub-mount electrode 13 except for the four corners of the sub-mount electrode 13, and has a shape lacking corners corresponding to the four corners.

The sub-mount electrode 13 has exposed surfaces 13S, which are portions exposed from the chip electrodes 17, at the four corners. The bonding layer 15 extends to the exposed surface 13S of all the four corners. Therefore, the submount electrode 13 and the chip electrode 17 are bonded by the bonding layer 15 in a state in which generation of voids is suppressed, uneven spreading is suppressed, and a few unbonded portions are formed. Therefore, the current density of the current flowing through the sub-mount electrode 13 and the chip electrode 17 is more uniform. Further, the unjoined portions such as the voids are less likely to interfere with the heat conduction of the submount 12, and the heat dissipation efficiency is high. Therefore, the optical semiconductor element 11 having a long life with a reduced rate of decrease in light emission efficiency and the light-emitting device 10 using the optical semiconductor element 11 can be provided.

Further, with the structure in which the bonding layer 15 extends to the exposed surface 13S of all the four corners, the flatness of the bonding layer 15 can be ensured, and the semiconductor chip 20 can be mounted in parallel to the submount 12 with high accuracy. Therefore, the emitted light can be extracted as designed for the light-emitting device 10, and a desired light emission output can be obtained. Thus, according to the present embodiment, it is possible to provide an optical semiconductor element having few unbonded portions between the optical semiconductor chip and the submount, high heat dissipation efficiency, and a long life.

[ modified examples ]

Fig. 6C is a bottom view of the optical semiconductor element 11R which is a modification of the present embodiment. Fig. 6D is a cross-sectional view taken along line 6D-6D of fig. 6C, showing the sub-mount 12 as the lowermost layer.

The chip electrode 17, the bonding layer 15, and the sub-mount electrode 13 of the optical semiconductor element 11R have a different structure from the optical semiconductor element 11, but are otherwise configured in the same manner.

The optical semiconductor element 11R has a chip electrode 17R having a rectangular shape as a whole, and a sub-mount electrode 13R having a shape matching the chip electrode 17R except for four corners of the chip electrode 17R and lacking corners corresponding to the four corners. The bonding layer 15 extends to the exposed surface 17S of the chip electrode 17R exposed from the sub-mount electrode 13R.

In this case, the submount 12 is a substrate having translucency to the inspection light. On the other hand, the element substrate 18 may not have translucency to the inspection light.

With this configuration, it is possible to determine whether or not the bonding layer 15 extends to all the exposed surfaces 17S from the submount 12 side. Therefore, as in the case of the optical semiconductor element 11, generation of unjoined portions such as voids can be suppressed.

[ example 2 ]

The structure of the light emitting device 30 according to the present embodiment will be described with reference to fig. 7 and 8. In the drawings of the present embodiment, the same reference numerals are given to the same or equivalent portions as those in embodiment 1, and the description thereof is omitted.

The light emitting device 30 includes the optical semiconductor element 31 of the present invention. Fig. 7 is a plan view showing the structure of the light emitting device 30. Fig. 8 is a cross-sectional view taken along line 8-8 of fig. 7 of the light emitting device 30. First, the structure of the optical semiconductor element 31 will be described.

As in the case of example 1, the submount 12 is a flat plate-like substrate having a mounting surface, and is connected to an external circuit of the optical semiconductor element 31. As shown in fig. 8, the submount electrode 33 is an electrode pattern formed on the mounting surface of the submount 12, and is made of, for example, metal such as Ti, Pt, Au, Pd, Cr, Ni, Cu, W, and Al. The sub mount electrode 33 has 2 sub mount electrode pads 33a1 and 33a 2.

As shown in fig. 7, the sub-mount electrode tabs 33a1 and 33a2 each have a rectangular shape, and are arranged apart from each other. The outer edge 33E of the sub-mount electrode 33 is defined by a straight line connecting portions of the outer peripheries of the sub-mount electrode tabs corresponding to the outer peripheries of all the sub-mount electrode tabs 33a1 and 33a2 in the arrangement, and has a rectangular shape. That is, the sub mount electrode 33 has a rectangular shape as a whole.

The bonding layer 35 is a conductive bonding material formed on the submount electrode 33. As the bonding layer 35, for example, a conductive paste, a solder material, or the like, which is the same as the bonding layer 15 of example 1, can be used. In this embodiment, an example in which AuSn is used as the bonding layer 35 will be described. The bonding layer 35 is formed on the sub-mount pad 33a1 and on the sub-mount pad 33a2, respectively.

The chip electrode 37 is an electrode pattern provided on the bonding layer 35. The chip electrode 37 is bonded to the sub-mount electrode 33 via the bonding layer 35. Chip electrode 37 has 2 chip electrode pads 37B1 and 37B 2. The chip electrode pads 37B1 and 37B2 have shapes and arrangements that match the corresponding sub-mount electrode pads 33a1 and 33a2, respectively, except for the four corners of the sub-mount electrode 33, that is, except for the four corners of the outer edge 33E of the sub-mount electrode 33, and lack corners corresponding to the four corners of the sub-mount electrode 33. The 2 sub-mount electrode pads 33a1 and 33a2 and the 2 chip electrode pads 37B1 and 37B2B are matingly engaged with each other.

The 2 sub-mount electrode pads 33a1 and 33a2 have exposed surfaces 33S at 4 corners corresponding to four corners of the sub-mount electrode 33, that is, four corners of the outer edge 33E. As shown in fig. 7, the bonding layer 35 extends to all of the 4 exposed surfaces 33S. For example, as shown in fig. 8, the bonding layer 35 extends to cover the entire 2 exposed surfaces 33S of the sub-mount electrode tabs 33a 2.

The semiconductor structure layer 19 is disposed on the chip electrode 37. That is, the chip electrode 37 is an electrode pattern formed on the semiconductor structure layer 19. The semiconductor structure layer 19 is configured by stacking a p-type semiconductor layer 19A, an active layer (i.e., a light-emitting layer) 19B, and an n-type semiconductor layer 19C on the chip electrode 37 in this order from the p-type semiconductor layer 19A, the active layer (i.e., the light-emitting layer) 19B, and the n-type semiconductor layer 19C. As described above, the light-emitting layer 19B emits the outgoing light having a wavelength corresponding to the material and composition of the semiconductor structure layer 19.

The element substrate 38 is disposed on the semiconductor structure layer 19. The element substrate 38 is a growth substrate of the semiconductor structure layer 19. The element substrate 38 is a substrate having transparency to visible light, such as sapphire, SiC, or AlN. In this embodiment, an example in which an AlN single crystal substrate is used as the element substrate 38 is shown. As shown in fig. 8, the chip electrode 37, the semiconductor structure layer 19, and the element substrate 38 constitute a semiconductor chip 40.

As in the case of example 1, the optical semiconductor element 31 is mounted on the package substrate 22 via the feed adhesive 21. The conductive pads 23 are provided on the mounting surface of the package substrate 22 and serve as connection electrodes for connection to an external circuit. As in the case of example 1, the reflector 25 is provided on the package substrate 22, and the optical semiconductor element 31 is housed in the cavity 26 and packaged.

In addition, in the present embodiment, an example is shown in which the optical semiconductor element 31 is a flip-chip type LED element in which a semiconductor chip 40 formed by growing the semiconductor structure layer 19 on the element substrate 38 is flip-chip mounted.

As described above, the chip electrodes 37 are divided into the chip electrode pads 37B1 and 37B 2. Therefore, one of the die pads 37B1 and 37B2 can be electrically connected to the p-type semiconductor layer 19A, and the other can be electrically connected to the n-type semiconductor layer 19C.

For example, the energization pads 23 are provided as connection electrodes of 2 systems including a connection electrode electrically connected to the chip electrode pad 37B1 and the sub-mount electrode pad 33a1 joined to the chip electrode pad 37B1, and a connection electrode (not shown) electrically connected to the chip electrode pad 37B2 and the sub-mount electrode pad 33a2 joined to the chip electrode pad 37B2, whereby energization can be performed in the flip-chip type optical semiconductor element.

Thus, according to the present embodiment, even when the sub-mount electrode 33 and the chip electrode 37 each have 2 electrode pads, the exposed surface 33S of the chip electrode 37 can be provided at four corners of the outer edge 33E of the sub-mount electrode 33.

Further, by adopting the structure in which the bonding layer 35 extends to the exposed surface 33S, the optical semiconductor element 31 with less generation of voids can be provided. Therefore, an optical semiconductor element having a uniform current density, a good heat dissipation efficiency, and a long life, and a light-emitting device using the optical semiconductor element can be provided.

Further, it is possible to provide an optical semiconductor element and a light emitting device using the optical semiconductor element, which can secure parallelism with respect to the submount 12 when the semiconductor chip 40 is mounted, and can obtain designed light distribution characteristics and light emission output.

Fig. 9 is a plan view of an optical semiconductor element 31V1, which is a modification of the optical semiconductor element 31 of the present embodiment. As shown in fig. 9, the sub-mount electrode 33 has 2 sub-mount electrode pads 33a1 and 33a 2.

The chip electrode 37 has 2 chip electrode pads 37B1 and 37B2, and the 2 chip electrode pads 37B1 and 37B2 have shapes and configurations matching the corresponding sub-mount electrode pads 33a1 and 33a2 except for the four corners of the 2 sub-mount electrode pads, and lack corners corresponding to the respective four corners of the 2 sub-mount electrode pads. The 2 sub-mount electrode pads 33a1 and 33a2 have exposed surfaces 33S at the four corners, and the bonding layer 35 extends to the exposed surfaces 33S at all the four corners.

In the optical semiconductor element 31V1, the bonding layer 35 between the sub-mount pad 33a1 and the chip electrode 37B1 and the bonding layer 35 between the sub-mount pad 33a2 and the chip electrode 37B2 are each configured to reliably suppress the occurrence of an unbonded portion.

[ example 3 ]

A light-emitting device according to example 3 will be described with reference to fig. 10 to 12B. In this embodiment, the optical semiconductor element 41 is mounted on the package substrate 22, as in embodiment 2. The structure of the optical semiconductor element 41 will be described below. Fig. 10 is a plan view of the optical semiconductor element 41. Fig. 11 is a cross-sectional view taken along line 11-11 of fig. 10.

As shown in FIG. 10, the sub-mount electrode 33 has 1 st to n th (n.gtoreq.2) sub-mount electrode pads 33A1 to 33An (hereinafter, also referred to simply as "sub-mount electrode pads"). The sub-mounting electrode pads 33A1 to 33An have a stripe shape (elongated shape) and are arranged apart from each other. More specifically, the sub-mount electrode pads are arranged so as to be parallel to each other.

As shown in fig. 10, the outer edge 33E of the sub-mount electrode 33 is defined by a straight line connecting portions of the outer peripheries of the sub-mount electrode tabs corresponding to the outer peripheries of all the sub-mount electrode tabs 33a1 to 33An arranged in this manner, and has a rectangular shape. That is, the sub mount electrode 33 has a rectangular shape as a whole.

The bonding layer 35 is a conductive bonding material formed on the submount electrode 33. As the bonding layer 35, a conductive material such as conductive paste or solder can be used. In the present embodiment, an example in which bonding layer 35 is AuSn is explained.

A bonding layer 35 is formed along each of the sub-mount electrode pads 33A1 to 33 An. Further, as shown in fig. 11, the bonding layer 35 extends to both end portions of the submount electrode 33 An.

The chip electrode 37 is an electrode pattern provided on the bonding layer 35. The chip electrode 37 is bonded to the sub-mount electrode 33 via the bonding layer 35. The chip electrodes 37 are constituted by 1 st to nth chip electrode pads 37B1 to 37Bn (hereinafter, also simply referred to as "chip electrode pads"). In fig. 10, the die pad and the bonding layer 35 are shown with hatching for clarity.

As shown in fig. 10, the chip electrode pads 37B1 to 37Bn have shapes and arrangements matching the corresponding sub-mount electrode pads except for the four corners of the outer edge 33E of the sub-mount electrode 33, and have ends corresponding to the two ends of the 1 st and n-th sub-mount electrode pads.

Except for the four corners, the sub-mount electrode pads and the chip electrode pads are matched with each other and bonded via the bonding layer 35. The 1 st and n-th sub-mount electrode sheets have exposed surfaces 33S, which are portions exposed from the chip electrodes, at both ends thereof, and the bonding layer 35 extends to all of the exposed surfaces 33S.

The semiconductor structure layer 19 and the element substrate 38 are configured in the same manner as in embodiment 2. The chip electrode 37, the semiconductor structure layer 19, and the element substrate 38 constitute a semiconductor chip 42.

An example of a method for manufacturing the optical semiconductor element 41 will be described with reference to fig. 12A and 12B. Fig. 12A is a plan view showing a patch material (DA material) 35L arranged on the sub-mount 12, the sub-mount electrode 33, and the sub-mount electrode 33. The same material as the DA material 15L forming the bonding layer 35 of the optical semiconductor element 31 is preferable, and a material having conductivity and fluidity at the time of manufacturing is preferable, and for example, AuSn is used.

As shown in FIG. 12A, the DA material 35L is disposed in the center of each of the sub-mount electrode pads 33A 1-33 An of the sub-mount electrode 33. For example, the DA material 35L is disposed centering on a position having a distance equal to both end portions of each of the sub mount electrode pads having a stripe shape. With such a configuration, the DA material 35L is less likely to be involved in air during expansion, and an unbonded portion such as a void is less likely to be generated in the bonding layer 35.

Fig. 12B is a top view of the semiconductor chip 42. As shown in FIG. 12B, the chip electrodes 37 are formed in an electrode pattern having chip electrode pads 37B 1-37 Bn. Each of the chip electrode pads is formed in a shape and arrangement that matches the sub-mount electrode 33 when bonded to the sub-mount electrode 33 as described above. For convenience of explanation, fig. 12B shows the shape and position of the outer edge 33E of the sub-mount electrode 33.

The semiconductor chip 42 is mounted on the sub-mount electrode 33 on which the DA material 35L is arranged in a direction in which the chip electrode 37 is in contact with the DA material 35L. In this case, the semiconductor chips 42 are preferably placed in alignment so that the sub-mount electrode pads 33A1 to 33An are joined to the corresponding chip electrode pads 37B1 to 37Bn, except for the respective end portions of the sub-mount electrode pads.

After the semiconductor chip 42 is mounted, a load is applied to a position corresponding to the center of the outer edge 33E of the sub-mount electrode 33. When a load is thus applied, the DA material 35L wets and spreads along the sub-mount electrode pads and the chip electrode pads.

After applying a load to the semiconductor chip 42, a determination is made as to whether or not the DA material 35L extends to all the exposed surfaces 33S. For example, the determination can be performed by visual confirmation. This determination can be made, for example, by an inspection apparatus using inspection light having a wavelength region that is transparent to the element substrate 38 and the semiconductor structure layer 19.

In this determination, it is determined that the DA material 35L is acceptable when it extends to all the exposed surfaces 33S of the sub-mount electrode pads 33a1 and 33 An. If the DA material 35L does not extend to any.1 or more exposed surfaces 33S of all the exposed surfaces 33S, it is determined to be defective.

However, more detailed determination criteria may be provided. For example, among the exposed surfaces 33S, the DA material 35L may be regarded as being acceptable when extending over the entire surface, and among any 1 or more exposed surfaces 33S among the exposed surfaces 33S, the DA material 35L may be regarded as being unacceptable when extending only to a part of the exposed surface 33S. Further, the determination may be made by whether or not the degree of extension (projecting amount) of the DA material 35L on the exposed surfaces 33S is uniform among all the exposed surfaces 33S.

Thereafter, the non-defective product is heated in a reflow furnace to cure the DA material 35L to form the bonding layer 35, thereby completing the optical semiconductor element 31. As a non-defective product of this determination, the DA material 35L spreads between the sub-mount electrode 33 and the chip electrode 37 with a more uniform thickness without variation, and generation of an unbonded portion between the sub-mount electrode 33 and the chip electrode 37 such as a void is suppressed. In addition, it can be said that the non-defective product can ensure the flatness of the DA material 35L.

As described above, according to the present embodiment, even when the sub-mount electrode 33 and the chip electrode 37 each have a plurality of electrode pads, the sub-mount electrode 33 can have a structure in which the chip electrode 37 and the exposed surface 33S are provided at four corners thereof.

More specifically, the following structure can be adopted: a1 st to n th chip electrode sheets are provided, the 1 st to n th chip electrode sheets having shapes and arrangements matching the corresponding sub-mount electrode sheets except four corners of the outer edge 33E of the sub-mount electrode 33 of the sub-mount electrode sheets 33A1 to 33An having a stripe shape, and lacking end portions corresponding to both end portions of the 1 st and n th sub-mount electrode sheets.

Further, by adopting a structure in which the bonding layer 35 extends to the exposed surface 33S at both ends of the 1 st and n-th sub-mount electrode pads, the optical semiconductor element 41 in which the occurrence of unbonded portions such as voids is suppressed can be provided. Therefore, an optical semiconductor element having a uniform current density, a good heat dissipation efficiency, and a long life, and a light-emitting device using the optical semiconductor element can be provided.

Further, it is possible to secure parallelism with respect to the submount 12 when the semiconductor chip 40 is mounted, and it is possible to provide an optical semiconductor element capable of obtaining designed light distribution characteristics and light emission output, and a light emitting device using the optical semiconductor element.

[ example 4 ]

A light-emitting device of example 4 will be described with reference to fig. 13 to 14B. In this embodiment, the optical semiconductor element 43 is mounted on the package substrate 22, as in embodiments 2 and 3. The optical semiconductor element 43 is configured in the same manner as the optical semiconductor element 41 of example 3, except for the configuration of the die pad pieces 37B1 to 37 Bn. The structure of the optical semiconductor element 43 will be described below.

Fig. 13 is a plan view of the optical semiconductor element 43. The sub-mount electrodes 33 have sub-mount electrode pads 33A 1-33 An each having a stripe shape (elongated shape) and arranged separately from each other, as in example 3. A bonding layer 35 is formed along each of the sub-mount electrode pads 33A1 to 33 An. The chip electrode 37 is bonded to the submount electrode 33 via a bonding layer 35, and has chip electrode pads 37B 1-37 Bn.

As shown in fig. 13, the chip electrode pads 37B1 to 37Bn have shapes and arrangements matching the corresponding sub-mount electrode pads except for the respective end portions of the sub-mount electrodes 33a1 to 33An, and are devoid of end portions corresponding to the respective end portions of the corresponding sub-mount electrode pads. That is, the chip electrode pads other than the 1 st and n-th chip electrode pads 37 are also short of the end portions corresponding to the both end portions of the corresponding sub-mount electrode pads, respectively.

Except for the two end portions, the sub-mount electrode pads 33A1 to 33An and the chip electrode pads 37B1 to 37Bn are matched with each other and bonded via the bonding layer 35. Each sub-mount electrode sheet has an exposed surface 33S which is a portion exposed from the chip electrode at both ends, and the bonding layer 35 extends to all of the exposed surfaces 33S.

Thus, each of the chip electrode sheets may have a structure in which end portions corresponding to both end portions of each of the sub-mount electrode sheets are absent, and each of the sub-mount electrode sheets may have the exposed surface 33S at both end portions. Therefore, the optical semiconductor element 43 in which generation of unjoined portions such as voids is suppressed in the bonding layer 35 between each sub-mount electrode pad and each corresponding chip electrode pad can be provided.

In the optical semiconductor element 43, the adhesive layer 35 may extend over all of the four corners of the sub-mount electrode 33, regardless of whether it extends over all of the exposed surface 33S or partially. Also, the exposed surfaces 33S at both ends of all the sub-mount electrode sheets having the stripe shape may be extended in all or part of the exposed surfaces 33S, as long as the adhesive layer 35 is extended on the exposed surfaces 33S at both ends of all the sub-mount electrode sheets having the stripe shape.

Therefore, the adhesive layer 35 may extend entirely on the exposed surfaces 33S of the two end portions of all the sub-mount electrode sheets, and may partially extend on the remaining exposed surfaces 33S. Further, it is more preferable that the entire exposed surface 33S extends or the entire exposed surface 33S partially extends.

With reference to fig. 14A and 14B, determination of whether or not the DA material 35L extends to all the exposed surfaces 33S during the manufacture of the optical semiconductor element 43 will be described. Fig. 14A is a plan view showing an example of a state in which the chip electrode 37 is bonded to the sub-mount electrode 33 via the DA material 35L.

In fig. 14A, the DA material 35L extends to the exposed surface 33S, which is the portion exposed from the chip electrodes 37B1 to 37Bn, at all the opposite ends of the sub-mount pads 33a1 to 33 An. That is, the DA material 35L extends to the exposed surface 33S at all four corners of the sub-mount electrode 33. Therefore, in this case, the determination at the time of manufacturing is qualified as a rule.

However, in fig. 14A, in one end portion (in fig. 14A, a portion L surrounded by a broken line) of both end portions of each sub-mount electrode tab, the DA material 35L extends over the entire exposed surface 33S. At the other end portion of each sub-mount electrode sheet (in fig. 14A, the portion R surrounded by the broken line), the DA material 35L extends to a partial region of the exposed surface 33S, and the exposed surface 33S is exposed from the DA material 35L in the other region.

Accordingly, in the case where there is variation in the degree to which the DA material 35L extends on the exposed surface 33S, that is, in the case where the amount of projection of the DA material 35L from the chip electrode 37 is not uniform, it is considered that the chip electrode 37 is joined to the sub-mount electrode 33 by inclining the chip electrode 37 in the longitudinal direction of the stripe shape of the sub-mount electrode as compared with the case where the amount of extension is uniform. Therefore, it is considered that the DA material 35L is unevenly spread, and voids or the like may be generated. In this case, a determination criterion for determining that the vehicle is a failure may be set.

Fig. 14B is a plan view showing another example of a state in which the chip electrode 37 is bonded to the sub-mount electrode 33 via the DA material 35L. In fig. 14B, the DA material 35L extends to the exposed surface 33S at all the opposite end portions of the sub-mount electrode tabs 33a1 to 33 An. Therefore, as in the case of fig. 14A, the determination at the time of manufacture is qualified as a rule.

More specifically, however, the DA material 35L extends over the entire exposed surface 33S at both ends of the sub-mount electrode tabs 33a1 to 33 An-1. On the other hand, in both end portions of the n-th sub-mount electrode sheet 33An, the DA material 35L extends to a partial region of the exposed surface 33S, and in the other region, the exposed surface 33S is exposed from the DA material 35L.

In this case, the DA material 35L is not extended to the same extent on the exposed surface 33S, and the chip electrode 37 is inclined in a direction perpendicular to the long side of the stripe shape and is joined to the submount 12 and the submount electrode 33. In this case, a determination criterion for determining that the vehicle is a failure may be set.

[ example 5 ]

The structure of the light-emitting device 50 according to example 5 will be described with reference to fig. 15 to 18. The light-emitting device 50 includes the optical semiconductor element 51 of the present invention. Fig. 15 is a plan view showing the structure of the light-emitting device 50. Fig. 16 is a cross-sectional view taken along line 16-16 of fig. 15.

The sub-mount 52 has a mounting surface on which through holes 52A and 52B and wirings 53C and 53D are provided. In the through holes 52A and 52B, for example, metal plating or metal filling is performed to establish electrical conduction between the surfaces opposite to the mounting surfaces. The wirings 53C and 53D are connected to an external circuit via the through holes 52A and 52B.

As shown in fig. 16, the submount electrode 53 is an electrode pattern formed on the mounting surface of the submount 52, and is made of, for example, a metal such as Ti, Pt, Au, or Pd. The sub-mount electrode 53 includes a sub-mount electrode piece 53A and a sub-mount electrode piece 53B as a sub-mount-side opposite electrode.

The sub-mount electrode piece 53A is constituted by the 1 st to nth (n.gtoreq.2) sub-mount electrode pieces. In this embodiment, a case where n is 6 will be described. As shown in FIG. 16, the sub-mount electrode 53A is constituted by the 1 st to 6 th sub-mount electrode pads 53A1 to 53A 6.

As shown in fig. 15, the sub-mount electrode pads 53a1 to 53a6 each have a stripe shape (a long strip shape) and are arranged so as to be separated from each other. More specifically, the long sides of the sub-mount electrode pads 53a1 to 53a6 in the shape of stripes are arranged parallel to each other, and n rows are arranged.

The sub-mount electrode pieces 53B have a stripe shape, and are disposed apart from the sub-mount electrode pieces 53A in a direction perpendicular to the long sides of the sub-mount electrode pieces 53A1 to 53A 6.

As shown in fig. 15, the outer edge 53A of the sub-mount electrode 53A is defined by a straight line connecting portions of the outer peripheries of the sub-mount electrode pads corresponding to the outer peripheries of all the sub-mount electrode pads 53A1 to 53A6 in the arrangement, and has a rectangular shape. That is, the sub mount electrode 53A has a rectangular shape as a whole.

The bonding layer 55 includes a bonding layer 55A and a bonding layer 55B. A bonding layer 55A is formed along each of the sub-mount electrode pads 53A 1-53A 6. As shown in fig. 16, the bonding layer 55A extends to both end portions of each sub-mount electrode pad 53A. The bonding layers 55B are formed along the sub-mount electrode pads 53B, and the bonding layers 55B extend to both end portions of the sub-mount electrode pads 53B.

As in the above-described embodiments, as the bonding layer 55, a conductive material such as a conductive paste or a solder material can be used, and in the present embodiment, an example in which the bonding layer 55 is AuSn will be described.

The chip electrode 57 is an electrode pattern provided on the bonding layer 55, and is bonded to the submount electrode 53 via the bonding layer 55. For example, the chip electrode 57 may be formed by combining metals such as Ti, Al, Au, Ni, Cr, Ni, and Cu, or the chip electrode 57 may be formed by using metals such as Pt, W, and Pd.

The chip electrode 57 includes a chip electrode pad 57A and a chip electrode pad 57B as a chip-side opposite electrode. The die pad 57A is provided on the bonding layer 55A, and has 1 st to nth (n.gtoreq.2) die pads. In this embodiment, a case where n is 6 will be described.

As shown in fig. 15, the chip electrode 57A has 1 st to 6 th chip electrode pieces 57A1 to 57A6, and the 1 st to 6 th chip electrode pieces 57A1 to 57A6 have shapes and arrangements matching the corresponding sub-mount electrode pieces 53A except for both ends of the sub-mount electrode pieces 53A1 to 53A6, and have ends corresponding to both ends of the sub-mount electrode pieces 53A.

The chip electrode pad 57B is provided on the bonding layer 55B. For example, the chip electrode pieces 57B have a shape and an arrangement matching the sub-mount electrode pieces 53B except for both ends of the sub-mount electrode pieces 53B, and have a shape lacking end portions corresponding to both ends of the sub-mount electrode pieces 53B.

The sub-mount electrode pieces 53A and the chip electrode pieces 57A are fitted to each other except for both end portions of the sub-mount electrode pieces 53A, and are joined together via a joining layer 55A. Further, the sub-mount electrode pieces 53B and the chip electrode pieces 57B are matched with each other except for both end portions of the sub-mount electrode pieces 53B, and are joined via the joining layer 55B.

Each of the sub-mount electrode pads 53A and 53B has an exposed surface 53S exposed from each of the chip electrode pads at both ends of the stripe shape. In the present embodiment, the bonding layer 55A extends to all the exposed surfaces 53S of the sub-mount electrode sheet 53A, and the bonding layer 55B extends to 2 exposed surfaces 53S of the sub-mount electrode sheet 53B. That is, the bonding layer 55 extends to all the exposed surfaces 53.

The semiconductor structure layer 59 is disposed on the chip electrode 57. That is, the chip electrode 57 is an electrode pattern formed on the semiconductor structure layer 59. The semiconductor structure layer 59 is configured by stacking a p-type (1 st conductivity type) semiconductor layer 59A, an active layer (i.e., light-emitting layer) 59B, and an n-type (2 nd conductivity type) semiconductor layer 59C on the chip electrode 57 in this order from the p-type (1 st conductivity type) semiconductor layer 59A, the active layer (i.e., light-emitting layer) 59B, and the n-type (2 nd conductivity type) semiconductor layer 59C.

The wavelength of the outgoing light emitted from the light-emitting layer 59B is a wavelength corresponding to the material and composition of the semiconductor structure layer 59. In this embodiment, a case where the light-emitting layer 59B emits deep ultraviolet light having a wavelength in the deep ultraviolet region will be described.

The element substrate 38 is provided on the semiconductor structure layer 59, and is a substrate having transparency to visible light, such as sapphire, SiC, or AlN. In this embodiment, an example in which an AlN single crystal substrate is used for the element substrate 38 will be described.

As shown in fig. 16, the element substrate 38, the semiconductor structure layer 59, and the chip electrode 57 constitute a semiconductor chip 60. The optical semiconductor element 51 is a flip-chip type optical semiconductor element in which a semiconductor chip 60 formed by growing a semiconductor structure layer 59 on an element substrate 38 is mounted in an inverted state. In the optical semiconductor element 51, light from the light-emitting layer 59B is emitted from the upper surface of the element substrate 38. That is, the upper surface of the element substrate 38 constitutes a light emitting surface.

The optical semiconductor element 51 is mounted on the package substrate 22 via the power feeding adhesives 61A and 61B. The current-carrying pads 23A and 23B are provided on the mounting surface of the package substrate 22 and are connection electrodes to be connected to an external circuit. The package substrate 22 is provided with a reflector 25, and the optical semiconductor element 51 is housed in the cavity 26 and packaged.

Fig. 17 is an enlarged view of the semiconductor chip 60 in fig. 16, which is inverted upside down. An n-type semiconductor layer 59C, an active layer 59B, and a p-type semiconductor layer 59A are formed on the element substrate 38 in this order from the n-type semiconductor layer 59C, the active layer 59B, and the p-type semiconductor layer 59A.

An n-electrode layer 59CL is formed in a partial region on the n-type semiconductor layer 59C. The chip electrode pad 57B is formed on the n-electrode layer 59 CL. That is, the die pad 57B is electrically connected to the n-type semiconductor layer 59C via the n-electrode layer 59 CL.

A p-electrode layer 59AL is formed in a partial region on the p-type semiconductor layer 59A. The chip electrode pad 57A is formed on the p-electrode layer 59 AL. That is, the chip electrode pad 57A is electrically connected to the p-type semiconductor layer 59A via the p-electrode layer 59 AL. That is, the chip electrode pads 57A and 57B are pad electrodes in the semiconductor chip 60.

Fig. 18 is a plan view showing the p-electrode layer 59AL and the n-electrode layer 59CL of the semiconductor structure layer 59. For convenience of explanation, the shapes and the arrangements of the chip electrodes 57A and 57B are shown by broken lines in fig. 18. As shown in FIG. 15, the chip electrode 57A includes chip electrode pads 57A 1-57A 6.

As shown in fig. 18, the p-electrode layer 59AL has a portion perpendicular to the chip electrode 57A at an end opposite to the side where the chip electrode 57B is provided. The vertical portion connects the opposite ends of the portion of the p-electrode layer 59AL formed along the chip electrode 57A. Therefore, the p-electrode layer 59AL has a comb-tooth shape in which the vertical portion is a base portion and a portion formed along the chip electrode 57A is a comb-tooth portion.

The n-electrode layer 59CL has a portion extending from a portion formed along the chip electrode 57B to a gap between the chip electrodes 57A in parallel with the chip electrodes 57A. Therefore, the n-electrode layer 59CL has a comb-tooth shape in which a portion formed along the chip electrode 57B is a base portion and a portion extending to a gap between the chip electrodes 57A is a comb-tooth portion.

Thus, the p-electrode layer 59AL and the n-electrode layer 59CL have a comb-shaped structure, and a more uniform current density can be obtained. Therefore, the optical semiconductor element 51 has a structure in which the bonding layer 55 extends to all the exposed surfaces 53S, and thus it is possible to suppress damage of the uniform current density due to the comb tooth structure by the non-bonded portion such as the void.

As described above, according to the present embodiment, the optical semiconductor element 51 in which the bonding layer 55 extends to the exposed surface 53S at both ends of each of the sub-mount electrode pads 53A can be configured by using the semiconductor structure layer 59 having the electrode layer having the comb-tooth structure, and providing the sub-mount electrodes 53 and the chip electrodes 57 corresponding to the comb-tooth structure. That is, the chip electrode corresponding to the comb-tooth structure and the sub-mount electrode may be bonded to each other by the bonding layer 55 having a small number of unbonded portions such as voids. Therefore, a more uniform current density can be obtained, and a longer lifetime of the optical semiconductor element can be provided. Further, flatness of the bonding layer 55 can be ensured, and the designed light distribution characteristics and light emission output can be obtained.

In the above-described embodiment, the structure in which the chip electrode lacks a predetermined position was described, but an insulating protective film may be provided in order to prevent a portion not covered with the chip electrode from coming into contact with the conductive bonding layer and causing a short circuit.

The configurations shown in the above-described embodiments are merely examples, and can be selected, combined, and changed according to the application and the like. For example, conditions such as the shape of the sub-mount electrode and the chip electrode used in the optical semiconductor element of the present invention, and the position of the portion where the chip electrode is missing can be appropriately selected according to the type of the semiconductor chip used, and the like.

As described above, according to the present invention, it is possible to provide an optical semiconductor element having a small number of unbonded portions between an electrode provided on the optical semiconductor chip side and an electrode provided on the submount side, high heat dissipation efficiency, and a long life. Further, it is possible to provide an optical semiconductor element in which the flatness of the bonding layer between the electrode provided on the optical semiconductor chip side and the electrode provided on the submount side is high, and the designed light distribution characteristics and light emission output can be obtained.