阅读说明：本技术 双生存储器单元互连结构 (Twin memory cell interconnect structure ) 是由 F·拉罗萨 S·尼埃尔 A·雷尼耶 于 2015-11-26 设计创作，主要内容包括：本发明涉及双生存储器单元互连结构。一种非易失性存储器(MEM1)包括存储器单元(C1,j)的行和列,存储器单元的列包括成对的双生存储器单元(C1,j、C2,j1),双生存储器单元包括共用的选择栅极(CSG1,2)。根据本发明,存储器单元的每列设置有两个位线(B1,j、B2,j+1)。相同列的相邻的双生存储器单元没有连接到相同的位线,而相同列的非双生存储器单元连接到相同的位线。(The invention relates to a twin memory cell interconnect structure. A non-volatile memory (MEM1) includes rows and columns of memory cells (C1, j), the columns of memory cells including pairs of twin memory cells (C1, j, C2, j1), the twin memory cells including a common select gate (CSG1, 2). According to the invention, each column of memory cells is provided with two bit lines (B1, j, B2, j + 1). Adjacent twin memory cells of the same column are not connected to the same bit line, while non-twin memory cells of the same column are connected to the same bit line.)

1. A non-volatile memory, comprising:

a first twin pair of memory cells, the first twin pair comprising a first memory cell and a second memory cell arranged along a first column, the first and second memory cells each comprising a respective select transistor and a respective floating gate transistor, the select transistors of the first twin pair having respective gate terminals coupled to each other;

a second twin pair of memory cells, the second twin pair comprising a third memory cell and a fourth memory cell arranged along a second column, the third memory cell being adjacent to the first memory cell, the fourth memory cell being adjacent to the second memory cell, the third and fourth memory cells each comprising a respective select transistor and a respective floating gate transistor, the select transistors of the second twin pair having respective gate terminals coupled to each other;

a first bit line coupled to a conductive terminal of a floating gate transistor of the first memory cell;

a second bit line coupled to a conductive terminal of a floating gate transistor of the second memory cell;

a third bit line coupled to a conductive terminal of a floating gate transistor of the third memory cell;

a fourth bit line coupled to a conductive terminal of a floating gate transistor of the fourth memory cell, the first, second, third, and fourth bit lines being different from one another; and

a first word line coupled to gate terminals of select transistors of the first and second twinned pairs.

2. The non-volatile memory as in claim 1, comprising:

a third twinned pair of memory cells, the third twinned pair including a fifth memory cell and a sixth memory cell arranged along the first column, the fifth and sixth memory cells each including a respective select transistor and a respective floating gate transistor, the select transistors of the third twinned pair having respective gate terminals coupled to each other;

a fourth twinned pair of memory cells, the fourth twinned pair including a seventh memory cell and an eighth memory cell arranged along the second column, the seventh memory cell being adjacent to the fifth memory cell, the eighth memory cell being adjacent to the sixth memory cell, the seventh memory cell and the eighth memory cell each including a respective select transistor and a respective floating gate transistor, the select transistors of the fourth twinned pair having respective gate terminals coupled to each other; and

a second word line coupled to gate terminals of select transistors of the third and fourth twinned pairs,

wherein the first bit line is coupled to a conductive terminal of a floating gate transistor of the sixth memory cell, the second bit line is coupled to a conductive terminal of a floating gate transistor of the fifth memory cell, the third bit line is coupled to a conductive terminal of a floating gate transistor of the eighth memory cell, and the fourth bit line is coupled to a conductive terminal of a floating gate transistor of the seventh memory cell.

3. The non-volatile memory of claim 2, comprising:

a first gate control line coupled to respective control gates of the floating gate transistors of the first and third memory cells;

a second gate control line coupled to respective control gates of the floating gate transistors of the second and fourth memory cells;

a third gate control line coupled to respective control gates of the floating gate transistors of the fifth and seventh memory cells; and

a fourth gate control line coupled to respective control gates of the floating gate transistors of the sixth and eighth memory cells.

4. The non-volatile memory as in claim 2, wherein the first bit line, the second bit line, and the third bit line are arranged on the first column of memory cells, and the fourth bit line is arranged on the second column of memory cells.

5. The non-volatile memory of claim 2, comprising:

an electrically isolating layer between the memory cell and the first through fourth bit lines;

a first conductive path coupling the first bit line to conductive terminals of floating gate transistors of the first and sixth memory cells, the first conductive path routed through at least a portion of the electrically isolated layer;

a second conductive path coupling the second bit line to conductive terminals of floating gate transistors of the second and fifth memory cells, the second conductive path routed through at least a portion of the electrically isolated layer;

a third conductive path coupling the third bit line to conductive terminals of floating gate transistors of the third and eighth memory cells, the third conductive path routed through at least a portion of the electrically isolated layer; and

a fourth conductive path coupling the fourth bit line to conductive terminals of floating gate transistors of the fourth and seventh memory cells, the fourth conductive path routed through at least a portion of the electrically isolated layer.

6. The non-volatile memory of claim 5, the electrically isolated layers comprising a first isolated layer, a second isolated layer, a third isolated layer, a fourth isolated layer, and a fifth isolated layer, wherein:

the first bit line extends over the second isolation layer;

the second bit line extends over the third isolation layer;

the third bit line extends over the fifth isolation layer; and

the fourth bit line extends over the fifth isolation layer.

7. The non-volatile memory of claim 6, the first conductive path comprising:

a first via extending through the first isolation layer;

a first partial conductive line on the first isolation layer and extending in a direction parallel to the memory cells of the first column; and

a second via extending through the second isolation layer.

8. The non-volatile memory of claim 6, the second conductive path comprising:

a first via extending through the first isolation layer;

a first partial conductive line on the first isolation layer and extending in a direction perpendicular to the memory cells of the first column and the memory cells of the second column;

a second via extending through the second isolation layer;

a second partial conductive line on the second isolation layer and extending in a direction parallel to the second column of memory cells;

a third via extending through the third isolation layer; and

a third partial conductive line on the third isolation layer and extending in a direction perpendicular to the memory cells of the first column and the memory cells of the second column.

9. The non-volatile memory of claim 6, the third conductive path comprising:

a first via extending through the first isolation layer;

a first partial conductive line on the first isolation layer and extending in a direction parallel to the second column of memory cells;

a second via extending through the second isolation layer;

a second partial conductive line on the second isolation layer and extending in a direction parallel to the second column of memory cells;

a third via extending through the third isolation layer;

a third partial conductive line on the third isolation layer and extending in a direction parallel to the second column of memory cells;

a fourth via extending through the fourth isolation layer;

a fourth portion conductive line on the fourth isolation layer and extending in a direction perpendicular to the memory cells of the first column and the memory cells of the second column; and

a fifth via extending through the fifth isolation layer.

10. The non-volatile memory of claim 6, the fourth conductive path comprising:

a first via extending through the first isolation layer;

a first partial conductive line on the first isolation layer and extending in a direction parallel to the second column of memory cells;

a second via extending through the second isolation layer;

a second partial conductive line on the second isolation layer and extending in a direction parallel to the second column of memory cells;

a third via extending through the third isolation layer;

a third partial conductive line on the third isolation layer and extending in a direction parallel to the second column of memory cells;

a fourth via extending through the fourth isolation layer;

a fourth portion conductive line on the fourth isolation layer and extending in a direction perpendicular to the memory cells of the first column and the memory cells of the second column; and

a fifth via extending through the fifth isolation layer.

11. The non-volatile memory of claim 1, further comprising read circuitry and a column decoder configured to read the memory cells.

12. A method, comprising:

forming a first memory cell and a second memory cell along a first column, the first memory cell and the second memory cell each including a respective select transistor and a respective floating gate transistor;

coupling respective gate terminals of select transistors of the first and second memory cells to each other;

forming a third memory cell and a fourth memory cell along a second column adjacent to the first column, the third memory cell and the fourth memory cell each including a respective select transistor and a respective floating gate transistor;

coupling respective gate terminals of select transistors of the third and fourth memory cells to each other;

forming a first bit line, a second bit line, a third bit line, and a fourth bit line, the first bit line, the second bit line, the third bit line, and the fourth bit line being different from one another;

coupling the first bit line to a conductive terminal of a floating gate transistor of the first memory cell;

coupling the second bit line to a conductive terminal of a floating gate transistor of the second memory cell;

coupling the third bit line to a conductive terminal of a floating gate transistor of the third memory cell; and

coupling the fourth bit line to a conductive terminal of a floating gate transistor of the fourth memory cell.

13. The method of claim 12, further comprising:

coupling a first word line to gate terminals of select transistors of the first, second, third, and fourth memory cells.

14. The method of claim 13, further comprising:

forming a fifth memory cell and a sixth memory cell along the first column, the fifth memory cell and the sixth memory cell each including a respective select transistor and a respective floating gate transistor, the fifth memory cell being adjacent to the second memory cell along the first column;

coupling respective gate terminals of select transistors of the fifth and sixth memory cells to each other;

forming a seventh memory cell and an eighth memory cell along the second column, the seventh memory cell and the eighth memory cell each including a respective select transistor and a respective floating gate transistor, the seventh memory cell being adjacent to the fourth memory cell along the second column;

coupling respective gate terminals of select transistors of the seventh and eighth memory cells to each other;

coupling the first bit line to a conductive terminal of a floating gate transistor of the sixth transistor;

coupling the second bit line to a conductive terminal of a floating gate transistor of the fifth memory cell;

coupling the third bit line to a conductive terminal of a floating gate transistor of the eighth memory cell; and

coupling a second word line to gate terminals of select transistors of the fifth, sixth, seventh, and eighth memory cells.

15. The method of claim 12, further comprising:

forming a first isolation layer, a second isolation layer, a third isolation layer, a fourth isolation layer and a fifth isolation layer;

forming the first bit line on the second isolation layer, the first bit line being arranged on the memory cells of the first column;

forming the second bit line on the third isolation layer, the second bit line being arranged on the memory cells of the second column;

forming the third bit line on the fifth isolation layer, the third bit line being arranged on the memory cells of the first column; and

forming the fourth bit line on the fifth isolation layer, the fourth bit line being arranged on the memory cells of the second column.

16. A non-volatile memory, comprising:

a first column of memory cells, the first column including a first memory cell and a second memory cell, the first memory cell and the second memory cell each including a respective select transistor and a respective floating gate transistor, the select transistors of the first memory cell and the second memory cell having respective gate terminals coupled to each other;

a second column of memory cells, the second column including a third memory cell and a fourth memory cell, the third memory cell being adjacent to the first memory cell, the fourth memory cell being adjacent to the second memory cell, the third memory cell and the fourth memory cell each including a respective select transistor and a respective floating gate transistor, the select transistors of the third memory cell and the fourth memory cell having respective gate terminals coupled to each other;

a first bit line coupled to a conductive terminal of a floating gate transistor of the first memory cell;

a second bit line coupled to a conductive terminal of a floating gate transistor of the second memory cell;

a third bit line coupled to a conductive terminal of a floating gate transistor of the third memory cell; and

a fourth bit line coupled to a conductive terminal of a floating gate transistor of the fourth memory cell, the first, second, third, and fourth bit lines being different from one another.

17. The non-volatile memory as in claim 16, wherein the first bit line, the second bit line, the third bit line are arranged on the first column of memory cells and the fourth bit line is arranged on the second column of memory cells.

18. The non-volatile memory as in claim 17, comprising:

a fifth memory cell and a sixth memory cell arranged along the first column, the fifth memory cell and the sixth memory cell each including a respective select transistor and a respective floating gate transistor, the select transistors of the fifth memory cell and the sixth memory cell having respective gate terminals coupled to each other;

a seventh memory cell and an eighth memory cell arranged along the second column, the seventh memory cell being adjacent to the fifth memory cell, the eighth memory cell being adjacent to the sixth memory cell, the seventh memory cell and the eighth memory cell each including a respective select transistor and a respective floating gate transistor, the select transistors of the seventh memory cell and the eighth memory cell having respective gate terminals coupled to each other,

wherein the first bit line is coupled to a conductive terminal of a floating gate transistor of the sixth memory cell, the second bit line is coupled to a conductive terminal of a floating gate transistor of the fifth memory cell, the third bit line is coupled to a conductive terminal of a floating gate transistor of the eighth memory cell, and the fourth bit line is coupled to a conductive terminal of a floating gate transistor of the seventh memory cell.

19. The non-volatile memory as in claim 18, comprising:

a first gate control line coupled to respective control gates of the floating gate transistors of the first and third memory cells;

a second gate control line coupled to respective control gates of the floating gate transistors of the second and fourth memory cells;

a third gate control line coupled to respective control gates of the floating gate transistors of the fifth and sixth memory cells; and

a fourth gate control line coupled to respective control gates of the floating gate transistors of the sixth and eighth memory cells.

20. The non-volatile memory as in claim 18, comprising:

an electrically isolating layer between the memory cell and the first through fourth bit lines;

a first conductive path coupling the first bit line to conductive terminals of floating gate transistors of the first and sixth memory cells, the first conductive path routed through at least a portion of the electrically isolated layer;

a second conductive path coupling the second bit line to conductive terminals of floating gate transistors of the second and fifth memory cells, the second conductive path routed through at least a portion of the electrically isolated layer;

a third conductive path coupling the third bit line to conductive terminals of floating gate transistors of the third and eighth memory cells, the third conductive path routed through at least a portion of the electrically isolated layer; and

a fourth conductive path coupling the fourth bit line to conductive terminals of floating gate transistors of the fourth and seventh memory cells, the fourth conductive path routed through at least a portion of the electrically isolated layer.

21. A non-volatile memory, comprising:

a first twin pair of memory cells, the first twin pair comprising a first memory cell and a second memory cell arranged along a first column, the first and second memory cells each comprising a respective select transistor and a respective floating gate transistor, the select transistors of the first twin pair having respective gate terminals coupled to each other;

a second twin pair of memory cells, the second twin pair comprising a third memory cell and a fourth memory cell arranged along the first column, the third memory cell being adjacent to the second memory cell, the third memory cell and the fourth memory cell each comprising a respective select transistor and a respective floating gate transistor, the select transistors of the second twin pair having respective gate terminals coupled to each other;

a first bit line coupled to conductive terminals of floating gate transistors of the first and fourth memory cells;

a second bit line coupled to conductive terminals of floating gate transistors of the second and third memory cells;

a first word line coupled to gate terminals of the first double-generation pair of select transistors; and

a second word line coupled to gate terminals of the second dyadic pair of select transistors.

22. The non-volatile memory as in claim 21, comprising:

a third twinned pair of memory cells, the third twinned pair including a fifth memory cell and a sixth memory cell arranged along a second column, the fifth and sixth memory cells each including a respective select transistor and a respective floating gate transistor, the select transistors of the third twinned pair having respective gate terminals coupled to each other;

a fourth twinned pair of memory cells, the fourth twinned pair including a seventh memory cell and an eighth memory cell arranged along the second column, the seventh memory cell being adjacent to the sixth memory cell, the seventh memory cell and the eighth memory cell each including a respective select transistor and a respective floating gate transistor, the select transistors of the fourth twinned pair having respective gate terminals coupled to each other; and

a third word line coupled to conductive terminals of floating gate transistors of the fifth and eighth memory cells; and

a fourth word line coupled to conductive terminals of the floating gate transistors of the sixth memory cell and the seventh memory cell.

23. The non-volatile memory as in claim 22, comprising:

a first gate control line coupled to respective control gates of the floating gate transistors of the first and fifth memory cells;

a second gate control line coupled to respective control gates of the floating gate transistors of the second and sixth memory cells;

a third gate control line coupled to respective control gates of the floating gate transistors of the third and seventh memory cells; and

a fourth gate control line coupled to respective control gates of the floating gate transistors of the fourth and eighth memory cells.

24. The non-volatile memory of claim 22, wherein the first bit line, the second bit line, and the third bit line are arranged along a first plane extending perpendicular to the first column of memory cells, and the fourth bit line is arranged along a second plane extending perpendicular to the second column of memory cells.

25. The non-volatile memory as in claim 22, comprising:

an electrically isolating layer between the memory cell and the first through fourth bit lines;

a first conductive path coupling the first bit line to conductive terminals of floating gate transistors of the first and fourth memory cells, the first conductive path routed through at least a portion of the electrically isolated layer;

a second conductive path coupling the second bit line to conductive terminals of floating gate transistors of the second and third memory cells, the second conductive path routed through at least a portion of the electrically isolated layer;

a third conductive path coupling the third bit line to conductive terminals of floating gate transistors of the fifth and eighth memory cells, the third conductive path routed through at least a portion of the electrically isolated layer; and

a fourth conductive path coupling the fourth bit line to conductive terminals of floating gate transistors of the sixth and seventh memory cells, the fourth conductive path routed through at least a portion of the electrically isolated layer.

26. The non-volatile memory of claim 25, the electrically isolated layers comprising a first isolated layer, a second isolated layer, a third isolated layer, a fourth isolated layer, and a fifth isolated layer, wherein:

the first bit line extends over the second isolation layer;

the second bit line extends over the third isolation layer;

the third bit line extends over the fifth isolation layer; and

the fourth bit line extends over the fifth isolation layer.

27. The non-volatile memory of claim 26, the first conductive path comprising:

a first via extending through the first isolation layer;

a first partial conductive line on the first isolation layer and extending along the first plane in a direction parallel to the memory cells of the first column; and

a second via extending through the second isolation layer.

28. The non-volatile memory of claim 26, the second conductive path comprising:

a first via extending through the first isolation layer;

a first partial conductive line on the first isolation layer and extending from the first plane to the second plane;

a second via extending through the second isolation layer;

a second partial conductive line on the second isolation layer and extending along the second plane in a direction parallel to the second column of memory cells;

a third via extending through the third isolation layer; and

a third partial conductive line on the third isolation layer and extending from the second plane to the first plane.

29. The non-volatile memory of claim 26, the third conductive path comprising:

a first via extending through the first isolation layer;

a first partial conductive line on the first isolation layer and extending along the second plane in a direction parallel to the second column of memory cells;

a second via extending through the second isolation layer;

a second partial conductive line on the second isolation layer and extending along the second plane in a direction parallel to the second column of memory cells;

a third via extending through the third isolation layer;

a third partial conductive line on the third isolation layer and extending along the second plane in a direction parallel to the second column of memory cells;

a fourth via extending through the fourth isolation layer;

a fourth portion of conductive lines on the fourth isolation layer and extending from the second plane to the first plane; and

a fifth via extending through the fifth isolation layer.

30. The non-volatile memory of claim 26, the fourth conductive path comprising:

a first via extending through the first isolation layer;

a first partial conductive line on the first isolation layer and extending along the second plane in a direction parallel to the second column of memory cells;

a second via extending through the second isolation layer;

a second partial conductive line on the second isolation layer and extending along the second plane in a direction parallel to the second column of memory cells;

a third via extending through the third isolation layer;

a third partial conductive line on the third isolation layer and extending along the second plane in a direction parallel to the second column of memory cells;

a fourth via extending through the fourth isolation layer;

a fourth portion of conductive lines on the fourth isolation layer and extending from the second plane to the first plane; and

a fifth via extending through the fifth isolation layer.

31. The non-volatile memory of claim 21, further comprising read circuitry and a column decoder configured to read the memory cells.

32. A method, comprising:

fabricating a non-volatile memory on a semiconductor substrate, the memory comprising a pair of twin memory cells, each memory cell comprising a floating gate transistor and a select transistor, the select transistor comprising a select gate in common with the select transistor of the twin memory cell, the method comprising:

forming a first column of memory cells and a second column of memory cells, including each of the pair of twin memory cells;

forming a first bitline aligned on a first bitline axis extending over a memory cell of the first column;

coupling the first bit line to a floating gate transistor of a non-twin memory cell of the first column through a first conductive path;

forming a second bitline aligned on the first bitline axis;

coupling the second bit line to floating gate transistors of other non-twin memory cells of the first column through a second conductive path;

forming a third bitline aligned on the first bitline axis;

coupling the third bit line to floating gate transistors of non-twin memory cells of the second column through a third conductive path;

forming a fourth bitline aligned on a second bitline axis extending over the second column of memory cells; and

coupling the fourth bit line to floating gate transistors of other non-twin memory cells of the second column through a fourth conductive path.

33. The method of claim 32, further comprising:

forming a first isolation layer, a second isolation layer, a third isolation layer, a fourth isolation layer and a fifth isolation layer;

forming the first bit line on the second isolation layer;

forming the second bit line on the third isolation layer;

forming the third bit line on the fifth isolation layer; and

forming the fourth bit line on the fifth isolation layer.

34. The method of claim 32, further comprising:

forming the first conductive path by forming a via through a first isolation layer aligned on the first bitline axis,

forming a conductive line portion aligned on the first bitline disposed on the first isolation layer, an

Forming a via aligned on the first bitline axis through the second isolation layer.

35. The method of claim 32, further comprising:

forming the second conductive path by forming a via through the first isolation layer aligned on the first bitline axis,

forming a conductive line portion extending from the first bobbin up to the second bobbin and disposed on the first isolation layer,

forming a via through the second isolation layer aligned on the second bit line axis,

forming a conductive line portion disposed on the second isolation layer aligned on the second bobbin,

forming a via through a third isolation layer aligned on the second bit line axis, an

Forming a conductive line portion disposed on the third isolation layer extending from the second bobbin up to the first bobbin.

36. The method of claim 32, further comprising:

forming the third conductive path by forming a via through the first isolation layer aligned on the second bit line axis,

forming a conductive line portion disposed on the first isolation layer aligned on the first bitline axis,

forming a via through the second isolation layer aligned on the second bit line axis,

forming a conductive line portion disposed on the second isolation layer aligned on the second bobbin,

forming a via aligned on the second bit line axis through the third isolation layer,

forming a conductive line portion disposed on the third isolation layer aligned on the second bobbin,

forming a via aligned on the second bit line axis through a fourth isolation layer,

forming a conductive line portion extending from the second bobbin up to the first bobbin disposed on the fourth isolation layer; and

forming a via aligned on the first bitline axis through a fifth isolation layer.

37. The method of claim 32, further comprising:

forming the third conductive path by forming a via through the first isolation layer aligned on the second bit line axis,

forming a conductive line portion disposed on the first isolation layer aligned on the first bitline axis,

forming a via through the second isolation layer aligned on the second bit line axis,

forming a conductive line portion disposed on the second isolation layer aligned on the second bobbin,

forming a via aligned on the second bit line axis through the third isolation layer,

forming a conductive line portion disposed on the third isolation layer aligned on the second bobbin,

forming a via aligned on the second bit line axis through a fourth isolation layer,

forming a conductive line portion disposed on the fourth isolation layer; and

forming a via aligned on the second bit line axis through a fifth isolation layer.

38. A non-volatile memory, comprising:

a first twin pair of memory cells, the first twin pair comprising a first memory cell and a second memory cell arranged along a first column, the first memory cell and the second memory cell each comprising a respective select transistor and a respective floating gate transistor, the select transistors of the first twin pair having respective gate transistors coupled to each other;

a second twin pair of memory cells, the second twin pair comprising a third memory cell and a fourth memory cell arranged along the first column, the third memory cell being adjacent to the second memory cell, the third memory cell and the fourth memory cell each comprising a respective select transistor and a respective floating gate transistor, the select transistors of the second twin pair having respective gate terminals coupled to each other;

a third twinned pair of memory cells, the third twinned pair including a fifth memory cell and a sixth memory cell arranged along a second column, the fifth and sixth memory cells each including a respective select transistor and a respective floating gate transistor, the select transistors of the third twinned pair having respective gate terminals coupled to each other;

a fourth twinned pair of memory cells, the fourth twinned pair including a seventh memory cell and an eighth memory cell arranged along the second column, the seventh memory cell being adjacent to the sixth memory cell, the seventh memory cell and the eighth memory cell each including a respective select transistor and a respective floating gate transistor, the select transistors of the fourth twinned pair having respective gate terminals coupled to each other;

a first bit line coupled to conductive terminals of floating gate transistors of the first and fourth memory cells;

a second bit line coupled to conductive terminals of floating gate transistors of the second and third memory cells;

a third word line coupled to conductive terminals of floating gate transistors of the fifth and eighth memory cells; and

a fourth word line coupled to conductive terminals of floating gate transistors of the sixth memory cell and the seventh memory cell,

wherein the first bit line, the second bit line, and the third bit line are arranged along a first plane extending perpendicular to the first column of memory cells, and the fourth bit line is arranged along a second plane extending perpendicular to the second column of memory cells.

39. The non-volatile memory as in claim 38, comprising:

a first gate control line coupled to respective control gates of the floating gate transistors of the first and fifth memory cells;

a second gate control line coupled to respective control gates of the floating gate transistors of the second and sixth memory cells;

a third gate control line coupled to respective control gates of the floating gate transistors of the third and seventh memory cells; and

a fourth gate control line coupled to respective control gates of the floating gate transistors of the fourth and eighth memory cells.

40. The non-volatile memory as in claim 38, comprising:

an electrically isolating layer between the memory cell and the first through fourth bit lines;

a first conductive path coupling the first bit line to conductive terminals of floating gate transistors of the first and fourth memory cells, the first conductive path routed through at least a portion of the electrically isolated layer;

a second conductive path coupling the second bit line to conductive terminals of floating gate transistors of the second and third memory cells, the second conductive path routed through at least a portion of the electrically isolated layer;

a third conductive path coupling the third bit line to conductive terminals of floating gate transistors of the fifth and eighth memory cells, the third conductive path routed through at least a portion of the electrically isolated layer; and

a fourth conductive path coupling the fourth bit line to conductive terminals of floating gate transistors of the sixth and seventh memory cells, the fourth conductive path routed through at least a portion of the electrically isolated layer.

Technical Field

The present invention relates to memories, and more particularly to twin memory cell interconnect structures.

Background

Figure 1 shows the Chinese herbal medicineMemory cell M of the type described in national patent application 20130228846_i，j、M_i，j+1、M_i-1，j、M_i-1，j+1Memory plane (plane) structure MA 0. Rank (rank) 'i' memory cell M_i，j、M_i，j+1Physical page PG belonging to a memory plane_iAnd connected to word lines WL_i-1，iAnd gate control line CGL_i. Memory cells M of rank' i-1_i-1，j、M_i-1，j+1Physical page PG belonging to rank 'i-1' of a memory plane_i-1And connected to word lines WL_i-1，iAnd gate control line CGL_i-1. Memory cells M of rank' j_i，j、M_i-1，jCan be passed through bit line B_jRead-write access, and memory cell M of rank' j-1_i，j+1、M_i-1，j+1Can be passed through bit line B_j+1And (4) reading and writing access.

Each memory cell includes a floating gate transistor (FG), respectively T_i，j、T_i，j+1、T_i-1，j、T_i-1j+1. Transistor T_i，j、T_i-1，jIs connected to a bit line B_jAnd a transistor T_i，j+1、T_i-1，j+1Is connected to bit line B_j+1. Transistor T_i，j、T_i，j+1Is connected to a gate control line CGL_iAnd a floating gate transistor T_i-1，j、T_i-1，j+1Is connected to a gate control line CGL_i-1。

Each floating gate transistor has its source (S) terminal connected to a source line via a select transistor ST. Memory cell M_i，jAnd M_i-1，jThe select transistor ST of (1) has a common select gate CSG and the two memory cells are accordingly referred to as 'twin'. Similarly, memory cell M_i，j+1And M_i-1，j+1Are twin memory cells and their select transistors ST have a common select gate CSG. Each select gate CGS is a vertical gate buried in the substrate in which the memory plane MA0 is embedded, and the source lines SL are likewise buriedIn (1). These common select gates CSG of the twin memory cells are connected to a word line WL_i-1，i。

Such memory cells can be erased or programmed via the channel by subjecting the substrate to a positive erase or negative program voltage, causing charge to be extracted from or injected into their floating gates by Fowler-Nordheim effect. More specifically, erasing a memory cell is implemented by combining a positive voltage applied to the substrate with a negative voltage applied to the control gate of its floating gate transistor, while the control gate of the floating gate transistor of a twin memory cell receives a positive erase inhibit voltage for preventing it from being erased simultaneously. Similarly, programming a memory cell may be performed by combining a negative voltage applied to the relevant bit line and substrate with a positive voltage applied to the control gate of its floating gate transistor, while the control gate of the floating gate transistor of a twin memory cell receives a negative program inhibit voltage for preventing it from being programmed simultaneously. The memory cell can also be programmed by hot electron injection by causing a current to flow in the bitline.

Finally, the memory cell is read by applying a positive voltage to the control gate CG of its floating gate transistor and a positive voltage to the corresponding bit line, while the twin memory cell connected to the same bit line receives a negative read inhibit voltage on its control gate for preventing it from being read simultaneously (fig. 9 of the aforementioned application).

Thus, the conventional memory plane structure including the twin memory cells needs to provide a word line decoder capable of applying a positive read voltage to the memory cell that needs to be read while applying a negative voltage read inhibit voltage to its twin memory cell.

Disclosure of Invention

It may be desirable to improve the memory plane structure and the twin memory cell so that it can be read without applying a negative read inhibit voltage to the twin memory cell.

Embodiments of the invention relate to a non-volatile memory on a semiconductor substrate, comprising rows and columns of memory cells, the columns of memory cells comprising pairs of twin memory cells, each twin memory cell comprising a floating gate transistor and a select transistor, the select transistor comprising a select gate common to the select transistors of the twin memory cells; bit lines, each bit line connected to conductive terminals of floating gate transistors of memory cells of the same column; a gate control line, transverse to the bit line, connected to the control gates of the floating gate transistors of the same row; and two bit lines per column of memory cells, and wherein two adjacent twin memory cells of the same column are not connected to the same bit line, and two adjacent non-twin memory cells of the same column are connected to the same bit line.

According to one embodiment, the memory comprises, for two adjacent columns of memory cells: three bit lines arranged and superimposed over a first column of memory cells and on three different interconnect levels; and a fourth bit line disposed over the second column of memory cells.

According to one embodiment, a memory includes: a first bit line arranged on the first bit line axis, extending over the first column of memory cells, and connected to the floating gate transistors of the first column by a first conductive path, the first conductive path including a via passing through the isolation layer and a portion of the conductive line disposed on the isolation layer; a second bit line arranged on the first bit line axis and connected to the floating gate transistors of the first column through a second conductive path including a via passing through the isolation layer and a portion of the conductive line disposed on the isolation layer; a third bit line arranged on the first bit line axis and connected to the floating gate transistors of the second column of memory cells by a third conductive path, the third conductive path including a via passing through the isolation layer and a portion of the conductive line disposed on the isolation layer; and a fourth bit line arranged on the second bit line axis, extending over the second column of memory cells, and connected to the floating gate transistor by a fourth conductive path including a via passing through the isolation layer and a portion of the conductive line disposed on the isolation layer.

According to one embodiment, a memory includes a first isolation layer, a second isolation layer, a third isolation layer, a fourth isolation layer, and a fifth isolation layer, a first bit line extending over the second isolation layer, a second bit line extending over the third isolation layer, a third bit line extending over the fifth isolation layer, and a fourth bit line extending over the fifth isolation layer.

According to one embodiment, the first conductive path comprises: a via hole arranged on the first bitline line, passing through the first isolation layer; a portion of the conductive wire arranged on a first bitline line, disposed on the first isolation layer; and a via hole arranged on the first bitline line through the second isolation layer.

According to one embodiment, the second conductive path comprises: a via hole arranged on the first bitline line, passing through the first isolation layer; a portion of the conductive line extending from the first bitline axis all the way to the second bitline axis, disposed on the first isolation layer; a via hole arranged on the second bit line axis and passing through the second isolation layer; a portion of the conductive wire arranged on a second bit line axis disposed on the second isolation layer; a via hole arranged on the second bit line axis and passing through the third isolation layer; and a portion of the conductive line extending from the second bitline axis all the way to the first bitline axis disposed on the third isolation layer.

According to one embodiment, the third conductive path comprises: a via hole arranged on the second bit line axis and passing through the first isolation layer; a portion of the conductive wire arranged on a first bitline line, disposed on the first isolation layer; a via hole arranged on the first bitline line through the second isolation layer; a portion of the conductive wire arranged on a second bit line axis disposed on the second isolation layer; a via hole arranged on the second bit line axis and passing through the third isolation layer; a portion of the conductive wire arranged on the second bit line axis, disposed on the third isolation layer; a via hole arranged on the second bit line axis and passing through the fourth isolation layer; a portion of the conductive line extending from the second bitline axis all the way to the first bitline axis disposed on the fourth isolation layer; and a via hole arranged on the first bitline line through the fifth insulation layer.

According to one embodiment, the fourth conductive path comprises: a via hole arranged on the second bit line axis and passing through the first isolation layer; a portion of the conductive wire arranged on a first bitline line, disposed on the first isolation layer; a via hole arranged on the first bitline line through the second isolation layer; a portion of the conductive wire arranged on a second bit line axis disposed on the second isolation layer; a via hole arranged on the second bit line axis and passing through the third isolation layer; a portion of the conductive wire arranged on the second bit line axis, disposed on the third isolation layer; a via hole arranged on the second bit line axis and passing through the fourth isolation layer; a portion of the conductive line disposed on the fourth isolation layer; and a via hole arranged on the second bit line through the fifth insulating layer.

According to one embodiment, a memory includes a read circuit and a column decoder configured to read memory cells of a same column through one of two bit lines assigned to the column.

Embodiments of the present invention also relate to a method of manufacturing a non-volatile memory on a semiconductor substrate, the memory comprising a pair of twin memory cells, each twin memory cell comprising a floating gate transistor and a select transistor, the select transistor comprising a select gate in common with the select transistor of the twin memory cell, the method comprising the steps of: fabricating a first column of memory cells and a second column of memory cells, the memory cells including each twin memory cell of a pair of twin memory cells; fabricating a first bit line, the first bit line being arranged on a first bit line axis, extending over a first column of memory cells, and being connected to the floating gate transistors of the non-twin memory cells of the first column by a first conductive path, the first conductive path including a via through an isolation layer and a portion of a conductive line disposed on the isolation layer; fabricating a second bit line, the second bit line arranged on the first bit line axis and connected to the floating gate transistors of the other non-twin memory cells of the first column by a second conductive path, the second conductive path comprising: a via through the isolation layer and a portion of the conductive line disposed on the isolation layer; fabricating a third bit line, the third bit line being arranged on the first bit line axis and connected to the floating gate transistors of the non-twin memory cells of the second column by a third conductive path, the third conductive path including a via through the isolation layer and a portion of the conductive line disposed on the isolation layer; and fabricating a fourth bit line, the fourth bit line being arranged on the second bit line axis, extending over the second column of memory cells, and being connected to the floating gate transistors of other non-twin memory cells of the second column by a fourth conductive path, the fourth conductive path comprising a via through the isolation layer and a portion of the conductive line disposed on the isolation layer.

According to one embodiment, the method comprises the steps of: the method includes fabricating a first spacer, a second spacer, a third spacer, a fourth spacer, and a fifth spacer, fabricating a first bit line on the second spacer, fabricating a second bit line on the third spacer, fabricating a third bit line on the fifth spacer, and fabricating a fourth bit line on the fifth spacer.

According to one embodiment, the step of manufacturing the first conductive path comprises: fabricating vias, the vias being arranged on a first bitline axis, through the first isolation layer; fabricating portions of conductive wire, the portions of conductive wire arranged on a first bitline line, disposed on a first isolation layer; and fabricating vias arranged on the first bitline lines through the second isolation layer.

According to one embodiment, the step of manufacturing the second conductive path comprises: fabricating vias, the vias being arranged on a first bitline axis, through the first isolation layer; fabricating a portion of a conductive line, the portion of the conductive line extending from the first bitline axis all the way to the second bitline axis, disposed on the first isolation layer; manufacturing a via hole, wherein the via hole is arranged on the second position line and penetrates through the second isolation layer; fabricating portions of the conductive wire, the portions of the conductive wire arranged on a second bobbin line, disposed on a second spacer layer; manufacturing a via hole, wherein the via hole is arranged on the second position line and penetrates through the third isolation layer; and fabricating a portion of the conductive line, the portion of the conductive line extending from the second bitline axis all the way to the first bitline axis, disposed on the third isolation layer.

According to one embodiment, the step of manufacturing the third conductive path comprises: manufacturing a via hole, wherein the via hole is arranged on the second position line and penetrates through the first isolation layer; fabricating portions of conductive wire, the portions of conductive wire arranged on a first bitline line, disposed on a first isolation layer; manufacturing a via hole, wherein the via hole is arranged on the first bit line and penetrates through the second isolation layer; fabricating portions of the conductive wire, the portions of the conductive wire arranged on a second bobbin line, disposed on a second spacer layer; manufacturing a via hole, wherein the via hole is arranged on the second position line and penetrates through the third isolation layer; fabricating portions of the conductive wire, the portions of the conductive wire being arranged on a second bobbin line, disposed on a third isolation layer; manufacturing a via hole, wherein the via hole is arranged on the second position line and penetrates through the fourth isolation layer; fabricating a portion of the conductive line, the portion of the conductive line extending from the second bitline axis all the way to the first bitline axis, disposed on the fourth isolation layer; and fabricating a via, the via being aligned on the first bitline axis, through the fifth isolation layer.

According to one embodiment, the step of manufacturing the fourth conductive path comprises: manufacturing a via hole, wherein the via hole is arranged on the second position line and penetrates through the first isolation layer; fabricating portions of conductive wire, the portions of conductive wire arranged on a first bitline line, disposed on a first isolation layer; manufacturing a via hole, wherein the via hole is arranged on the first bit line and penetrates through the second isolation layer; fabricating portions of the conductive wire, the portions of the conductive wire arranged on a second bobbin line, disposed on a second spacer layer; manufacturing a via hole, wherein the via hole is arranged on the second position line and penetrates through the third isolation layer; fabricating portions of the conductive wire, the portions of the conductive wire arranged on the second bobbin line, disposed on the third isolation layer; manufacturing a via hole, wherein the via hole is arranged on the second position line and penetrates through the fourth isolation layer; fabricating a portion of the conductive line, the portion of the conductive line disposed on the fourth isolation layer; and fabricating vias, the vias aligned on the second bit line through the fifth isolation layer.

Drawings

Embodiments of a memory plane structure, a memory cell, and methods of fabricating such a memory plane structure and memory cell will be described subsequently by way of non-limiting reference to the accompanying drawings in which:

figure 1 described previously is a circuit diagram of a conventional memory plane structure and twin memory cells,

FIG. 2 is a circuit diagram of an embodiment of a memory plane comprising binoculars (bins) of twin memory cells according to the invention,

figures 3 to 7 are top views of a semiconductor substrate showing steps of a method of manufacturing a twin memory cell,

FIG. 8A, FIG. 9, FIG. 10A, FIG. 11, FIG. 12A, FIG. 13, FIG. 14A, FIG. 15, FIG. 16A, FIG. 17A are top views of a semiconductor substrate showing further steps of a method of fabricating a twin memory cell,

FIG. 8B, FIG. 10B, FIG. 12B, FIG. 14B, FIG. 16B, FIG. 17B are perspective views corresponding to the top views of FIG. 8A, FIG. 10A, FIG. 12A, FIG. 14A, FIG. 16A, FIG. 17A, and

fig. 18 is a circuit diagram of a memory comprising the memory plane in fig. 2.

Detailed Description

Fig. 2 is a circuit diagram of an embodiment of a memory plane MA1 embedded in a semiconductor substrate according to the present invention. The memory plane includes rows and columns of memory cells, here shown eight memory cells C1, j, C2, j, C3, j, C4, j, C1, j +1, C2, j +1, C3, j +1, C4, j + 1. Each memory cell includes: floating Gates (FG), T1, j, T2, j, T3, j, T4, j, T1, j +1, T2, j +1, T3, j +1, T4, j +1, respectively; and a selection transistor ST, a drain (D) terminal of which is connected to a source (S) terminal of the floating gate transistor.

Memory cells C1, j, C2, j, C3, j, C4, j belong to a column of row j, and memory cells C1, j +1, C2, j +1, C3, j +1, C4, j +1 belong to an adjacent column of row j + 1. Memory cells C1, j, C1, j +1 belong to the first row of memory cells, or physical page PG1, and their floating gate transistors T1, j, T1, j +1 have control gates CG1 connected to a common gate control line CGL 1. Memory cells C2, j, C2, j +1 belong to the second row of memory cells, or physical page PG2, and their floating gate transistors T2, j, T2, j +1 have control gates CG2 connected to a common gate control line CGL 2. Memory cells C3, j, C3, j +1 belong to the third row of memory cells, or physical page PG3, and their floating gate transistors T3, j, T3, j +1 have control gates CG3 connected to a common gate control line CGL 3. Memory cells C4, j, C4, j +1 belong to the fourth row of memory cells, or physical page PG4, and their floating gate transistors T4, j, T4, j +1 have control gates CG4 connected to a common gate control line CGL 4.

In row j, memory cells C1, j, C2, j are twin memory cells and their select transistors ST include a common select gate CSG1,2 connected to a common word line WL1, 2. Similarly, memory cells C3, j, C4, j are twin memory cells and their select transistors ST include a common select gate CSG3, 4 connected to a common word line WL3, 4. In row j +1, memory cells C1, j +1, C2, j +1 are twin memory cells and their select transistors ST include a common select gate CSG1,2 connected to a common word line WL1, 2. Similarly, memory cells C3, j +1, C4, j +1 are twin memory cells and their select transistors ST include a common select gate CSG3, 4 connected to a common word line WL3, 4. The common select gate CSG1,2 or CSG3, 4 of the twin memory cells of a pair is a buried vertical gate made in the form of a conductive trench made in the substrate, and the source (S) terminal of the select transistor ST is connected to a buried source plane SL extending below the region of the substrate in which the memory cells are embedded.

According to a first aspect of the present invention, memory plane MA1 includes two bit lines per column of memory cells. Thus, two bit lines B1, j, B2, j are assigned to the memory cells of the column of rank j, and two bit lines B1, j +1, B2, j +1 are assigned to the memory cells of the column of rank j + 1. Still further in accordance with this aspect of the invention, the two twin memory cells are connected to different ones of the two bit lines assigned to the column in which they are located, while the two adjacent but non-twin memory cells are connected to the same bit line.

Thus, in column row j:

the drain (D) terminal of the floating gate transistor T1, j is connected to the bit line B1, j via conductive path 1A,

the drain terminal of the floating gate transistor T2, j is connected to the bit line B2, j via a conductive path 23B,

the drain terminal of the floating gate transistor T3, j is connected to the bit line B2, j (memory cell C2, j is adjacent to but not doubled from memory cell C3, j) via a conductive path 23B, and

the drain terminal of the floating gate transistor T4, j is connected to the bit line B1, j via a conductive path 4A.

In column row j + 1:

the drain terminal of the floating gate transistor T1, j +1 is connected to the bit line B1, j +1 via a conductive path 1C,

the drain terminal of the floating gate transistor T2, j +1 is connected to the bit line B2, j +1 via a conductive path 23D,

the drain terminal of the floating gate transistor T3, j +1 is connected to the bit line B2, j +1 (memory cell C2, j +1 is adjacent to but not doubled from memory cell C3, j +1) via a conductive path 23D, and

the drain terminal of the floating gate transistor T4, j +1 is connected to the bit line B1, j +1 via a conductive path 4C.

Thus, each memory cell can be read independently of its twin memory cell by the bit line to which it is connected and to which its twin memory cell is not connected. For example, after selecting a twin memory cell C1, j, C2, j by a select voltage applied to the word line WL1, 2, and after applying a read voltage to the gate control line CGL1, the memory cell C1, j can be read via the bit line B1, j without applying a negative read inhibit voltage to the gate control line CGL2 of the twin memory cell C2, j because the memory cell is not connected to the bit line B1, j but is connected to the bit line B2, j.

Providing such twin memory cells with buried common select gates provides the advantage of greatly reducing the semiconductor surface occupied by the memory cells, so that the minimum distance between two columns of memory cells is no longer determined by the limitations of their manufacturing method, but rather by the limitations of the manufacturing method of the bit lines. Thus, tolerances of the bit lines and their manufacturing methods exert an influence on the minimum distance between two columns of memory cells and thus generally determine the space requirements of the memory plane.

More particularly, the bit lines are fabricated in the form of conductive traces arranged side-by-side on an electrically isolating layer deposited on the memory cells and connected to the memory cells by vertical electrical contacts, called "vias," through the isolating layer. The distance between two conductive traces and the minimum width of a conductive trace are parameters that are affected by the tolerance of the manufacturing method (for avoiding short circuits between adjacent bit lines), and determine the minimum width of a column of memory cells. By way of example, in the case of the '90 nm' (channel width of a transistor) microelectronics domain, a bit line fabricated in the form of an aluminum conductive trace may typically exhibit a width on the order of 120nm, with a minimum distance between two bit lines on the order of 120nm, such that the minimum width of a column of memory cells is typically on the order of 240 nm.

Providing two bit lines per column of memory cells thus involves doubling the width of each column of memory cells with conventional fabrication methods, which is also unacceptable although the advantages provided by the two bit lines simplify the process of reading the memory cells.

Thus, a second aspect of the present invention is directed to a method of manufacturing for memory plane MA1 to manufacture two bit lines per column without increasing the width of the columns of memory cells.

One embodiment of the method will be described below by taking as an example the fabrication of eight memory cells C1, j through C4, j +1 and four corresponding bit lines B1, j through B2, j +1 in fig. 2. More specifically, the steps of fabricating these memory cells will be described with respect to fig. 3-7, and the steps of fabricating the bit line B1, j-B2, j +1 will be described with respect to fig. 8A-17B.

Fig. 3 shows an initial step of forming three isolation trenches STI0, STI1, STI2 of the longitudinal STI (shallow trench isolation) type in a semiconductor substrate PW, wherein the isolation trenches STI0, STI1, STI2 define two substrate strips S1, S2 in which the memory cells are to be created. This step is performed by a step of embedding in the substrate a doped buried layer forming a source plane SL (not visible in the figure) or embedding a plurality of interconnected source lines SL. Where the memory cells are intended to be erased by hot electron injection, the source plane is typically preferably the source line.

During the step illustrated in fig. 4, two conductive trenches are formed transversely to the substrate strips S1, S2 by: the substrate is etched, a dielectric layer (not visible) is deposited, then a layer of polysilicon P0 (polycrystalline silicon) is deposited and the latter is etched until only the conductive trenches P0 remain. Each conductive trench is intended to form both a word line WL1, 2, WL2, 3 and a select gate CSG of the select transistor ST of the memory cell.

During the step illustrated in fig. 5, a tunnel dielectric layer D1 is deposited on the substrate PW, then two polysilicon P1 strips intended to form the floating gate FG are formed on the layer D1 above the substrate strips S1, S2 by etching the polysilicon layer.

During the step illustrated in fig. 6 for the result, a dielectric layer D2 is deposited on the substrate and on the polysilicon strip P1, and then a polysilicon layer is deposited on layer D2. The polysilicon layer is then etched, along with layer D2 and strip P1, to obtain lateral polysilicon strip P2 covering portions of residual strip P1. The strip P2 is intended to form the gate control lines CGL1, CGL2, CGL3, CGL4 of the floating gate transistor, and the portion of the strip P1 is intended to form the floating gate FG.

During the steps illustrated in fig. 7, the substrate strips S1, S2 are doped by self-aligned implantation of dopants on the gate control lines CGL1 to CGL 4. This step reveals the drain (D) region of the select transistor ST and the drain (D) and source (S) regions of the floating gate transistors T1, j to T4, j +1, and more specifically:

the drain region D (T1, j) of the transistor T1, j,

a common drain region D (T2, j, T3, j) of the transistors T2, j, T3, j,

a drain region D (T4, j) of the transistor T4, j,

the drain region D (T1, j +1) of the transistor T1, j +1,

a common drain region D (T2, j +1, T3, j +1) of the transistors T2, j +1, T3, j +1), and

the drain region D (T4, j +1) of the transistor T4, j.

The regions of the gate control lines CGL1 to CGL4 extending between these drain and source regions form the control gates CG1 to CG4 of the floating gate transistors, and the portions with P1 extending under the control gates CG1 to CG4 form the floating gates FG of the transistors. The conductive trench P0 forms the word lines WL1, 2, WL2, 3 and the select gate CSG of the select transistor ST of the memory cell.

It should be noted that the portion of the memory plane in production here forms the 'building block' of the memory plane, that is to say the smallest unit for implementing the method of manufacturing the bit line, which will be described below, as shown in fig. 7. In practice, the building block is manufactured together with other building blocks extending on the right and left side, above or below the building block (in the plane of fig. 7). Thus, the drain regions D (T2, j, T3, j) and D (T2, j +1, T3, j +1) are not the only drain regions common to both floating gate transistors. Each drain region D (T1, j), D (T1, j +1) is also a drain region common to another floating gate transistor belonging to an adjacent building block located above the shown building block, and each drain region D (T4, j), D (T4, j +1) is a drain region common to another floating gate transistor belonging to an adjacent building block located below the shown building block.

The steps for fabricating the bit lines B1, j, B1, j +1, B2, j, B2, j +1 over the building blocks will now be described with respect to table 1 in the appendix, which forms an integral part of the specification, and with reference to fig. 8A-17B. These steps include the steps of: depositing a dielectric layer, forming a via in the dielectric layer, then forming a portion of a conductive trace on the dielectric layer and over the via, and so on, until a bit line is obtained. The conductive traces may be formed by etching the metal layer or by Chemical Mechanical Polishing (CMP) the metal layer. CMP techniques require that trenches corresponding to conductive traces be previously created in a dielectric layer, and the conductive traces are then filled with a conductive material (e.g., aluminum) by depositing a conductive layer on the dielectric layer. The conductive layer is then polished until only the conductive traces in the trenches remain.

The following reference numerals will be used, chosen for those appearing in fig. 2:

a-bit line B1, j,

a bit line B2, j,

-C-bit line B1, j +1,

-D-bit line B2, j +1,

-1A-the conductive path linking the drain region of transistor T1, j to bit line A,

-23B being the conductive path between the drain region of the transistor T2, j, T3, j and the bit line B,

a conduction path linking the drain region of transistor T4, j to bit line a,

link the drain region of transistor T1, j +1 to the conductive path of bit line C,

-23D-the conductive path between the drain region of the transistor T2, j +1, T3, j +1 and the bit line D,

link the drain region of transistor T4, j +1 to the conductive path of bit line C,

v1Ax ═ level 'x' vias forming part of conductive path 1A,

v23Bx ═ level 'x' vias forming part of conductive path 23B,

v4Ax ═ level 'x' vias forming part of the conductive path 4A,

v1Cx ═ level 'x' vias forming part of the conductive path 1C,

v23Dx ═ level 'x' vias forming part of conductive path 23D,

v4Cx ═ level 'x' vias forming part of the conductive path 4C.

-T1Ax ═ a level 'x' trace portion 1A forming part of the conductive path 1A,

-T23Bx ═ a level 'x' trace portion 23B forming part of the conductive path 23B,

-T4Ax ═ a level 'x' trace portion 4A forming part of the conductive path 4A,

-T1Cx ═ a level 'x' trace portion 1C forming part of the conductive path 1C,

-T23Dx ═ a level 'x' trace portion 23D forming part of the conductive path 23D,

-T4Cx ═ a level 'x' trace portion 4C forming part of the conductive path 4C.

During step E1 shown in fig. 8A, a dielectric layer I0 was deposited on the substrate, and the level 0 vias mentioned in table 1 were fabricated in layer I0. The location of the via relative to the drain region of the floating gate transistor is described in table 1, with two elements appearing in the same column of table 1 and in two consecutive rows overlying (superexposure) and making electrical contact. Thus, via V1a0 is fabricated over drain region D (T1, j), via V23B0 is fabricated over drain region D (T2, j, T3, j), via V4a0 is fabricated over drain region D (T4, j), via V1C0 is fabricated over drain region D (T1, j +1), via V23D0 is fabricated over drain region D (T2, j +1, T3, j +1), and via V4C0 is fabricated over drain region D (T4, j + 1). It should be noted that the end VIAs VIA0, V1C0 and V4a0, VAC0 of the building blocks are also end VIAs of building blocks located above and below the illustrated building block and are thus shared with adjacent upper and lower building blocks.

As shown in fig. 8A, the vias are arranged along two bit lines Xj and Xj +1 that extend over the doped substrate strip S1 and over the doped substrate strip S2, respectively. Here, the vias V1a0, V23B0, V4a0 are aligned on the bit line axis Xj, and the vias V1C0, V23D0, V4C0 are aligned on the bit line axis Xj + 1. Table 1 includes columns 'Xj' and 'Xj + 1' showing the arrangement of each element with respect to these axes, with the elements mentioned in column 'Xj' being arranged on axis 'Xj' and the elements mentioned in column 'Xj + 1' being arranged on axis 'Xj + 1'.

Fig. 8B is a perspective and partial schematic view of a substrate showing the memory cell at this stage of its manufacture. Fig. 8B shows the substrate PW extending over the doped buried layer SL forming the source plane, the isolation trenches STI0, STI1, STI2 fabricated in the substrate PW, the longitudinal strips of doped substrate S1, S2 forming the drain and source regions of the floating gate transistors and the drain region of the select transistor, the lateral buried conductive trenches forming the word lines WL1, 2, WL2, 3 and the gates of the memory cell select transistors, the lateral polysilicon strips CGL1, CGL2, CGL3, CGL4 forming the gate control lines and the control gates of the floating gate transistors, and vias V1a0, V23B0, V4a0, V1C0, V23D0, V4C0 arranged on the axes Xj, Xj + 1. Dielectric layer I0 is not shown for visibility of the other elements shown.

During step E2 illustrated in fig. 9, a metal layer M1 ('metal 1') was deposited on dielectric layer I0, and then etched or chemically-mechanically polished to obtain the portions of the conductive traces of level M1 mentioned in table 1. Each portion of the conductive trace extends over a level 0 via mentioned in table 1. The portion T23B1 of the conductive trace has a longitudinal portion aligned on axis Xj and a transverse portion intersecting axis Xj +1, thus creating a 'wire jump' from axis Xj to axis Xj + 1. Thus, portion T23B1 appears in both column 'Xj' and column 'Xj + 1' of table 1.

During step E3 illustrated in fig. 10A, a dielectric layer I1 is deposited on the substrate and the level 1 vias mentioned in table 1 are fabricated in layer I1. Each via extends over a portion of the conductive trace of level M1 referenced in table 1. The positions of the vias with respect to the axes Xj, Xj +1, i.e. the positions aligned on the axes Xj or Xj +1, are given in table 1 as previously described by reference to the columns 'Xj' or 'Xj + 1' in which the vias are mentioned.

Fig. 10B is a perspective and partial schematic view of the substrate showing the via fabricated in step E3 and portions of the trace fabricated in step E2, and the via fabricated in step E1. The dielectric layers I0, I1 are not shown for visibility of the other elements shown.

During step E4 illustrated in fig. 11, a metal layer was deposited on dielectric layer I1, and then etched or chemically-mechanically polished to obtain the portion of the conductive trace of level M2 ('metal 2') mentioned in table 1. Each portion of the conductive trace extends over a level 1 via mentioned in table 1. The portion of the conductive trace fabricated over vias V1a1 and V4a1 forms bit line B1, j. Thus, the bit lines extend beyond the illustrated building blocks over the entire length of the columns of memory cells.

During step E5 illustrated in fig. 12A, a dielectric layer I2 is deposited on the substrate, and the level 2 vias mentioned in table 1 are fabricated in layer I2. Each via extends over a portion of the conductive trace of level M2 referenced in table 1. The positions of the vias relative to the axes Xj, Xj +1 are given in table 1 as previously described.

Fig. 12B is a perspective and partial schematic view of the substrate showing portions of traces and vias fabricated during and before steps E4, E5. The dielectric layers I0, I1, I2 are not shown for visibility of the other elements shown.

During step E6 illustrated in fig. 13, a metal layer was deposited on dielectric layer I2, and then etched or chemically-mechanically polished to obtain the portion of the conductive trace of level M3 ('metal 3') mentioned in table 1. Each portion of the conductive trace extends over a level 2 via mentioned in table 1. The portion of the conductive trace fabricated over via V23B2 includes a first lateral portion T23B3 that leads from axis Xj +1 to axis Xj, and a longitudinal segment that is aligned on axis Xj and forms bit line B2, j. Thus, the bit lines extend beyond the illustrated building blocks over the entire length of the columns of memory cells.

During step E7 illustrated in fig. 14A, a dielectric layer I3 is deposited on the substrate, and the level 3 vias mentioned in table 1 are fabricated in layer I3. Each via extends over a portion of the conductive trace of level M3 referenced in table 1. The positions of the vias relative to the axes Xj, Xj +1 are given in table 1 as previously described.

Fig. 14B is a perspective and partial schematic view of the substrate showing portions of traces and vias fabricated during steps E6, E7 and previously fabricated. The dielectric layers I0, I1, I2, I3 are not shown for visibility of the other elements shown.

During step E8 illustrated in fig. 15, a metal layer was deposited on dielectric layer I3, and then etched or chemically-mechanically polished to obtain the portion of the conductive trace of level M4 ('metal 4') mentioned in table 1. Each portion of the conductive trace extends over a level 3 via mentioned in table 1. The three portions of the conductive traces produced here are arranged transverse to the axes Xj, Xj +1 and thus appear in both columns 'Xj' and 'Xj + 1' of table 1.

Step E8 may optionally include creating conductive traces WLS1, 2, WLS3, 4 that cross the memory plane transverse to the axes Xj, Xj +1 and are connected from time to word lines WLS1, 2, WLS3, 4 to reduce their linear resistance, these connections being outside the range of fig. 15. Other functional conductive traces of this type (e.g., connected to gate control lines CGL 1-CGL 4) that are not involved in connecting memory cells to bit lines may be fabricated at the same time as part of the traces used to connect memory cells to bit lines.

During step E9 illustrated in fig. 16A, a dielectric layer I4 is deposited on the substrate, and the level 4 vias mentioned in table 1 are fabricated in layer I4. Each via extends over a portion of the conductive trace of level M4 referenced in table 1. The positions of the vias relative to the axes Xj, Xj +1 are given in table 1 as previously described.

Fig. 16B is a perspective and partial schematic view of the substrate showing trace portions and vias fabricated during steps E8, E9 and previously fabricated. The dielectric layers I0, I1, I2, I3, I4 are not shown for visibility of the other elements shown.

During step E10 illustrated in fig. 17A, a metal layer is deposited on the dielectric layer I4, and then etched or chemically mechanically polished to obtain the bit lines B1, j +1, B2, j +1 mentioned in table 1. The bit line B1, j +1 is in contact with vias V1C4 and V4C4, and the bit line B2, j +1 is in contact with via V23D 4.

Fig. 17B is a perspective and partial schematic view of the substrate showing portions of all traces and vias being fabricated. As previously described, the various dielectric layers are not shown for visibility of the other elements shown.

Table 1 shows how the drain region of the floating gate transistor is connected to the bit line via portions of all the vias and traces that are fabricated. Table 1 and the previously described figures also show that the bit lines B1, j, B2, j and B1, j +1 are superimposed, the bit lines B1, j, B2, j and B1, j +1 being created on levels M2, M3 and M5 respectively and being aligned on the axis Xj. Only the bit lines B2, j +1 fabricated on level M5 are aligned on axis Xj + 1.

Thus, the present fabrication method benefits from this advantage with respect to space requirements provided by twin memory cells with a common buried vertical select gate (the control gate of its select transistor), while at the same time making it possible to read the memory cells individually, since two bit lines per column are provided without destroying the space requirements of the memory plane. The present method enables a variety of variations with respect to the arrangement of the wires and vias of the bit line portions and the materials used to fabricate these elements.

Fig. 18 is a circuit diagram of an integrated circuit device DV including the memory plane MA1 of fig. 2. The device DV comprises a control circuit CCT1, a word line decoder RD1, a column decoder CD1, a read amplifier SA equal in number to the number of bits in a word to be read in the memory plane (e.g. a word of 8 bits B0-B7), and a program latch BLT1 for applying voltages to bit lines B1, j, B2, j, B1, j +1, B2, j +1 according to the word DTW to be written into the memory (e.g. a word of 8 bits B0-B7).

The word line decoder RD1 controls voltages applied to the gate control lines CGL1 to CGL4 and to the word lines WL1, 2, WL2, 3 according to the most significant address a (n-1) -a (x) or row address of a word. Decoder CD1 in combination with latch BLT1 controls the voltages applied to bit lines B1, j, B2, j, B1, j +1, B2, j +1, depending on the least significant address a (x-1) -a (0) or column address of the word, the row and column addresses together forming the address a (n-1) -a0 of the word to be read or written into the memory plane. In read mode, the decoder CD1 connects the sense amplifier SA to the bit line connected to the memory cell that needs to be read, and the sense amplifier provides the word DTR.

The circuit CCT1 includes, for example, a central processing unit CPU, a voltage generator VGEN, and address and data registers. The circuit CCT1 executes a read or write command, controls the decoder, supplies the voltages required for the read or write operation (erase programming), supplies the most and least significant addresses to the decoder, and executes a program to refresh the memory cells as needed.

Due to the presence of two bit lines per column, the word line decoder RD1 is configured to be able to separately control the voltage applied to the gate control lines (i.e., CGL1, CGL2 or CGL3, CGL4) of the twin memory cells, where the gate control lines have the same most significant address A (n-1) -A (x). This separate control of voltages may be reserved for erase operations for applying a positive voltage to those memory cells located on a page containing a twin page of erased cell or cells. In the read mode, the decoder on the other hand applies the same voltage to the twin gate control line or even to all the gate control lines of the memory plane to limit the switching of the logic gates and thus reduce the power consumption of the memory, since the selection of the memory cells is ensured by the word line WL in reading. In such an embodiment, decoder RD1 receives the least significant bits A (0) of the least significant addresses A (x-1) -A (0) of the words in addition to the most significant address A (n-1) A (x) of the words. Decoder RD2 also receives an information signal from circuit CCT1 telling the decoder whether address decoding to be performed is occurring as part of the reading, erasing or programming of the memory cells. Decoder RD1 distinguishes the two gate control lines according to bit a (0) if decoding is occurring as part of an erase. For example, the decoder RD1 selects the gate control line CGL1 if the bit line B1, j is specified by a full address received by the memory, or selects the gate control line CGL2 if the bit line B2, j is specified by a full address received by the memory. In an equivalent variation, the decoder may receive a signal from column decoder CD1 telling the decoder which of the two gate control lines must be selected. Other embodiments of decoders can naturally be provided by those skilled in the art, for example, to separately control the voltages applied to the gate control lines of a twin memory cell in reading, programming, and erasing.