阅读说明：本技术 一种发光二极管结构及其制备方法 (Light-emitting diode structure and preparation method thereof ) 是由 吴礼清 唐军 程斌 于 2019-09-11 设计创作，主要内容包括：本发明公开一种发光二极管结构及其制备方法,涉及半导体器件技术领域。本发明的一种发光二极管结构,包括：衬底；第一电极,其设置在衬底上；第一半导体层,其设置在第一电极上；应力消除层,其设置在第一半导体层上；发光层,其设置在应力消除层上；第二半导体层,其设置在发光层上；第二电极,其设置在第二半导体层上。本发明通过发光二极管结构及其制备方法改善发光量子阱的发光面和出光角度,解决了现有方法中发光二极管发光效率不高的问题。(The invention discloses a light-emitting diode structure and a preparation method thereof, and relates to the technical field of semiconductor devices. The invention relates to a light emitting diode structure, comprising: a substrate; a first electrode disposed on a substrate; a first semiconductor layer disposed on the first electrode; a stress relief layer disposed on the first semiconductor layer; a light emitting layer disposed on the stress relief layer; a second semiconductor layer provided on the light emitting layer; a second electrode disposed on the second semiconductor layer. The invention improves the light-emitting surface and the light-emitting angle of the light-emitting quantum well through the light-emitting diode structure and the preparation method thereof, and solves the problem of low light-emitting efficiency of the light-emitting diode in the prior method.)

1. A light emitting diode structure, comprising:

A substrate;

A first electrode disposed on the substrate;

A first semiconductor layer disposed on the first electrode;

A stress relief layer disposed on the first semiconductor layer;

A light emitting layer disposed on the stress relief layer;

A second semiconductor layer provided on the light emitting layer; and

a second electrode disposed on the second semiconductor layer.

2. the led structure of claim 1, wherein the first semiconductor layer comprises a buffer layer and an N-type gan layer stacked in sequence.

3. The led structure of claim 1, wherein said stress relief layer comprises a plurality of convex structures.

4. the led structure of claim 1, wherein said stress relief layer is comprised of a plurality of cycles of indium gallium nitride and N-type gallium nitride layers.

5. the led structure of claim 1, wherein said indium gallium nitride composition in said stress relief layer has an indium composition ratio of 0.01-0.1.

6. The led structure of claim 1, wherein said N-type gan composition in said stress relief layer is doped with silicon at a concentration of 1.0 x 10¹⁷cm^-3-1.0×10¹⁸cm^-3。

7. The led structure of claim 1, wherein the second semiconductor layer comprises a first P-type gan layer, an electron blocking layer and a second P-type gan layer stacked in sequence.

8. The led structure of claim 1, wherein said electron blocking layer comprises al and ga, and the doping concentration ratio of al to ga is 0.1-0.6.

9. a preparation method of a light-emitting diode structure is characterized by comprising the following steps:

Providing a substrate;

forming a first electrode on the substrate;

forming a first semiconductor layer on the first electrode;

Forming a stress relief layer on the first semiconductor layer;

Forming a light emitting layer on the stress relieving layer;

Forming a second semiconductor layer on the light emitting layer;

And forming a second electrode on the second semiconductor layer.

10. The method according to claim 9, wherein the growing further comprises annealing the light emitting diode structure after the light emitting diode structure is manufactured, the annealing temperature is 650 ℃ to 800 ℃, and the annealing atmosphere is pure nitrogen atmosphere.

Technical Field

The invention belongs to the technical field of semiconductor devices, particularly relates to the technical field of semiconductor epitaxy, and particularly relates to a light emitting diode structure and a preparation method thereof.

background

a light emitting diode is a semiconductor solid light emitting device that can directly convert electricity into light using a semiconductor PN junction as a light emitting material. The light emitting diode is used as a novel efficient, environment-friendly and green solid-state lighting source and has the advantages of low voltage, low power consumption, small size, light weight, long service life, high reliability, rich colors and the like. At present, the scale of the domestic production of the light-emitting diode is gradually enlarged, but the light-emitting diode still has the problem of low luminous efficiency. For the epitaxial growth of the purple light emitting diode, the promotion of the internal quantum efficiency usually relates to the carrier injection efficiency, in addition, because the light emitting wavelength of the purple light is shorter, the indium component of an indium nitride gallium layer in a quantum well is lower, and electrons generally overflow from a multi-quantum well structure to a P region to form non-radiative recombination type recombination. In the case that the carrier injection efficiency and the radiation recombination efficiency are constant, whether to find a light emitting diode structure and a preparation method thereof to improve the light emitting efficiency of the light emitting diode is a technical problem to be solved urgently in the technical field.

Disclosure of Invention

the invention aims to provide a light-emitting diode structure and a preparation method thereof, which improve the light-emitting surface and the light-emitting angle of a light-emitting quantum well by using the preparation method of a stress relief layer structure with a convex structure and solve the problem of low light-emitting efficiency of a light-emitting diode in the prior art.

In order to solve the technical problems, the invention is realized by the following technical scheme:

The invention provides a light emitting diode structure, which comprises:

a substrate;

a first electrode disposed on the substrate;

A first semiconductor layer disposed on the first electrode;

a stress relief layer disposed on the first semiconductor layer;

A light emitting layer disposed on the stress relief layer;

A second semiconductor layer provided on the light emitting layer;

A second electrode disposed on the second semiconductor layer.

in one embodiment of the present invention, the first semiconductor layer includes a buffer layer and an N-type gallium nitride layer stacked in this order.

in one embodiment of the present invention, the stress relief layer comprises a plurality of convex structures.

In one embodiment of the invention, the stress relief layer is comprised of a plurality of cycles of indium gallium nitride and N-type gallium nitride layers.

In one embodiment of the present invention, the indium component ratio of the indium gallium nitride component in the stress relief layer is 0.01 to 0.1.

in one embodiment of the present invention, the N-type gallium nitride component in the stress relief layer is doped with silicon with a doping concentration of 1.0 × 10¹⁷cm^-3-1.0×10¹⁸cm^-3。

In one embodiment of the present invention, the second semiconductor layer includes a first P-type gallium nitride layer, an electron blocking layer, and a second P-type gallium nitride layer, which are sequentially stacked.

In one embodiment of the present invention, the doping concentration ratio of aluminum to gallium in the electron blocking layer is 0.1 to 0.6.

the invention provides a preparation method of a light-emitting diode structure, which comprises the following steps:

Providing a substrate;

forming a first electrode on the substrate;

forming a first semiconductor layer on the first electrode;

forming a stress relief layer on the first semiconductor layer;

Forming a light emitting layer on the stress relieving layer;

forming a second semiconductor layer on the light emitting layer;

And forming a second electrode on the second semiconductor layer.

In an embodiment of the present invention, the growing method further includes annealing the light emitting diode structure after the light emitting diode structure is manufactured, where the annealing temperature is 650 ℃ to 800 ℃, and the annealing atmosphere is a pure nitrogen atmosphere.

the invention improves the light-emitting surface and the light-emitting angle of the light-emitting quantum well by the preparation method of the stress relief layer structure with the convex structure, and solves the problem of low light-emitting efficiency of the light-emitting diode in the prior art.

of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram of a light emitting diode structure according to an embodiment of the present invention;

FIG. 2 is a diagram of a light emitting diode structure according to an embodiment of the present invention;

FIG. 3 is a diagram of a light emitting diode structure according to an embodiment of the present invention;

FIG. 4 is a diagram of a light emitting diode structure according to an embodiment of the present invention;

Fig. 5 is a flowchart of a method for manufacturing a light emitting diode structure according to the present invention.

in the drawings, the components represented by the respective reference numerals are listed below:

the light-emitting diode comprises a substrate 1, a first electrode 2, a first semiconductor layer 3, a buffer layer 31, an N-type gallium nitride layer 32, a stress relieving layer 4, a light-emitting layer 5, a second semiconductor layer 6, a first P-type gallium nitride layer 61, an electron blocking layer 62, a second P-type gallium nitride layer 63 and a second electrode 7.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

the light emitting diode is called as a fourth generation illumination light source or a green light source, has the characteristics of energy conservation, environmental protection, long service life, small volume and the like, and is widely applied to the fields of various indications, display, decoration, backlight sources, common illumination, urban night scenes and the like. According to different use functions, the system can be divided into five categories of information display, signal lamps, vehicle lamps, liquid crystal display backlight sources and general illumination.

Because the light-emitting diode has the characteristics of shock resistance, impact resistance, high light response speed, power saving, long service life and the like, the light-emitting diode is widely applied to various indoor and outdoor display screens; because the light-emitting diode not only saves energy, but also has high reliability, the light-emitting diode is also widely applied to traffic signal lamps. Because of its high response speed, leds are used in the automotive industry as automotive lamps. The light-emitting diode has the characteristics of long service life, high luminous efficiency, no interference, high cost performance and the like, is widely applied to called subscriber receivers, electronic calculators and card readers in electronic watches, mobile phones and wireless paging systems, and has more advantages as portable electronic products become more miniaturized.

Referring to fig. 1 to 4, the present invention provides a light emitting diode structure, including: the light-emitting diode comprises a substrate 1, a first electrode 2, a first semiconductor layer 3, a stress relieving layer 4, a light-emitting layer 5, a second semiconductor layer 6 and a second electrode 7.

Referring to fig. 1 to 4, in the present embodiment, the substrate 1 may be an aluminum nitride substrate, and in other embodiments, a sapphire substrate, a silicon carbide substrate, or the like may be used. The first electrode 2 is disposed on the substrate 1, and the first electrode 2 may include a plurality of conductive layers.

Referring to fig. 1 to 4, the first semiconductor layer 3 is disposed on the first electrode 2. In the present embodiment, the first semiconductor layer 3 includes the buffer layer 31 and the N-type gallium nitride layer 32. In this embodiment, the buffer layer 31 may be a gallium nitride buffer layer, and in other embodiments, may also be a low-temperature N-type gallium nitride layer, an undoped gallium nitride layer, or the like. The buffer layer 31 may be grown to a thickness of 500nm to 2500nm, and include a group v element and a group iii element in a molar ratio of the group v element to the group iii element of 300 to 2500. The growth thickness of the N-type gallium nitride layer 32 can be 1000nm-4500Nthe m, N-type gallium nitride layer 32 contains impurities, and the doping concentration thereof may be 1.0 × 10¹⁸cm^-3-1.0×10¹⁹cm^-3the N-type gallium nitride layer 32 contains a group v element and a group iii element, and the molar ratio of the group v element to the group iii element may be 50to 2000. The range given by the parameters is optimized according to the appearance and performance of the device, and the structural characteristics of the first semiconductor layer provide a basis for the subsequent stress relief layer.

Referring to fig. 1 to 4, the stress relief layer 4 is disposed on the first semiconductor layer 3. The stress relief layer 4 includes a plurality of convex structures, and in this embodiment, the convex structures may be saw-toothed convex structures, for example, as shown in fig. 1. In other embodiments, the convex structure may be a hemispherical convex structure such as shown in fig. 2, a wavy convex structure such as shown in fig. 3, a square wave convex structure such as shown in fig. 4, and the like. The convex structure of the stress relief layer 4 is beneficial to relieving the tensile stress generated by the first semiconductor layer 3. The stress relief layer 4 is formed by cycling m periods of indium gallium nitride layers and N-type gallium nitride layers, and in this embodiment, m may be 1-20, for example. The indium gallium nitride layer comprises indium element, the composition ratio of the indium element can be 0.01-0.1, and the growth thickness of each indium gallium nitride layer can be 0.5-5 nm. The doping concentration of silicon in the N-type gallium nitride layer may be 1.0 × 10¹⁷cm^-3-1.0×10¹⁸cm^-3the growth thickness of each N-type gallium nitride layer can be 1nm-10 nm. The stress relief layer 4 further includes a group V element and a group III element, and the molar ratio of the group V element to the group III element may be 200to 5000. The ranges given for the above parameters seek optimal values, such as thickness, doping concentration, molar ratio, depending on the morphology and performance of the device.

referring to fig. 1 to 4, the light emitting layer 5 is disposed on the stress relief layer 4. The light emitting layer 5 includes a plurality of convex structures, and in this embodiment, the convex structures may be saw-tooth convex structures, for example, as shown in fig. 1. In other embodiments, the convex structure may be a hemispherical convex structure such as shown in fig. 2, a wavy convex structure such as shown in fig. 3, a square wave convex structure such as shown in fig. 4, and the like. On the premise of not changing the size of the whole structure, the convex structure of the luminous layer 5 increases the luminous area of the luminous layer 5 on one hand, and on the other hand, the light-emitting angle of the luminous layer 5 is changed, so that the reflection phenomenon that light reaches the surface interface is reduced, and the light-emitting efficiency is greatly improved. The light emitting layer 5 is formed by n cycles of indium gallium nitride layers and aluminum gallium nitride layers, and in this embodiment, n may be 5 to 10, for example. The growth thickness of each indium gallium nitride layer can be 1nm-20nm, the growth thickness of each aluminum gallium nitride layer can be 1nm-20nm, the light-emitting layer 5 further comprises a plurality of barriers, and the thickness of each barrier can be 1nm-10 nm. The stress relief layer 4 contains a group V element and a group III element, and the molar ratio of the group V element to the group III element may be 300 to 8000. The ranges given for the above parameters seek optimal values, such as thickness, doping concentration, molar ratio, depending on the morphology and performance of the device.

referring to fig. 1 to 4, the second semiconductor layer 6 is disposed on the light emitting layer 5. The second semiconductor layer 6 includes a plurality of convex structures, and in this embodiment, the convex structures may be saw-tooth convex structures, for example, as shown in fig. 1. In other embodiments, the convex structure may be a hemispherical convex structure such as shown in fig. 2, a wavy convex structure such as shown in fig. 3, a square wave convex structure such as shown in fig. 4, and the like. The second semiconductor layer 6 further includes a first P-type gallium nitride layer 61, an electron blocking layer 62, and a second P-type gallium nitride layer 63, which are sequentially stacked. The first P-type gallium nitride layer 61 contains a group v element and a group iii element, and the molar ratio of the group v element to the group iii element may be 300 to 5000. The growth thickness of the electron blocking layer 62 can be 10nm to 120nm, the doping concentration ratio of aluminum to gallium in the electron blocking layer 62 can be 0.1 to 0.6, the electron blocking layer 62 layer further comprises a group V element and a group III element, and the molar ratio of the group V element to the group III element can be 200to 6000. The growth thickness of the second P-type gallium nitride layer 63 can be 30nm-100nm, the second P-type gallium nitride layer 63 contains a group V element and a group III element, and the molar ratio of the group V element to the group III element can be 200-6000. The second electrode 7 is disposed on the second semiconductor layer 6, and the second electrode 7 may include a plurality of conductive layers. The range given by the parameters enables the convex structure to be filled, and a tamped epitaxial layer is provided for subsequent surface evaporation.

Referring to fig. 1 to 4, the present invention further provides a method for manufacturing a light emitting diode structure, including the following steps:

Referring to fig. 5, in step S1, a substrate 1 is provided. In step S2, on the substrate 1, the first electrode 2 is formed. In this embodiment, the temperature in the chamber may be adjusted to 1000 ℃ to 1200 ℃, the growth pressure in the chamber may be adjusted to 100Torr to 500Torr, and triethylgallium is introduced into the chamber, and in step S3, the buffer layer in the first semiconductor layer 3 is formed on the first electrode 2. After the buffer layer in the first semiconductor layer 3 is formed, the growth pressure in the chamber may be adjusted to 100Torr to 600Torr, and a gallium nitride layer, for example, may be formed on the buffer layer. The range given by the parameters is optimized according to the appearance and performance of the device, and the structural characteristics of the first semiconductor layer provide a basis for the subsequent stress relief layer.

Referring to fig. 5, in step S4, in this embodiment, the temperature in the chamber may be adjusted to 600 ℃ to 1000 ℃, the growth pressure in the chamber may be adjusted to 100Torr to 400Torr, and triethylgallium is introduced into the chamber to form the stress relief layer 4 on the first semiconductor layer 3. The ranges given for the above parameters seek optimal values, such as thickness, doping concentration, molar ratio, depending on the topography of the device.

Referring to fig. 5, in step S5, in this embodiment, the temperature in the chamber may be adjusted to 750 ℃ to 920 ℃, the growth pressure in the chamber may be adjusted to 400Torr to 600Torr, and the light-emitting layer 5 is formed on the stress relieving layer 4. The ranges given for the above parameters seek optimal values, such as thickness, doping concentration, molar ratio, depending on the topography of the device.

Referring to fig. 5, in step S6, in this embodiment, the temperature in the chamber may be adjusted to 620 ℃ to 820 ℃, the growth pressure in the chamber may be adjusted to 50Torr to 500Torr, and the first P-type gallium nitride layer in the second semiconductor layer 6 is formed on the light-emitting layer 5 for 5min to 35 min. After the first P-type gallium nitride layer in the second semiconductor layer 6 is formed, the temperature in the chamber can be adjusted to 700-1100 ℃, the growth pressure in the chamber can be adjusted to 200-600 Torr, and an electron blocking layer is formed on the first P-type gallium nitride layer, wherein the growth time can be 5-30 min. After the electron blocking layer in the second semiconductor layer 6 is formed, the growth environment in the whole chamber is maintained, and a second P-type gallium nitride layer is grown on the electron blocking layer, wherein the growth time can be 5min to 30 min. The range given by the parameters enables the convex structure to be filled, and a tamped epitaxial layer is provided for subsequent surface evaporation.

referring to fig. 5, in step S7, a second electrode 7 is formed on the second semiconductor layer 6. After the second electrode 7 is prepared, annealing the light emitting diode structure, wherein the annealing temperature can be 650-800 ℃, and the annealing atmosphere is pure nitrogen atmosphere. And (3) carrying out subsequent processing technologies such as cleaning, deposition, photoetching and etching on the annealed light-emitting diode structure to prepare a single small-size chip. In this example, high-purity hydrogen or nitrogen gas may be used as a carrier gas, trimethyl gallium or triethyl gallium may be used as a gallium source, trimethyl aluminum may be used as an aluminum source, trimethyl indium may be used as an indium source, ammonia (NH3) may be used as a nitrogen source, silane may be used as an N-type dopant, and magnesium dicylocene may be used as a P-type dopant. The proper annealing temperature can ensure that the dopant magnesium is fully activated, and the P-type doping efficiency is highest.

The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.