阅读说明：本技术 陶瓷电子部件及其制造方法、以及电路基板 (Ceramic electronic component, method for manufacturing same, and circuit board ) 是由 星野良介 小林智司 内田康明 藤井皐 于 2021-03-24 设计创作，主要内容包括：本发明提供能够在陶瓷主体上良好地形成包括烧结基底层和镀层的外部电极的陶瓷电子部件及其制造方法、以及电路基板。本发明的陶瓷电子部件包括陶瓷主体和一对外部电极。陶瓷主体包括一对端面和连接一对端面的侧面,侧面由与一对端面相邻的一对端部区域和位于该一对端部区域之间的中间区域构成。一对外部电极覆盖一对端面和侧面的一对端部区域,包括一对基底层和一对镀层,一对基底层具有与侧面的中间区域的表面粗糙度Ra的差为40nm以下的外表面,一对镀层覆盖一对基底层的外表面、并具有从一对基底层的外表面延伸至侧面的中间区域的一对延伸区域。优选一对延伸部与侧面的中间区域的接触角为锐角。(The invention provides a ceramic electronic component capable of forming external electrodes including a sintered base layer and a plating layer on a ceramic body, a method for manufacturing the same, and a circuit board. A ceramic electronic component of the present invention includes a ceramic main body and a pair of external electrodes. The ceramic body includes a pair of end faces and a side face connecting the pair of end faces, and the side face is composed of a pair of end regions adjacent to the pair of end faces and an intermediate region between the pair of end regions. The pair of external electrodes cover a pair of end regions of the pair of end faces and the side faces, and include a pair of base layers having outer surfaces whose difference from a surface roughness Ra of a middle region of the side faces is 40nm or less, and a pair of plating layers covering the outer surfaces of the pair of base layers and having a pair of extension regions extending from the outer surfaces of the pair of base layers to the middle region of the side faces. Preferably, the contact angle of the pair of extensions with the middle region of the side face is acute.)

1. A ceramic electronic component, comprising:

a ceramic body including a pair of end faces and a side face connecting the pair of end faces, the side face being configured by a pair of end regions adjacent to the pair of end faces and an intermediate region located between the pair of end regions; and

and a pair of external electrodes covering the pair of end surfaces and the pair of end regions of the side surface, the pair of external electrodes including a pair of base layers having outer surfaces with a difference of surface roughness Ra of 40nm or less from the middle region of the side surface, and a pair of plating layers covering the outer surfaces of the pair of base layers and having a pair of extension portions extending from the outer surfaces of the pair of base layers to the middle region of the side surface.

2. The ceramic electronic component according to claim 1, wherein:

the contact angle of the pair of extensions with the middle region of the side face is acute.

3. The ceramic electronic component according to claim 1 or 2, wherein:

the base layer comprises nickel as a main component.

4. A ceramic electronic component according to any one of claims 1 to 3, wherein:

the base layer contains a ceramic component.

5. The ceramic electronic component according to any one of claims 1 to 4, wherein:

the difference in surface roughness Ra between the outer surfaces of the pair of base layers and the intermediate regions of the side surfaces is 30nm or less.

6. A ceramic electronic component according to any one of claims 1 to 5, wherein:

the surface roughness Ra of the outer surface of the base layer is 10nm or more and less than 200 nm.

7. The ceramic electronic component according to any one of claims 1 to 6, wherein:

the surface roughness Ra of the intermediate region is 10nm or more and less than 150 nm.

8. A method for manufacturing a ceramic electronic component, comprising:

a step of producing a composite sintered body including a ceramic main body including a pair of end faces and a side face connecting the pair of end faces, and a pair of base layers extending from the pair of end faces to the side face and spaced apart from each other on the side face;

performing jet polishing on the composite sintered body; and

and forming a pair of plating layers covering outer surfaces of the pair of base layers on the composite sintered body subjected to the jet polishing by a wet plating method.

9. The method for manufacturing a ceramic electronic component according to claim 8, wherein:

the step of performing jet milling comprises: and a step of setting a difference in surface roughness Ra between the outer surfaces of the pair of base layers and a region between the pair of base layers in the side surface to 40nm or less.

10. The method for manufacturing a ceramic electronic component according to claim 8 or 9, wherein:

the pair of plating layers has a pair of extensions extending from outer surfaces of the pair of base layers to the side surfaces.

11. The method for manufacturing a ceramic electronic component according to claim 10, wherein:

the contact angle between the pair of extending parts and the side surface is acute.

12. The method for manufacturing a ceramic electronic component according to any one of claims 8 to 11, wherein:

the step of producing a composite sintered body includes the step of simultaneously firing the ceramic main body and the pair of base layers.

13. A circuit substrate, comprising:

a ceramic body including a pair of end faces and a side face connecting the pair of end faces, the side face being configured by a pair of end regions adjacent to the pair of end faces and an intermediate region located between the pair of end regions;

a pair of external electrodes covering the pair of end surfaces and the pair of end regions of the side surface, the pair of external electrodes including a pair of base layers having outer surfaces with a difference of 40nm or less from a surface roughness Ra of the middle region of the side surface, and a pair of plating layers covering the outer surfaces of the pair of base layers and having a pair of extension portions extending from the outer surfaces of the pair of base layers to the middle region of the side surface;

a substrate main body;

a pair of terminals provided on the substrate main body; and

a solder joining the pair of external electrodes and the pair of terminals.

Technical Field

The present invention relates to a ceramic electronic component having a pair of external electrodes, a method for manufacturing the same, and a circuit board.

Background

Patent document 1 discloses a laminated ceramic capacitor having external electrodes including a base layer and a plating layer. In the method for manufacturing a laminated ceramic capacitor disclosed in patent document 1, a conductive paste is sintered on a ceramic body to form an underlying layer, and a plating layer is formed on the underlying layer by a wet plating method.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2019-201106

Disclosure of Invention

Technical problem to be solved by the invention

However, in the multilayer ceramic capacitor having the structure in which the plating layer is provided on the ceramic body with the underlying layer interposed therebetween as described above, defects are likely to occur in the plating layer. In contrast, the inventors of the present application have found that by subjecting the ceramic body having the underlayer formed thereon to a specific pretreatment, the occurrence of defects in the plating layer can be reduced.

In view of the above circumstances, an object of the present invention is to provide a ceramic electronic component, a method for manufacturing the same, and a circuit board, in which an external electrode including a base layer and a plating layer can be formed well on a ceramic body.

Means for solving the problems

In order to achieve the above object, a ceramic electronic component according to one embodiment of the present invention includes a ceramic main body and a pair of external electrodes.

The ceramic body includes a pair of end faces and a side face connecting the pair of end faces, and the side face is constituted by a pair of end regions adjacent to the pair of end faces and an intermediate region between the pair of end regions.

The pair of external electrodes covers the pair of end surfaces and the pair of end regions of the side surface, and includes a pair of base layers having outer surfaces whose difference from a surface roughness Ra of the middle region of the side surface is 40nm or less, and a pair of plating layers covering the outer surfaces of the pair of base layers and having a pair of extension portions extending from the outer surfaces of the pair of base layers to the middle region of the side surface.

Preferably, a contact angle of the pair of extensions with the middle region of the side face is acute.

In the ceramic electronic component, the extension portion of the plating layer extends from the outer surface of the base layer to the middle region of the side surface of the ceramic main body. In such a configuration, by keeping the difference in surface roughness Ra between the outer surface of the foundation layer and the intermediate region of the side surface of the ceramic body small, the contact angle between the extension of the plating layer and the intermediate region of the side surface of the ceramic body can be reduced. This can suppress the peeling of the external electrode from the extended portion of the plating layer.

The base layer may contain nickel as a main component.

The base layer may contain a ceramic component.

The difference in surface roughness Ra between the outer surfaces of the pair of base layers and the intermediate region of the side surface may be 30nm or less.

The outer surface of the base layer may have a surface roughness Ra of 10nm or more and less than 200 nm.

The surface roughness Ra of the intermediate region may be 10nm or more and less than 150 nm.

In a method of manufacturing a ceramic electronic component according to an aspect of the present invention, a composite sintered body is manufactured, the composite sintered body including a ceramic main body including a pair of end faces and a side face connecting the pair of end faces, and a pair of base layers extending from the pair of end faces to the side face and spaced apart from each other on the side face.

The composite sintered body was subjected to blast polishing (blast polishing).

A pair of plating layers covering the outer surfaces of the pair of base layers are formed on the composite sintered body subjected to the jet polishing by a wet plating method.

In this embodiment, the outer surface of the base layer can be uniformly ground by performing jet polishing on the composite sintered body composed of the ceramic body and the base layer. This makes it possible to remove the metal oxide formed on the outer surface of the underlayer during firing or the like, and thus to form a plated layer on the outer surface of the underlayer without unevenness. Further, since the difference in surface roughness Ra between the outer surface of the foundation layer and the side surface of the ceramic body can be kept small by the jet polishing, a structure in which the peeling of the external electrode can be suppressed can be obtained.

The step of performing jet milling may include: the difference in surface roughness Ra between the outer surfaces of the pair of base layers and the region between the pair of base layers on the side surface is 40nm or less.

The pair of plating layers may have a pair of extensions extending from outer surfaces of the pair of base layers to the side surfaces. In this case, a contact angle between the pair of extensions and the side surface may be acute.

The step of producing a composite sintered body may include the step of simultaneously firing the ceramic main body and the pair of base layers.

A circuit board according to an embodiment of the present invention includes the ceramic electronic component, a board main body, a pair of terminals, and solder.

The pair of terminals is provided on the substrate main body.

The solder bonds the pair of external electrodes and the pair of terminals.

Effects of the invention

The present invention can provide a ceramic electronic component in which an external electrode including a base layer and a plating layer can be formed well on a ceramic body, a method for manufacturing the same, and a circuit board.

Drawings

Fig. 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention.

Fig. 2 is a sectional view of the laminated ceramic capacitor taken along line a-a' of fig. 1.

Fig. 3 is a sectional view of the laminated ceramic capacitor taken along line B-B' of fig. 1.

Fig. 4 is a sectional view of the laminated ceramic capacitor taken along line C-C' of fig. 1.

Fig. 5 is a partial cross-sectional view showing a part of the multilayer ceramic capacitor in an enlarged manner.

Fig. 6 is a flowchart showing the method for manufacturing the multilayer ceramic capacitor.

Fig. 7 is a perspective view of the ceramic main body produced in step S01.

Fig. 8 is a sectional view of the composite green body obtained in step S02.

Fig. 9 is a sectional view of the composite sintered body obtained in step S03.

Fig. 10 is a partial sectional view showing the formation process of the plating layer in step S05.

Fig. 11 is a graph showing a relationship between Δ Ra and a defective rate of plating.

Fig. 12 is a side view of a circuit board using the multilayer ceramic capacitor.

Description of the reference numerals

10 … laminated ceramic capacitor, 11 … ceramic body, 12, 13 … internal electrode, 14, 15 … external electrode, 14a, 15a … base layer, 14b, 15b … plating layer, 14b1, 15b1 … extending part, E … end face, S1, S2 … side face, end region of P1 … side face, middle region of P2 … side face, outer surface of Q … base layer.

Detailed Description

Embodiments of the present invention will be described below with reference to the drawings.

In the drawings, an X-axis, a Y-axis, and a Z-axis orthogonal to each other are properly shown. The X, Y and Z axes are the same throughout the figures.

1. Basic structure of multilayer ceramic capacitor 10

Fig. 1 to 4 show a multilayer ceramic capacitor 10 according to an embodiment of the present invention. Fig. 1 is a perspective view of a multilayer ceramic capacitor 10. Fig. 2 is a sectional view taken along line a-a' of fig. 1. Fig. 3 is a sectional view taken along line B-B' of fig. 1. Fig. 4 is a sectional view taken along line C-C' of fig. 1.

The laminated ceramic capacitor 10 includes a ceramic main body 11, a first external electrode 14, and a second external electrode 15. The multilayer ceramic capacitor 10 may be formed in various sizes according to the application and the like, and as an example, the sizes along the X axis, the Y axis, and the Z axis may be 1.0mm, 0.5mm, and 0.5mm, respectively.

The ceramic main body 11 is formed as a hexahedron having an outer surface including a pair of end surfaces E, a pair of first side surfaces S1, and a pair of second side surfaces S2. In the ceramic body 11, a pair of end faces E extending parallel to the Y-Z plane are connected in the X-axis direction by a first side face S1 extending parallel to the X-Y plane and a second side face S2 extending parallel to the X-Z plane.

The end face E and the side faces S1, S2 of the ceramic main body 11 are each formed as a flat face. The flat surface in the present embodiment is not necessarily a strictly-defined flat surface as long as it is considered to be flat when viewed as a whole, and includes, for example, a surface having a minute uneven shape on the surface, a gently curved shape existing in a predetermined range, and the like.

The external electrodes 14 and 15 cover both end surfaces E of the ceramic body 11 and face each other in the X-axis direction with the ceramic body 11 interposed therebetween. The external electrodes 14, 15 extend from the respective end faces E of the ceramic main body 11 to the first side face S1 and the second side face S2, and are spaced apart from each other in the X-axis direction on the first side face S1 and the second side face S2.

The ceramic main body 11 is formed of a dielectric ceramic. The ceramic main body 11 has a plurality of first internal electrodes 12 and second internal electrodes 13 covered with a dielectric ceramic. The plurality of internal electrodes 12, 13 are each in the shape of a sheet extending along the X-Y plane and are alternately arranged along the Z-axis direction (in the Z-axis direction).

That is, in the ceramic body 11, opposing regions are formed in which the internal electrodes 12 and 13 oppose each other in the Z-axis direction with the ceramic layers interposed therebetween. The first inner electrode 12 is drawn out from the opposing region to one end face E, and is connected to the first outer electrode 14. The second internal electrode 13 is drawn out from the facing region to the other end face E, and is connected to the second external electrode 15.

With such a configuration, in the laminated ceramic capacitor 10, when a voltage is applied between the first external electrode 14 and the second external electrode 15, the voltage is applied to the plurality of ceramic layers in the opposing region where the internal electrodes 12, 13 oppose each other. Accordingly, in the multilayer ceramic capacitor 10, electric charges corresponding to the voltage between the first external electrode 14 and the second external electrode 15 can be accumulated.

In the ceramic body 11, a dielectric ceramic having a high dielectric constant can be used in order to increase the capacitance of each ceramic layer between the internal electrodes 12 and 13. The dielectric ceramic having a high dielectric constant includes, for example, barium titanate (BaTiO)₃) A typical perovskite-structured material containing barium (Ba) and titanium (Ti).

The dielectric ceramic may be strontium titanate (SrTiO)₃) Calcium titanate (CaTiO)₃) Magnesium titanate (MgTiO)₃) Calcium zirconate (CaZrO)₃) Titanium calcium zirconate (Ca (Zr, Ti) O)₃) Barium zirconate (BaZrO)₃) Titanium oxide (TiO)₂) And the like.

2. Detailed structure of multilayer ceramic capacitor 10

The multilayer ceramic capacitor 10 of the present embodiment has a structure in which the external electrodes 14 and 15 can be stably formed on the ceramic body 11. Therefore, the external electrodes 14 and 15 of the present embodiment can easily obtain good connectivity with the internal electrodes 12 and 13, and can easily ensure good solder wettability at the time of mounting.

Specifically, in the multilayer ceramic capacitor 10, the first external electrode 14 has a first base layer 14a and a first plating layer 14b, and the second external electrode 15 has a second base layer 15a and a second plating layer 15 b. The base layers 14a and 15a are sintered films of a conductor, and the plating layers 14b and 15b are wet-plated films of a metal.

The base layers 14a and 15a are adjacent to the end face E and the side faces S1 and S2 of the ceramic body 11, and constitute the innermost layers of the external electrodes 14 and 15. By providing the base layers 14a and 15a in the external electrodes 14 and 15, the connection with the internal electrodes 12 and 13 at the end face E of the ceramic body 11 can be more reliably obtained.

As shown in fig. 2 and 3, the side surfaces S1 and S2 of the ceramic main body 11 are formed of a pair of end regions P1 located at both ends in the X-axis direction and an intermediate region P2 located between the pair of end regions P1. The pair of end regions P1 are covered with the base layers 14a, 15a, and the intermediate region P2 is not covered with the base layers 14a, 15 a.

The plating layers 14b and 15b cover the ceramic body 11 from the underlying layers 14a and 15a, and constitute the outermost layers of the external electrodes 14 and 15. In the multilayer ceramic capacitor 10, the plating layers 14b and 15b having higher solder wettability than the base layers 14a and 15a are provided as the outermost layers of the external electrodes 14 and 15, and thus the multilayer ceramic capacitor can be easily mounted.

The plating layers 14b, 15b cover the entire outer surfaces Q of the base layers 14a, 15a, and have extension portions 14b1, 15b1 extending inward in the X-axis direction beyond the base layers 14a, 15 a. The extended portions 14b1, 15b1 of the plated layers 14b, 15b are in direct contact with the middle region P2 of the side surfaces S1, S2 of the ceramic main body 11.

Fig. 5 is a partial cross-sectional view showing the extension portions 14b1, 15b1 of the plating layers 14b, 15b and the vicinity thereof in the multilayer ceramic capacitor 10 in an enlarged manner. In the laminated ceramic capacitor 10, the external electrodes 14 and 15 have the same structure, and therefore, for the sake of convenience of explanation, reference numerals of the external electrodes 14 and 15 are shown in fig. 5 at the same time.

In the multilayer ceramic capacitor 10, the difference Δ Ra between the surface roughness Ra of the outer surfaces Q of the base layers 14a and 15a and the middle region P2 of the side surfaces S1 and S2 of the ceramic body 11 is small. Specifically, Δ Ra is preferably 40nm or less, more preferably 30nm or less. If Δ Ra is small, the magnitude relationship of the surface roughness Ra of each surface may be arbitrary.

With this structure, in the multilayer ceramic capacitor 10, the contact angle θ shown in fig. 5, which is defined as the angle formed by the surfaces of the extending portions 14b1, 15b1 with respect to the intermediate region P2 of the side surfaces S1, S2 of the ceramic main body 11, is small. Specifically, the contact angle θ of the extending portions 14b1 and 15b1 is preferably acute.

In the external electrodes 14 and 15, by making the contact angle θ of the extending portions 14b1 and 15b1 acute, an external force in a direction of separating from the intermediate region P2 of the side surfaces S1 and S2 of the ceramic body 11 is less likely to be applied to the extending portions 14b1 and 15b 1. Therefore, the joining of the extending portions 14b1, 15b1 to the intermediate region P2 of the side surfaces S1, S2 of the ceramic main body 11 is not easily hindered.

Therefore, in the multilayer ceramic capacitor 10, separation of the external electrodes 14 and 15 from the extending portions 14b1 and 15b1 can be prevented. Therefore, in the multilayer ceramic capacitor 10, the occurrence of a trouble such as a decrease in moisture resistance due to peeling of the external electrodes 14 and 15 can be prevented, and therefore, high reliability can be obtained.

The surface roughness Ra of the middle region P2 of the side surfaces S1, S2 of the ceramic body 11 can be measured, for example, in the region of the ceramic body 11 exposed without being covered with the plating layers 14b, 15 b.

The surface roughness Ra of the outer surface Q of the underlying layers 14a and 15a can be measured by, for example, peeling off the plating layers 14b and 15 b. For example, a plating stripping solution can be used for stripping the plating layers 14b and 15 b. More specifically, the plating layers 14b and 15b can be peeled off and the underlying layers 14a and 15a can be exposed by stirring the plating peeling liquid in which the multilayer ceramic capacitor 10 is immersed.

The surface roughness Ra of the intermediate region P2 of the side surfaces S1 and S2 of the ceramic body 11 and the outer surface Q of the base layers 14a and 15a may be measured using a laser microscope (e.g., model number: OLS4100, manufactured by OLYMPUS corporation). The surface roughness Ra can be measured, for example, in a predetermined rectangular region (250 μm × 250 μm) in each surface. In order to exclude the abnormal value, for example, the measurement length may be set to 250 μm every 1, the surface roughness Ra at 5 may be measured, and the average value of the central 3 values obtained by removing the maximum value and the minimum value from the obtained 5 values may be used. The surface roughness Ra is an arithmetic average roughness.

The outer surface Q of the underlayer 14a, 15a preferably has a surface roughness Ra of 10nm or more and less than 200nm, more preferably 30nm or more and less than 150nm, over the entire area thereof. Thus, in the multilayer ceramic capacitor 10, the plating layers 14b and 15b can be easily formed to have a uniform thickness over the entire outer surfaces Q of the base layers 14a and 15 a.

In the intermediate region P2 between the side surfaces S1 and S2 of the ceramic body 11, the surface roughness Ra is preferably 10nm or more and less than 150nm, and more preferably 20nm or more and less than 120 nm. This makes it easy to keep the contact angle θ between the extending portions 14b1 and 15b1 and the middle region P2 of the side surfaces S1 and S2 of the ceramic main body 11 smaller.

The underlayer 14a, 15a is typically formed mainly of Ni (nickel). However, the base layers 14a and 15a may be made of, for example, Cu (copper), Pd (palladium), Ag (silver), or the like, in addition to the main component. In the present embodiment, the main component refers to a component having the highest content ratio.

In order to improve the adhesion between the base layers 14a and 15a and the ceramic body 11, the base layers 14a and 15a preferably contain a ceramic component. The ceramic component contained in the base layers 14a and 15a is typically a dielectric ceramic of the same composition as the ceramic body 11, but may be another ceramic if necessary.

In the multilayer ceramic capacitor 10, the plating layers 14b and 15b are likely to be uneven due to the presence of the metal oxide having low conductivity on the outer surfaces Q of the underlying layers 14a and 15 a. Therefore, the metal oxide is preferably small on the outer surface Q of the underlayer 14a, 15 a.

The plating layers 14b and 15b may have a single-layer structure composed of one plating film or a laminated structure composed of a plurality of plating films. As an example, the plating layers 14b and 15b may have a laminated structure in which a Cu (copper) film, a Ni (nickel) film, and an Sn () film are laminated in this order from the outer surface Q side of the foundation layers 14a and 15 a.

3. Method for manufacturing multilayer ceramic capacitor 10

Fig. 6 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10 according to the present embodiment. FIGS. 7 to 11 show a process for manufacturing the multilayer ceramic capacitor 10. Next, a method for manufacturing the multilayer ceramic capacitor 10 will be described with reference to fig. 6 and fig. 7 to 11 as appropriate.

3.1 step S01: ceramic body fabrication

In step S01, an unfired ceramic body 111 shown in fig. 7 is produced. The unfired ceramic body 111 can be obtained, for example, by laminating a plurality of ceramic sheets in the Z-axis direction and thermocompression bonding the laminated ceramic sheets. The unfired internal electrodes 112 and 113 can be arranged by printing a predetermined pattern of conductive paste on the ceramic sheet in advance.

The ceramic sheet is an unfired dielectric green sheet obtained by forming a ceramic slurry into a sheet shape. The ceramic sheet can be formed into a sheet shape using, for example, a roll coater or a doctor blade. The components of the ceramic slurry are adjusted so that a ceramic body 11 having a predetermined composition can be obtained.

3.2 step S02: formation of base layer

In step S02, unfired underlying layers 114a and 115a are formed on the unfired ceramic body 111 produced in step S01. Thereby, a composite green body 111a shown in fig. 8 was obtained. The base layers 114a and 115a can be formed by applying a conductive paste on the ceramic body 111, for example.

In the composite green body 111a, for example, ceramic powder is mixed with conductive paste to contain a ceramic component in the underlying layers 114a and 115 a. This makes it possible to obtain high bondability between the base layers 14a and 15a and the ceramic body 11 in the composite sintered body 11a after firing.

3.3 step S03: firing

In step S03, the composite green body 111a obtained in step S02 is fired. Thereby, the composite green body 111a is sintered to obtain a composite sintered body 11a shown in fig. 9. The composite green body 111a may be fired in a reducing atmosphere or a low-oxygen partial pressure atmosphere, for example. The firing conditions of the composite green body 111a can be appropriately determined.

In step S03, the ceramic body 111 and the underlying layers 114a, 115a connected to the internal electrodes 112, 113 exposed at the end face E of the ceramic body 111, which constitute the composite green body 111a, are fired simultaneously. This makes it possible to obtain good connectivity between the internal electrodes 12 and 13 and the ground layers 14a and 15a in the composite sintered body 11a after firing.

More specifically, the internal electrodes 112 and 113 and the underlying layers 114a and 115a, which mainly contain metal, start to shrink at a stage earlier than the ceramic constituting the ceramic body 111. However, the internal electrodes 112 and 113 and the base layers 114a and 115a connected in the unfired stage are integrally shrunk, so that the connection is easily maintained even after sintering.

Therefore, in the multilayer ceramic capacitor 10, the connection between the internal electrodes 12 and 13 and the external electrodes 14 and 15 can be secured. Therefore, in the multilayer ceramic capacitor 10, a decrease in capacitance due to a connection failure between the internal electrodes 12, 13 and the external electrodes 14, 15, or an increase in Equivalent Series Resistance (ESR) is less likely to occur.

3.4 step S04: jet milling

In step S04, the composite sintered body 11a obtained in step S03 is subjected to jet polishing. In the jet polishing, the composite sintered body 11a is ground by blasting an abrasive composed of fine particles, thereby grinding the outer surface Q of the underlying layers 14a and 15a constituting the outer surface of the composite sintered body 11a and the intermediate region P2 of the side surfaces S1 and S2 of the ceramic body 11.

The abrasive used in the jet polishing apparatus M may be formed of, for example, zirconia, alumina, or the like, as long as it has a hardness sufficiently higher than that of the composite sintered body 11 a. The particle diameter of the abrasive may be sufficiently small relative to the composite sintered body 11a, and may be, for example, in the range of 10 μm to 1200 μm.

The inventors of the present application have found that jet polishing is very excellent as a pretreatment to be performed on the composite sintered body 11a for forming the plating layers 14b and 15 b. That is, by performing the jet polishing on the composite sintered body 11a, the entire outer surface of the composite sintered body 11a can be brought into a state suitable for forming the good plating layers 14b and 15 b.

More specifically, in the jet polishing, a large amount of abrasive grains composed of small fine particles each having energy is blown, whereby the impact applied to the outer surface of the composite sintered body 11a can be made uniform. Therefore, in the jet polishing, the uneven shape, that is, the surface roughness Ra can be reduced, regardless of the workability of the surface to be treated.

Therefore, in the jet polishing of the composite sintered body 11a, the surface roughness Ra can be reduced simultaneously with the surface to be treated having significantly different workability in the outer surface Q of the underlying layers 14a and 15a mainly composed of metal and the intermediate region P2 of the side surfaces S1 and S2 of the ceramic body 11 mainly composed of ceramic.

Therefore, the difference Δ Ra between the surface roughness Ra of the outer surface Q of the base layers 14a and 15a and the surface roughness Ra of the intermediate region P2 of the side surfaces S1 and S2 of the ceramic body 11 can be reduced by jet polishing the composite sintered body 11 a. That is, in the laminated ceramic capacitor 10, a structure having a small Δ Ra can be realized by using the jet polishing.

Further, by jet polishing of the composite sintered body 11a, the metal oxide formed on the outer surface Q of the underlying layers 14a, 15a during firing or the like can be uniformly removed. This improves the conductivity of the outer surface Q of the underlying layers 14a and 15a, and thus allows metal to be uniformly deposited by the wet plating method.

The surface roughness Ra of the outer surface of the composite sintered body 11a and the difference Δ R between the surface roughness Ra can be adjusted by the conditions of the jet polishing. The conditions for the jet polishing include, for example, the kind and particle size of the abrasive, the shot size and shot velocity of the abrasive, and the treatment time. The jet polishing in step S04 may be either dry or wet, and any known technique may be applied as needed.

Here, barrel polishing and chemical polishing, which are typical polishing techniques used in the manufacturing process of the laminated ceramic capacitor 10, will be described. By barrel polishing and chemical polishing, the entire outer surface of the composite sintered body 11a cannot be brought into a state suitable for forming the good plating layers 14b and 15b as in the spray polishing of the present embodiment.

That is, in barrel polishing, since the composite sintered bodies 11a are caused to collide with each other, a large impact is unevenly applied to the outer surface of the composite sintered body 11 a. Therefore, in the barrel polishing, the difference Δ Ra in the surface roughness Ra tends to be large between the outer surface Q of the underlying layers 14a and 15a and the intermediate region P2 of the side surfaces S1 and S2 of the ceramic body 11, which have significantly different workability.

In the chemical polishing, the outer surface of the composite sintered body 11a is dissolved. The uneven shape is enlarged by dissolution on the outer surface Q of the base layers 14a and 15a, and the surface roughness Ra is likely to increase. This makes it easy for the plating layers 14b and 15b formed on the outer surfaces Q of the underlying layers 14a and 15a to be uneven.

The metal oxide formed on the outer surface Q of the underlying layers 14a and 15a during firing or the like can be dissolved and removed by chemical polishing. However, in the chemical polishing, the ceramic body 11 is dissolved together with the metal oxide, and therefore, the appearance defect or the life defect of the multilayer ceramic capacitor 10 is likely to occur.

3.5 step S05: formation of a coating

In step S05, plating layers 14b and 15b are formed on the composite sintered body 11a subjected to the jet polishing in step S04. The plating layers 14b and 15b are formed by an electrolytic or electroless wet plating method. Thus, the external electrodes 14 and 15 are completed, and the multilayer ceramic capacitor 10 shown in fig. 1 to 4 is obtained.

Fig. 10 is a diagram showing the procedure of step S05. The growth of the plating layers 14b and 15b is promoted on the outer surfaces Q of the highly conductive base layers 14a and 15 a. Further, since the outer surfaces Q of the underlying layers 14a and 15a have no unevenness in conductivity and have small surface roughness Ra over the entire surface, the growth of the plating layers 14b and 15b proceeds uniformly.

On the other hand, in the intermediate region P2 of the side surfaces S1 and S2 of the ceramic body 11 having low conductivity, it is difficult to form the plated layers 14b and 15 b. Therefore, the plating layers 14b and 15b are not formed in most of the middle region P2 of the side surfaces S1 and S2 of the ceramic body 11, which is expanded in the center in the X-axis direction.

However, in the intermediate region P2 of the side surfaces S1, S2 of the ceramic main body 11, the metal is attracted (induced) by the deposition of the metal on the outer surfaces Q of the underlying layers 14a, 15a, and the deposition of the metal occurs at both ends in the X-axis direction adjacent to the underlying layers 14a, 15 a. Thereby, the extension portions 14b1, 15b1 of the plating layers 14b, 15b are formed.

In particular, in the present embodiment, in the intermediate region P2 of the side faces S1, S2 of the ceramic main body 11, the surface roughness Ra is close to the outer surface Q of the base layers 14a, 15a, i.e., has the same smoothness. Therefore, the intermediate region P2 of the side surfaces S1, S2 of the ceramic main body 11 constitutes a series of smooth surfaces together with the outer surfaces Q of the underlying layers 14a, 15 a.

Therefore, in the intermediate region P2 between the side surfaces S1 and S2 of the ceramic main body 11, the growth of the extending portions 14b1 and 15b1 at both ends in the X-axis direction is promoted by the potential force of the growth of the plating layers 14b and 15b on the outer surfaces Q of the underlying layers 14a and 15 a. This reduces the contact angle θ of the extending portions 14b1 and 15b 1.

4. Examples and comparative examples

As examples and comparative examples of the present invention, 100 samples of the laminated ceramic capacitors 10 having different differences Δ Ra in surface roughness Ra were produced by the same production method as described above by changing the polishing conditions. In the laminated ceramic capacitor 10 of each configuration, the configuration is the same except for the surface roughness Ra.

In the laminated ceramic capacitor 10 having each configuration, the presence or absence of defects such as unevenness and peeling of the plating layers 14b and 15b was evaluated, and the number of samples in which defects occurred in the plating layers 14b and 15b was counted. Fig. 11 is a graph showing the results, and a graph (plot) is shown in which the difference Δ Ra in the surface roughness Ra is plotted on the horizontal axis and the defect rates of the plating layers 14b and 15b are plotted on the vertical axis for the laminated ceramic capacitor 10 of each configuration.

As shown in fig. 11, in the multilayer ceramic capacitor 10 having the configuration in which the difference Δ Ra in the surface roughness Ra is 40nm or less, defects of the plating layers 14b and 15b do not occur. In the laminated ceramic capacitor 10 having the difference Δ Ra in surface roughness Ra exceeding 40nm, the defects of the plating layers 14b and 15b tend to occur more frequently as the difference Δ Ra in surface roughness Ra becomes larger.

It is also found that in the multilayer ceramic capacitor 10 having the configuration in which the difference Δ Ra in the surface roughness Ra is 30nm or less, particularly high solder wettability can be obtained, and the plating layers 14b and 15b can be formed more favorably. In the multilayer ceramic capacitor 10 having the difference Δ Ra in surface roughness Ra of 30nm or less, it is found that the stresses applied to the end region P1 and the intermediate region P2 of the side faces S1 and S2 are equal in the ceramic body 11 during the formation of the plated layers 14b and 15b, and therefore cracks are less likely to occur.

Further, in order to make the difference Δ Ra in the surface roughness Ra smaller than 10 μm, it is necessary to increase the processing time of the jet polishing, to improve the accuracy of the polishing conditions such as the particle diameter of the abrasive, and the like, and therefore, the manufacturing cost is greatly increased. Therefore, the difference Δ Ra in the surface roughness Ra is preferably 10 μm or more.

5. Other embodiments

While the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications may be made.

For example, the present invention can be applied not only to a laminated ceramic capacitor but also to all ceramic electronic components having a structure including a pair of external electrodes. Examples of the ceramic electronic component to which the present invention can be applied include a chip varistor, a chip thermistor, and a multilayer inductor, in addition to a multilayer ceramic capacitor.

The circuit board of the present invention can be configured using the ceramic electronic component of the present invention. As an example, the circuit board 200 shown in fig. 12 includes: the laminated ceramic capacitor 10 of the above embodiment; a substrate main body 201; a pair of terminals 202; and solder 203. A pair of terminals 202 is provided on the substrate main body 201. The external electrodes 14 and 15 of the multilayer ceramic capacitor 10 are bonded to the pair of terminals 202 via solders 203, respectively. In the circuit board 200, since the plating layers 14b and 15b of the external electrodes 14 and 15 have high solder wettability, more reliable bonding between the external electrodes 14 and 15 and the pair of terminals 202 via the solder 203 can be obtained.