Clock adjusting circuit and method for stably capturing Beidou satellite signals
阅读说明：本技术 一种北斗卫星信号稳定捕获的调钟电路及方法 (Clock adjusting circuit and method for stably capturing Beidou satellite signals ) 是由 范梦怡 于 2021-01-14 设计创作，主要内容包括：本发明涉及一种北斗卫星信号稳定捕获的调钟电路及方法,该调钟电路包括压控晶振、数模转换器和三个等效电阻组成的电阻网络,DAC输出端经等效电阻R1连接压控晶振的压控端,供电端经等效电阻R2连接压控端,压控端经等效电阻R3接地。该调钟方法包括：初始化DAC输出电压V-(DA)；判断是否已捕获卫星信号,是则接收成功,否则以左右往复调频的方式逐步扩大扫频范围,在电压初始值左右往复取点并判断是否已捕获卫星信号,是则接收成功,否则判断V-(DA)是否超过取值范围,是则接收失败,等待重发,否则继续取值。该调钟电路及方法以低成本、轻量化的方式解决了北斗导航卫星通信终端的时钟偏移问题,有效提高了系统长时间高性能工作的稳定性。(The invention relates to a clock circuit and a method for stably capturing Beidou satellite signals R 1 is connected with the voltage-controlled end of the voltage-controlled crystal oscillator, and the power supply end is connected with the voltage-controlled end of the voltage-controlled crystal oscillator through an equivalent resistor R 2 connecting the voltage-controlled terminal via an equivalent resistor R 3 to ground. The clock adjusting method comprises the following steps: initializing DAC output voltages V DA (ii) a Judging whether the satellite signal is captured, if so, successfully receiving, otherwise, gradually expanding the sweep frequency range in a left-right reciprocating frequency modulation mode, repeatedly taking points around the voltage initial value and judging whether the satellite signal is captured, if so, successfully receiving, otherwise, judging whether the satellite signal is captured V DA If the value range is exceeded, if so, the receiving fails, the retransmission is waited, otherwise, the value range is continuously takenThe value is obtained. The clock adjusting circuit and the clock adjusting method solve the clock offset problem of the Beidou navigation satellite communication terminal in a low-cost and light-weight mode, and effectively improve the stability of long-time high-performance work of the system.)
1. The clock adjusting circuit for stable capture of Beidou satellite signals is characterized by comprising a voltage-controlled crystal oscillator, a digital-to-analog converter (DAC) and a resistor network consisting of three equivalent resistors, wherein the output end of the DAC is connected with the voltage-controlled end of the voltage-controlled crystal oscillator through a first equivalent resistor R1, the power supply end is connected with the voltage-controlled end through a second equivalent resistor R2, and the voltage-controlled end is grounded through a third equivalent resistor R3.
2. The tuning circuit for stable acquisition of Beidou satellite signals according to claim 1, characterized in thatThe voltage-controlled crystal oscillator is a high-precision voltage-controlled crystal oscillator, the power supply range of the voltage-controlled crystal oscillator is 2.7V to 3.3V, and the voltage range V of a voltage-controlled endCONTThe crystal oscillator frequency can be adjusted to be within a range of +/-8 ppm to +/-15 ppm and is linearly changed, and the frequency deviation of the crystal oscillator is +/-0.5 ppm when the crystal oscillator is 1.5 +/-1V.
3. The clock circuit for stable capturing of Beidou satellite signals according to claim 1, wherein the resolution of the DAC is 10 bits, the power supply voltage is 3.3V, and communication can be carried out through the SPI.
4. The clock circuit for stable capturing of Beidou satellite signals according to claim 1, wherein a resistor network consisting of a first equivalent resistor R1, a second equivalent resistor R2 and a third equivalent resistor R3 has a proportionality coefficient according to VCONT＝α·VDA+ β.VCC, wherein VDAFor the DAC output voltage, VCC is the supply voltage,
5. the clock circuit for stable capturing of Beidou satellite signals according to claim 4, characterized in that: according to kirchhoff's current law, the values of all components R1, R2 and R3 in the resistor network are R1: r2: r3 ═ 1.25: 15: 3, and the supply voltage VCC at the pull-up end of R2 is 3V.
6. The clock adjusting method for stably capturing the Beidou satellite signals based on the clock adjusting circuit of any one of claims 1 to 5, is characterized by comprising the following steps of:
1) for DAC output voltage VDACarrying out initialization;
2) judging whether the satellite signal is captured or not, if so, successfully receiving, and otherwise, turning to the next step;
3) gradually expanding the sweep frequency range in a left-right reciprocating frequency modulation mode, reciprocating point acquisition at the left and right sides of the voltage initial value, judging whether the satellite signal is captured once, if so, successfully receiving, and otherwise, turning to the next step;
4) judgment voltage VDAIf the value exceeds the value range, the receiving fails and the retransmission is waited, otherwise, the step 3 is returned to continue the value taking.
7. The method of claim 6, wherein the frequency hopping interval is set to 1KHz, and the number of frequency modulation points is set to 60; the initial voltage of the DAC is 2V, the adjusting range is 0.8V to 3.2V, and the jitter interval is 40 mV.
Technical Field
The invention belongs to the technical field of Beidou navigation, and particularly relates to a clock adjusting circuit and method for stably capturing Beidou satellite signals.
Background
In the Beidou navigation satellite system, the stability and the precision of the system crystal oscillator frequency simultaneously influence the modulation and demodulation process of a baseband signal, and the success rate of communication is directly related, so that the system can be regarded as the heart of the system. In the Beidou RDSS system, the influence of a clock signal on a receiving channel is more prominent, and when the frequency deviation is generated by the output of a crystal oscillator, the receiving channel is more difficult to track and capture the Beidou satellite signal.
In an actual environment, the frequency deviation, temperature, power supply voltage, load change and operating time of the crystal oscillator affect the frequency deviation of the crystal oscillator. The influence of the length of the working time is the most serious, and along with the increase of the working time of the communication terminal, the frequency error of the offset of the crystal oscillator frequency of the system is larger after frequency doubling, so that the frequency of an intermediate frequency signal obtained by down-conversion is influenced, and the processes of capturing, demodulating, modulating and the like of the Beidou satellite signal are directly influenced. Therefore, solving the frequency offset problem plays a crucial role for the communication system.
Disclosure of Invention
In view of this, the present invention provides a clock circuit and a method for stably capturing a beidou satellite signal, which are beneficial to improving the stability of a system in long-time operation, resisting the influence of a severe environment, and prolonging the service life of a communication terminal.
In order to achieve the purpose, the invention adopts the following technical scheme: a clock circuit for stable capture of Beidou satellite signals comprises a voltage-controlled crystal oscillator, a digital-to-analog converter (DAC) and a resistor network consisting of three equivalent resistors, wherein the output end of the DAC is connected with the voltage-controlled end of the voltage-controlled crystal oscillator through a first equivalent resistor R1, the power supply end is connected with the voltage-controlled end through a second equivalent resistor R2, and the voltage-controlled end is grounded through a third equivalent resistor R3.
Further, the voltage-controlled crystal oscillator is a high-precision voltage-controlled crystal oscillator, the power supply range of the voltage-controlled crystal oscillator is 2.7V to 3.3V, and the voltage range V of a voltage-controlled endCONTThe crystal oscillator frequency can be adjusted to be within a range of +/-8 ppm to +/-15 ppm and is linearly changed, and the frequency deviation of the crystal oscillator is +/-0.5 ppm when the crystal oscillator is 1.5 +/-1V.
Furthermore, the resolution of the DAC is 10 bits, the power supply voltage is 3.3V, and communication can be carried out through the SPI.
Furthermore, the proportion coefficient of the resistor network consisting of the first equivalent resistor R1, the second equivalent resistor R2 and the third equivalent resistor R3 is according to VCONT＝α·VDA+ β.VCC, wherein VDAFor the DAC output voltage, VCC is the supply voltage,
further, analysis is carried out according to kirchhoff's current law, and the values of all components R1, R2 and R3 in the resistor network are R1: r2: r3 ═ 1.25: 15: 3, and the supply voltage VCC at the pull-up end of R2 is 3V.
The invention also provides a clock adjusting method for stably capturing the Beidou satellite signals based on the clock adjusting circuit, which comprises the following steps of:
1) for DAC output voltage VDACarrying out initialization;
2) judging whether the satellite signal is captured or not, if so, successfully receiving, and otherwise, turning to the next step;
3) gradually expanding the sweep frequency range in a left-right reciprocating frequency modulation mode, reciprocating point acquisition at the left and right sides of the voltage initial value, judging whether the satellite signal is captured once, if so, successfully receiving, and otherwise, turning to the next step;
4) judgment voltage VDAIf the value exceeds the value range, the receiving fails and the retransmission is waited, otherwise, the step 3 is returned to continue the value taking.
Furthermore, the frequency hopping interval is set to be 1KHz, and the number of frequency modulation points is set to be 60; the initial voltage of the DAC is 2V, the adjusting range is 0.8V to 3.2V, and the jitter interval is 40 mV.
Compared with the prior art, the invention has the following beneficial effects: according to the invention, by a method of combining software and hardware, the clock offset problem is solved in a low-cost and light-weight manner, the Beidou communication terminal can be ensured to accurately capture Beidou satellite signals all the time in the long-time working process, and the stability of the long-time high-performance working of the system is effectively improved. The service life of the system is prolonged, and meanwhile, the communication success rate of the system in a severe environment can be improved. In addition, the method of the invention is not limited by the conditions of voltage-controlled crystal oscillator, DAC, power supply voltage VCC and the like, and different hardware schemes can be flexibly adapted by adjusting parameters.
Drawings
Fig. 1 is a circuit schematic of an embodiment of the invention.
Fig. 2 is a linear characteristic diagram of the voltage controlled crystal oscillator according to the embodiment of the present invention.
Fig. 3 is a flow chart of a method of an embodiment of the present invention.
Fig. 4 shows the test results of the tuning spectrum in the embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments.
As shown in fig. 1, the present embodiment provides a clock circuit for stable capturing of beidou satellite signals, which includes a voltage-controlled crystal oscillator, a digital-to-analog converter DAC, and a resistor network composed of three equivalent resistors, where the DAC output end is connected to the voltage-controlled end of the voltage-controlled crystal oscillator through a first equivalent resistor R1, the power supply end is connected to the voltage-controlled end through a second equivalent resistor R2, and the voltage-controlled end is grounded through a third equivalent resistor R3. Wherein, VDAFor DAC outputting voltage, VCONTFor voltage controlled terminal voltages, VCC is the supply voltage.
In this embodiment, the resolution of the DAC is 10 bits, the supply voltage is 3.3V, and communication can be performed through the SPI. The voltage-controlled crystal oscillator is a high-precision voltage-controlled crystal oscillator, the power supply range of the voltage-controlled crystal oscillator is 2.7V to 3.3V, and the voltage range of the voltage-controlled end is VCONTThe crystal oscillation frequency can be adjusted to be between +/-8 ppm and +/-15 ppm and is linearly changed when the crystal oscillation frequency is 1.5 +/-1V. The self frequency deviation of the crystal oscillator is +/-0.5 ppm, the temperature is +/-0.5 ppm, the power supply voltage is +/-0.2 ppm, the load change is +/-0.2 ppm, and the working time is +/-1 ppm/year. For example, the crystal oscillator will have an accumulated deviation of ± 6.4ppm (1ppm to 10Hz) when operating for 5 years. The central frequency of the Beidou satellite signal S frequency point is 2491.75MHz, and in order to down-convert the Beidou satellite signal S frequency point to 12.24MHz, the frequency of a clock signal needs to be approximately 248 multiplied during frequency synthesis. So that after 5 years the maximum frequency deviation of the intermediate frequency signal is about 16 KHz. In view of the above, it is desirable to provide,the linear characteristic of the voltage controlled crystal oscillator is shown in fig. 2.
In combination with linear proportional relationship analysis, when the voltage range V of the voltage-controlled end isCONTWhen the crystal oscillator frequency is 1.5 +/-0.8V, the variation range of the crystal oscillator frequency is +/-6.4 ppm to +/-12 ppm (namely, the intermediate frequency is +/-16 KHz to +/-30 KHz), and the frequency deviation range caused by 5-year crystal oscillator aging can be covered. According to the performance requirement and the test method of the Beidou user terminal RDSS unit, in order to quickly capture satellite signals with power of-127.6 dBm, the frequency deviation of the intermediate frequency signals needs to be controlled within +/-1 KHz.
The clocked resistor network shown in fig. 1 can be obtained according to kirchhoff's current law:
after simplification, the method can be obtained:
let VCC be 3V, VDAIs 2V (in this case V)CONT1.5V is the most suitable point when the voltage controlled crystal oscillator is shipped from the factory). To let VDAUndertake control and VCC undertake stabilization, requiring V to be adjusted upDAThe coefficient of VCC is turned down, assuming:
will VDACoefficient of (C), coefficient of VCC and VCONTThe variation range of (3) is taken into the formula (2), and V is calculatedDAIs controlled in the range of 0.8V to 3.2V. By combining and simplifying the formulas (3) and (4), the following can be obtained:
for convenience of resistance value, when R3 is 3K, R2 is 15K, which is taken back to formula (4), and R1 is 1.25K.
Based on the clock circuit, the invention provides a clock method for stably capturing Beidou satellite signals, which comprises the following steps as shown in fig. 3:
1) for DAC output voltage VDACarrying out initialization;
2) judging whether the satellite signal is captured or not, if so, successfully receiving, and otherwise, turning to the next step;
3) gradually expanding the sweep frequency range in a left-right reciprocating frequency modulation mode, reciprocating point acquisition at the left and right sides of the voltage initial value, judging whether the satellite signal is captured once, if so, successfully receiving, and otherwise, turning to the next step;
4) judgment voltage VDAIf the value exceeds the value range, the receiving fails and the retransmission is waited, otherwise, the step 3 is returned to continue the value taking.
In order to cover the crystal oscillator offset range, meet the requirement of quickly capturing a satellite signal of-127.6 dBm and adapt to the communication frequency of a Beidou satellite 60S, the frequency hopping interval of the invention is set to be 1KHz, and the number of frequency modulation points is set to be 60. From the output range of the DAC, when 60 points are taken, the initial voltage of the DAC is 2V, and the jitter interval should be 40 mV.
Through detailed theoretical analysis and calculation, the software and hardware combined method provided by the invention can solve the clock skew problem and effectively improve the stability of long-time high-performance work of the system.
On the basis of completing circuit design and algorithm analysis, the test and verification can be carried out through a spectrum analyzer. The center frequency of the spectrum analyzer is set to be 10MHz, the spectrum of each time of tuning can be overlapped through the Max Hold function, and the test result is shown in FIG. 4.
Carefully observing the distribution situation and Mark points of a frequency spectrum diagram, 16 wave crests are respectively arranged at the left and right of the center frequency, the interval between the wave crests is 4.1Hz, the frequency of the wave crests is about 1.015KHz after frequency multiplication of a frequency synthesizer, and the wave crests only deviate from 1KHz analyzed theoretically by 15Hz, so that the design requirement is completely met. The frequency offset is mainly caused by crystal oscillator precision error, resistance value deviation, DAC conversion error and the like, so the frequency accuracy can be improved by selecting a DAC or a resistor with higher precision.
The invention can simulate the modulated signal with frequency offset through the signal source, and test the DAC output voltage, the voltage-controlled terminal voltage, the clock frequency and the capture time in detail, and the test result is shown in table 1.
TABLE 1
The test data of the invention is basically consistent with the theoretical design, the central frequency of the crystal oscillator can be stabilized at about 10MHz by the pressure control voltage within the design range, and the Beidou satellite signals can be recaptured in the clock adjusting process. The environment simulation experiment shows that the clock adjusting circuit and the method provided by the invention have practical use value.
The invention effectively improves the stability of long-time high-performance work of the system while solving the problem of clock skew, and can ensure that the Beidou RDSS communication terminal can accurately capture signals for a long time under the condition of high receiving sensitivity.
The above are preferred embodiments of the present invention, and all changes made according to the technical scheme of the present invention that produce functional effects do not exceed the scope of the technical scheme of the present invention belong to the protection scope of the present invention.
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