阅读说明：本技术 步进编程脉冲操作中决定快速通过写入操作的方法与系统 (Method and system for determining fast-pass write operation in step-by-step programming pulse operation ) 是由 黄昱闳 程政宪 古绍泓 陈映仁 于 2019-11-04 设计创作，主要内容包括：本发明公开了步进编程脉冲操作中决定快速通过写入操作的方法与系统。快速通过写入操作是在步进编程脉冲操作中同时施加一位线电压。此方法包括：依照变化在第一范围内的多个位线电压以及变化在第二范围内相对验证电压的多个电压差值,估计在该位线电压与该电压差值下所得到阈值电压分布宽度的缩减量,得到缩减量地形图。依照多个该位线电压以及多个该电压差值,估计施加该步进编程脉冲操作达到该编程验证电压所需要的编程枪数,得到编程枪数地形图。将缩减量地形图与编程枪数地形图叠置后,决定由该位线电压的施加范围以及该电压差值的施加范围所构成的操作区域。(The invention discloses a method and a system for determining a fast-pass write operation in a step-by-step programming pulse operation. The quick pass write operation is a simultaneous application of a bit line voltage in a step programming pulse operation. The method comprises the following steps: according to a plurality of bit line voltages changing in a first range and a plurality of voltage difference values changing in a second range relative to the verification voltage, the reduction amount of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference values is estimated, and a reduction amount topographic map is obtained. Estimating the programming gun number required for applying the stepping programming pulse operation to reach the programming verification voltage according to a plurality of bit line voltages and a plurality of voltage difference values to obtain a programming gun number topographic map. After the reduction amount map and the program gun number map are superimposed, an operation region constituted by an application range of the bit line voltage and an application range of the voltage difference is determined.)

1. A method for determining a fast pass write operation in a step program pulse operation, the step program pulse operation being applied to a plurality of memory cells of a memory cell array, the fast pass write operation being a fast pass write operation initiated after a gate voltage reaches a pre-program verify voltage that is less than a program verify voltage, wherein there is a voltage difference from the pre-program verify voltage to the program verify voltage, the fast pass write operation being a simultaneous application of a bit line voltage in the step program pulse operation, the method for determining the fast pass write operation comprising:

estimating the reduction of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference value according to a plurality of bit line voltages changing in a first range and a plurality of voltage difference values changing in a second range to obtain a reduction topographic map;

estimating the programming gun number required by applying the stepping programming pulse operation to reach the programming verification voltage according to a plurality of bit line voltages and a plurality of voltage difference values to obtain a programming gun number topographic map; and

after the reduction amount map and the program gun number map are superimposed, an operation region constituted by an application range of the bit line voltage and an application range of the voltage difference is determined.

2. The method of claim 1, wherein the reduction in the width of the threshold voltage distribution is estimated at a step voltage for each of the bit line voltages, comprising:

under the voltage corresponding to the bit line and the stepping voltage, estimating the change curves of the threshold voltage relative to the grid voltage of different voltage difference values;

estimating a slope at the program verify voltage under the voltage difference according to the variation curve; and

estimating the decrement of 0V relative to the bit line voltage according to the slope and the step voltage,

wherein the bit line voltage is a plurality of discrete analysis values from 0V to a predetermined value.

3. The method of claim 1, wherein the operation region comprises a triangle, and a bottom of the triangle is a range of the bit line voltage.

4. The method of claim 1, wherein the reduced amount topographic map determines a first selected region according to a height of the bit line voltage, the program gun number topographic map determines a second selected region according to the height of the program gun number, and at least a portion of an overlapping region of the first selected region and the second selected region is defined as an operating region.

5. The method of claim 1, wherein estimating the reduction in the width of the threshold voltage distribution comprises model-comparing the bit line voltage, the voltage difference, and the step voltage with experimental data to determine model correctness.

6. A system for determining a fast-pass write operation in a step-by-step program pulse operation, the step-by-step program pulse operation being performed on a plurality of memory cells of a memory cell array, the fast-pass write operation being performed by starting a fast-pass write operation after a gate voltage reaches a pre-program-verify voltage that is less than a program-verify voltage, wherein a voltage difference is applied from the pre-program-verify voltage to the program-verify voltage, the fast-pass write operation being performed by simultaneously applying a bit line voltage in the step-by-step program pulse operation,

the system for determining a quick pass write operation comprises an analysis circuit and an analysis program storage unit, wherein the analysis circuit is configured to obtain an analysis program from the analysis program storage unit and operate the storage unit array to execute the following steps:

estimating the reduction of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference value according to a plurality of bit line voltages changing in a first range and a plurality of voltage difference values changing in a second range to obtain a reduction topographic map;

estimating the programming gun number required by applying the stepping programming pulse operation to reach the programming verification voltage according to a plurality of bit line voltages and a plurality of voltage difference values to obtain a programming gun number topographic map; and

after the reduction amount map and the program gun number map are superimposed, an operation region constituted by an application range of the bit line voltage and an application range of the voltage difference is determined.

7. The system of claim 6, wherein the decrement in the width of the threshold voltage distribution is estimated at a step voltage for each of the bit line voltages, comprising:

under the voltage corresponding to the bit line and the stepping voltage, estimating the change curves of the threshold voltage relative to the grid voltage of different voltage difference values;

estimating a slope at the program verify voltage under the voltage difference according to the variation curve; and

estimating the decrement of 0V relative to the bit line voltage according to the slope and the step voltage,

wherein the bit line voltage is a plurality of discrete analysis values from 0V to a predetermined value.

8. The system of claim 6, wherein the operation region comprises a triangle, the bottom of the triangle being a range of the bit line voltage.

9. The system of claim 6, wherein the reduced amount map determines a first selected region according to a height of the bit line voltage, the program gun number map determines a second selected region according to the height of the program gun number, and at least a portion of an overlapping region of the first selected region and the second selected region is set as an operation region.

10. The system of claim 6, wherein the estimating of the reduction in the width of the threshold voltage distribution comprises model-comparing the bit line voltage, the voltage difference, and the step voltage based on predetermined samples to experimental data to determine model correctness.

Technical Field

The present invention relates to memory operation technology, and more particularly, to a method and system for determining a Quick Pass Write (QPW) operation in an Increment Step Pulse Programming (ISPP) operation.

Background

In response to the wide application of various electronic products, flash memories are steadily growing in the market. In order to increase the storage capacity, the structure of the memory cell has also been developed into a memory cell capable of storing multiple bits, such as a multi-level-cell (MLC), which uses different levels of threshold voltages of the memory transistors to correspond to the stored data, so as to achieve multi-bit storage. The flash memory is more, for example, a NAND type flash memory, but is not limited thereto.

Since the threshold voltages of the transistors of the memory are not completely uniform, the threshold voltage of each order of the transistors is actually a packet distribution. When the memory cell is a multi-level cell (MLC) structure, it has multiple packets spread between 0V and program-verify (PV) voltage. If the width of the distribution of packets is large, the tail ends of two adjacent packets are likely to overlap. If the threshold voltage of the read data falls in the overlap region, a data determination error may be caused, which requires a subsequent complicated procedure to correct the error code.

If the width of the distribution of the threshold voltage envelope can be reduced, it can be expected to reduce the overlap area. This is one of the issues that needs to be continuously developed in the operation of multi-level memory cells.

Disclosure of Invention

The present invention provides a method and system for determining a fast-pass write operation in a step-and-program pulse operation. The invention can determine the time point of introducing the quick pass write operation in the step programming pulse operation, wherein the bit line voltage of the quick pass write operation can also be set cooperatively, so that the optimized operating area formed by the bit line voltage and the time point of the quick pass write operation can be estimated.

In one embodiment, the present invention provides a method for determining a fast pass write operation in a step program pulse operation. The step programming pulse operation is firstly applied to a plurality of memory cells of the memory cell array, and the quick pass write operation is started after the grid voltage reaches a pre-programming verification voltage smaller than a programming verification voltage. The fast pass write operation is a step program pulse operation in which a bit line voltage is simultaneously applied. The method for determining the quick pass write operation comprises the steps of estimating the reduction amount of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference value according to a plurality of bit line voltages changing in a first range and a plurality of voltage difference values changing in a second range, and obtaining a reduction amount topographic map. And estimating the programming gun number required by applying the stepping programming pulse operation to reach the programming verification voltage according to a plurality of bit line voltages and a plurality of voltage difference values to obtain a programming gun number topographic map. After the reduction amount map and the program gun number map are superimposed, an operation region constituted by an application range of the bit line voltage and an application range of the voltage difference is determined.

In one embodiment, for the method of determining a fast pass write operation, the reduction in the width of the threshold voltage distribution is estimated for each of the bit line voltages at a step voltage, which includes estimating a variation curve of the threshold voltage versus the gate voltage for different voltage differences corresponding to the bit line voltage and the step voltage. A slope at the program verify voltage at the voltage difference is estimated according to the variation curve. Estimating the decrement of 0V relative to the bit line voltage according to the slope and the step voltage. The bit line voltage is a plurality of discrete analysis values from 0V to a predetermined value.

In one embodiment, for the method of determining a quick pass write operation, the operating region includes a triangle, the bottom of the triangle being the range of the bit line voltages.

In one embodiment, for the method of determining a fast pass write operation, the reduced amount topographic map determines a first selected region according to a height of the bit line voltage, the program gun number topographic map determines a second selected region according to the height of the program gun number, and at least a portion of an overlapping region of the first selected region and the second selected region is set as an operating region.

In one embodiment, for the method of determining a fast pass write operation, the estimating of the reduction of the width of the threshold voltage distribution comprises performing a model comparison of the bit line voltage, the voltage difference and the step voltage according to predetermined samples with experimental data to determine the correctness of the model.

In one embodiment, the present invention further provides a system for determining a fast pass write operation in a step program pulse operation. The step programming pulse operation is firstly applied to a plurality of memory cells of the memory cell array, and the quick pass write operation is started after the grid voltage reaches a pre-programming verification voltage smaller than a programming verification voltage. There is a voltage difference from the pre-program-verify voltage to the program-verify voltage. The fast pass write operation is a simultaneous application of a bit line voltage in a step programming pulse operation. The system for determining a quick pass write operation includes an analysis circuit and an analysis program storage unit, wherein the analysis circuit is configured to obtain an analysis program from the analysis program storage unit to operate the memory cell array, so as to perform the following steps including estimating a reduction amount of a threshold voltage distribution width obtained under a bit line voltage and a voltage difference value according to the bit line voltage and the voltage difference value, wherein the bit line voltage and the voltage difference value are changed within a first range, and obtaining a reduction amount topographic map. Estimating the programming gun number required for applying the stepping programming pulse operation to reach the programming verification voltage according to a plurality of bit line voltages and a plurality of voltage difference values to obtain a programming gun number topographic map. After the reduction amount map and the program gun number map are superimposed, an operation region constituted by an application range of the bit line voltage and an application range of the voltage difference is determined.

In one embodiment, for the system for determining a fast pass write operation, the reduction in the width of the threshold voltage distribution is estimated for each of the bit line voltages at a step voltage, including estimating a variation curve of the threshold voltage versus the gate voltage for different voltage differences at the corresponding bit line voltage and the step voltage. According to the variation curve, the slope at the program verify voltage under the voltage difference is estimated. Estimating the decrement of 0V relative to the bit line voltage according to the slope and the step voltage. The bit line voltage is a plurality of discrete analysis values from 0V to a predetermined value.

In one embodiment, for the system for determining a fast pass write operation, the operating region includes a triangle, the bottom of the triangle being the range of the bit line voltages.

In one embodiment, for the system for determining a fast pass write operation, the reduced amount map determines the first selected region based on a height of the bit line voltage. The programmed gun number topographic map determines a second selected area according to the height of the programmed gun number. At least a part of the overlapping area of the first selection area and the second selection area is set as an operation area.

In one embodiment, for the system for determining a fast pass write operation, the estimating of the reduction of the width of the threshold voltage distribution comprises performing a model comparison of the bit line voltage, the voltage difference and the step voltage according to predetermined samples with experimental data to determine the correctness of the model.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating threshold voltage distributions of multiple MLC memory cells in a memory device corresponding to multiple levels according to an embodiment of the invention.

FIG. 2 is a graph illustrating the measured variation of the threshold voltage (Vt) versus the gate voltage (Vg) of a memory cell, in accordance with one embodiment of the present invention.

FIG. 3 is a graph of the conversion of the data from FIG. 2 into an effective current density (J), in accordance with one embodiment of the present invention_pgm) Relative effective gate voltage (Vg)_eff) The curve of the inverse of (1) is shown schematically.

FIG. 4 is a schematic diagram of a mechanism for performing step programming pulse (ISPP) operation in conjunction with Quick Pass Write (QPW) operation in the linear region of Vt versus Vg, in accordance with one embodiment of the present invention.

FIG. 5 is a graph illustrating the slope of the curve according to FIG. 2 at the program verify voltage according to the variation of the voltage difference (Δ PV) from the pre-program verify voltage to the program verify voltage, in accordance with an embodiment of the present invention.

FIG. 6 is a graph illustrating the accumulation rate of memory cells actually measured according to the variation of the voltage difference (Δ PV) from the pre-program-verify voltage to the program-verify voltage, in accordance with one embodiment of the present invention.

FIG. 7 is a graph illustrating comparison of simulation data and measurement data for a reduction in width of a threshold voltage envelope distribution according to a change in a voltage difference (Δ PV) from a pre-program verify voltage to a program verify voltage, in accordance with one embodiment of the present invention.

FIG. 8 is a schematic diagram of a reduced quantity topographic map and a programmed gun count topographic map in accordance with one embodiment of the present invention.

FIG. 9 is a schematic diagram of the operating region of a Quick Pass Write (QPW) operation determined after overlap of a reduced amount topographic map and a program gun number topographic map, in accordance with one embodiment of the present invention.

FIG. 10 is a block diagram of a system for determining a fast pass write operation according to an embodiment of the present invention.

[ notation ] to show

10 reduction amount

100 reduced amount topographic map

102. 104 region (c)

110 topographic map of programmed gun number

112. 114 region (c)

200 analysis circuit

202 memory cell array

204 memory cell

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

The invention can determine the time point for introducing the quick pass write operation in the step programming pulse operation, wherein the bit line voltage of the Quick Pass Write (QPW) operation can also be set cooperatively, so that the optimized operation area formed by the bit line voltage and the time point of the quick pass write operation can be estimated. The model of the reduced quantity topographic map and the programming gun number topographic map established according to the invention can determine the time for introducing the Quick Pass Write (QPW) operation and the applicable bit line voltage range after the interleaving comparison of the reduced quantity topographic map and the programming gun number topographic map.

The invention is illustrated below by means of some examples, but is not limited to the examples.

FIG. 1 is a diagram illustrating threshold voltage distributions of multiple MLC memory cells in a memory device corresponding to multiple levels according to an embodiment of the invention. Referring to fig. 1, a threshold voltage distribution at the upper portion is generally possible. For example, a two bit memory cell, which has four threshold voltages versus four memory states. The tail regions of the threshold voltage distributions corresponding to the respective steps may overlap. For example, the threshold voltage value read from the memory cell falls in the overlap region, which may make it difficult to determine the corresponding packet, and may even cause data errors, and then require a complicated error code correction process.

With continued reference to the lower portion of fig. 1, if the width of the threshold voltage distribution can be properly reduced, the threshold voltages of the respective levels can be clearly distinguished to reduce the occurrence probability of erroneous data.

The invention adopts the mode of properly introducing QPW operation under the ISPP operation, and can retract the trailing edge of the threshold voltage distribution packet, thereby at least reducing the overlapping area with the next packet.

Before estimating the mode of QPW operation, the present invention first explores and verifies the variation of some operation parameters corresponding to ISPP operation and QPW operation, and then determines the condition of QPW operation.

FIG. 2 is a graph illustrating the measured variation of the threshold voltage (Vt) versus the gate voltage (Vg) of a memory cell, in accordance with one embodiment of the present invention. Referring to fig. 2, actual measurement of the threshold voltage is performed on the memory cells of the memory cell array. A gate voltage (Vg) is applied to the gate of the memory transistor. The gate voltage (Vg) varies from 10V to 20V, for example. The waveform of the gate voltage (Vg) is a pulse, the pulse time width is, for example, 1 microsecond, 2 microseconds, and 3 microseconds, and the change of the threshold voltage with the gate voltage (Vg) can be measured under the ISPP operation.

FIG. 3 is a graph of the conversion of the data from FIG. 2 into an effective current density (J), in accordance with one embodiment of the present invention_pgm) Relative effective gate voltage (Vg)_eff) The curve of the inverse of (1) is shown schematically. Referring to FIG. 3, according to the data of FIG. 2, the current density (J) can be obtained by the following transformation of equations (1) and (2)_pgm) Relative effective gate voltage (Vg)_eff) The slope of the change in reciprocal of (b) to verify that the relationship is linear is β. This ensures that the gate voltage (Vg) of fig. 2 can be used to achieve current density.

Vg_eff＝Vg-V_BL-Vt＝Vg^*-Vt (1)

J_pgm＝C_pp×ΔVt/t_pgm (2)

Wherein V_BLIs the bit line voltage, C_ppIs the capacitance constant, t_pgmIs the pulse width.

Through the verification of FIG. 3, in the ISPP operation, if the bit line voltage (V) is applied at the same time_BL) Its current density is predictable in ISPP operation. The gate voltage (Vg) of the ISPP operation is gradually increased in a stepped manner by the pulse height of the gate voltage (Vg). At this time if the bit line voltage (V)_BL) Is 0V, this operation is a normal ISPP operation. QPW operation refers to the simultaneous application of the bit line voltage (V) during ISPP operation_BL) This causes the voltage on the channel to rise, which in turn causes the write field strength to weaken, slowing the programming speed, which is expected to reduce the width of the threshold voltage distribution.

Further coordinating the bit line voltage (V) in the ISPP operation according to the relationship between the equations (1) and (2)_BL) A prediction of the behavior of the threshold voltage is made. Equations (3) through (5) are added to the ISPP operation and the QPW operation (depending on the bit line potential)Pressure (V)_BL) Value of (a), a voltage difference value (Δ Vt — i) corresponding to the number of program guns (i) under the ISPP operation can be estimated.

ΔVt_{_i}＝J_{pgm_i}×t_pgm/C_pp (5)

FIG. 4 is a schematic diagram of a mechanism for performing step programming pulse (ISPP) operation in conjunction with Quick Pass Write (QPW) operation in the linear region of Vt versus Vg, in accordance with one embodiment of the present invention. Referring to fig. 4, a linear region of fig. 2 is taken, which is a range where the gate voltage (Vg) is greater than 16V. In ISPP operation, the gate voltage (Vg) is increased stepwise. If V_BLThis is an ISPP operation throughout the entire range, 0. When a QPW operation is desired, in the present embodiment, for the target value of the program verify voltage (PV), the voltage value to be initially added to the QPW operation is selected, which is called the pre-program verify voltage (V)_pre-PV) Its program verify voltage (V) against the target_PV) There is a voltage difference (apv). The voltage difference (Δ PV) is defined as:

ΔPV＝V_PV-V_pre-PV (6)

after the program pulse of the gate voltage reaches the pre-program verify voltage (pre-PV), the bit line voltage (V) starts to be applied_BL). Upon application of a non-zero bit line voltage (V)_BL) When it is time to enter QPW mode of operation, its threshold voltage (Vt) will be due to the bit line voltage (V)_BL) A bias is generated, i.e. its slope decreases. When the gate voltage (Vg) reaches the program verify voltage (PV), the slope (S) of the threshold voltage (Vt) with respect to the gate voltage (Vg)_QPW) And therefore the bit line voltage (V)_BL) And the value of (c) varies. Bit line voltage (V) of FIG. 4_BL) The effects of QPW operations are observed, for example, at 0V, 0.4V, 0.8V, and 1.2V.

FIG. 5 is a drawing of a table according to the inventionIn one embodiment of the present invention, the slope of the curve at the program verify voltage according to the curve of FIG. 2 is shown according to the variation of the voltage difference (Δ PV) from the pre-program verify voltage to the program verify voltage. Referring to FIG. 5, the slope (S) is calculated according to the above_QPW) Varying behavior in QPW operation, for each bit line voltage (V)_BL) The slope (S) can be simulated_QPW) Curve of the relative voltage difference (Δ PV). FIG. 5 is, for example, V_BLThe gate voltage of the ISPP is stepped by 0.4V, which is 0.2V. Similarly, other conditions, such as different bit line voltages (V)_BL) There is also a corresponding slope curve. The voltage difference (Δ PV) at the lowest point of the slope is the voltage value corresponding to the entry into QPW operation. Since the program verify voltage (PV) is a fixed value, the voltage difference (Δ PV) is the corresponding pre-program verify voltage (pre-PV). The pre-program verify voltage (pre-PV) is the reference value that is decided to enter QPW operation. According to the slope (S)_QPW) And a step voltage (vsv) which can be multiplied to estimate a reduction amount (threshold value) of the threshold voltage distribution width, for example. Here, the behavior of FIG. 5 is a result of a model (model) according to the present invention to facilitate rapid analysis by the system. However, the present invention also needs to confirm the correctness of the model (model) through experimental data.

FIG. 6 is a graph illustrating the accumulation rate of memory cells actually measured according to the variation of the voltage difference (Δ PV) from the pre-program-verify voltage to the program-verify voltage, in accordance with one embodiment of the present invention. Referring to FIG. 6, according to the bit line voltage (V)_BL) And step voltage (V)_ISPP) Is counted for threshold voltage Vt measurements of a plurality of memory cells, wherein, for example, V_BL0.2V and V_ISPP0.4V and the voltage difference (Δ PV) is the variation of the values. Square point is V_BL0V, which is the case without QPW operation, is taken as the reference value. When the QPW operation is applied, the threshold voltage Vt is retracted and the measured reduction of 10 can be estimated.

FIG. 7 is a graph illustrating comparison of simulation data and measurement data for a reduction in width of a threshold voltage envelope distribution according to a change in a voltage difference (Δ PV) from a pre-program verify voltage to a program verify voltage, in accordance with one embodiment of the present invention. Referring to fig. 7, the amount of width reduction of the threshold voltage envelope distribution estimated by simulation according to fig. 5 is represented by a circular dot. The reduction in width 10 of the threshold voltage envelope distribution estimated by measurement according to fig. 6 is represented by square dots. The results of the simulation and the measurement may be considered to be in agreement to one extent. Therefore, the simulation model of the invention can reasonably reflect the width reduction of the threshold voltage packet distribution.

FIG. 8 is a schematic diagram of a reduced quantity topographic map and a programmed gun count topographic map in accordance with one embodiment of the present invention. Referring to FIG. 8, a plurality of bit line voltages (V) within a range, e.g., 0.1V to 0.35V, according to the variation of FIG. 5 are shown_BL) And a plurality of voltage difference values (Δ PV) varying within a range, e.g., 0.1V to 0.4V, estimated at the bit line voltage (V)_BL) The reduction amount of the threshold voltage distribution width obtained by the voltage difference value (Δ PV) is compared with the reduction amount, and a reduction amount topographic map 100 is obtained. The reduction amount is a height of the topographic map, for example, represented in gray scale. From the reduced amount map 100, a desired region 102 and a region 104 other than the desired region can be selected according to the height of the reduced amount.

In addition, the bit line voltages (V) are similarly varied according to the bit line voltages_BL) And a plurality of voltage difference value (Δ PV) maps estimating that the applying step program pulse (ISPP) operation reaches the program Verify Voltage (VV)_PV) The number of programming guns required is counted as altitude to obtain a programming gun number map 110. The accepted region 112 and the excluded region 114 are also determined based on operational time cost considerations.

It is noted that since the model of the present invention has been confirmed to be correct, the data of FIG. 8 can be subjected to a number of simulations based on the model to facilitate estimation, which does not require actual measurements, or which requires only simple measurement confirmation.

FIG. 9 is a schematic diagram of the operating region of a Quick Pass Write (QPW) operation determined after overlap of a reduced amount topographic map and a program gun number topographic map, in accordance with one embodiment of the present invention. Referring to FIG. 9, overlapping the reduced quantity topographic map 100 of FIG. 8 with the program gun number topographic map 110, the region where region 102 overlaps region 112 may be determined by the bit line voltage (V)_BL) In the application range ofAnd an application range of the voltage difference (Δ PV). The operation region taken will be different for different types of memory cell structures, but the estimated mechanism is similar.

From the results of FIG. 9, the present invention can convert the bit line voltage (V)_BL) And the voltage difference (Δ PV) can be optimized to reduce the distribution width of the threshold voltage and maintain a reasonable operation time.

Referring to the hardware system, FIG. 10 is a block diagram of a system for determining a fast pass write operation according to an embodiment of the present invention. Referring to FIG. 10, a system for determining a fast pass write operation includes, for example, an analysis circuit 200 and an analysis program storage unit 204, wherein the analysis circuit 200 is configured to retrieve an analysis program from the analysis program storage unit 204 and operate on the memory cells of the memory cell array 202 to obtain the reduced quantity topographic map 100 and the programmed gun number topographic map 110 as described above.

Specifically, the system for determining a quick pass write operation is configured to perform a plurality of steps including estimating a reduction in the width of the threshold voltage distribution obtained at a plurality of bit line voltages varying within a first range and a plurality of voltage difference values varying within a second range, resulting in a reduction map. Estimating the programming gun number required for applying the stepping programming pulse operation to reach the programming verification voltage according to a plurality of bit line voltages and a plurality of voltage difference values to obtain a programming gun number topographic map. After the reduction amount map and the program gun number map are superimposed, an operation region constituted by an application range of the bit line voltage and an application range of the voltage difference is determined.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.