阅读说明：本技术 一种发光二极管芯片 (Light-emitting diode chip ) 是由 王绘凝 夏宏伟 马全扬 卓佳利 史伟斌 林素慧 杨人龙 张中英 于 2021-07-20 设计创作，主要内容包括：本发明涉及种发光二极管芯片,包括衬底、半导体发光序列层、第一电极和第二电极,所述第一电极电连接第一导电型半导体层；所述第一电极包括反射层、中间层和导电层,反射层用于反射来自发光层的光；所述的中间层包括阻挡层,阻挡层至少包括第一层和第二层,第一层比第二层更接近导电层,第一层和第二层均包括有Pt金属层,且第一层中Pt金属层的厚度大于第二层中Pt金属层的厚度,以解决电极结构中金属互溶的问题。(The invention relates to a light-emitting diode chip which comprises a substrate, a semiconductor light-emitting sequence layer, a first electrode and a second electrode, wherein the first electrode is electrically connected with a first conductive semiconductor layer; the first electrode includes a reflective layer for reflecting light from the light emitting layer, an intermediate layer, and a conductive layer; the middle layer comprises a blocking layer, the blocking layer at least comprises a first layer and a second layer, the first layer is closer to the conducting layer than the second layer, the first layer and the second layer both comprise Pt metal layers, and the thickness of the Pt metal layers in the first layer is larger than that of the Pt metal layers in the second layer, so that the problem of mutual solubility of metals in the electrode structure is solved.)

1. A light emitting diode chip comprises a semiconductor light emitting sequence layer, a first electrode and a second electrode, wherein the first electrode and the second electrode are arranged on the semiconductor light emitting sequence layer, the semiconductor light emitting sequence layer at least comprises a first conductive type semiconductor layer, a second conductive type semiconductor layer and a light emitting layer positioned between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and the first electrode is electrically connected with the first conductive type semiconductor layer; the method is characterized in that: the first electrode includes a reflective layer for reflecting light from the light emitting layer, an intermediate layer, and a conductive layer; the middle layer comprises a blocking layer, the blocking layer at least comprises a first layer and a second layer, the first layer is closer to the conducting layer than the second layer, the first layer and the second layer both comprise Pt metal layers, and the thickness of the Pt metal layers in the first layer is larger than that of the Pt metal layers in the second layer.

2. The light-emitting diode chip of claim 1, wherein: the barrier layer includes a plurality of pairs of repeating stacks, each of which includes a Pt metal layer and a buffer metal layer.

3. The light-emitting diode chip of claim 2, wherein: the buffer metal layer is a Ni metal layer and/or a Ti metal layer.

4. The light-emitting diode chip of claim 2, wherein: the number of pairs of the repeated stacked layers is 2-5 pairs.

5. The light-emitting diode chip of claim 2, wherein: the thickness of the Pt metal layer in each repeated lamination is 20-150nm, and the thickness of the buffer metal layer is 40-200 nm.

6. The light-emitting diode chip of claim 2, wherein: the repeating stack closest to the conductive layer is the first layer, and the thickness of the layer of Pt metal in the first layer is greater than the thickness of the layer of Pt metal in the other individual repeating stacks.

7. The light-emitting diode chip of claim 1, wherein: the reflecting layer is an aluminum reflecting layer, and the conducting layer is a gold conducting layer or a gold-tin alloy conducting layer.

8. The light-emitting diode chip of claim 1, wherein: the light-emitting diode chip is of a positive structure, the first electrode comprises a pad electrode and an extension electrode, the pad electrode is used for being connected with an external circuit through a bonding wire and is in a block shape, the extension electrode extends out from the edge of the block-shaped pad electrode and is in a strip shape, and the pad electrode and the extension electrode respectively comprise a reflecting layer, an intermediate layer and a conducting layer.

9. The light-emitting diode chip of claim 8, wherein: the width of the extension electrode is 1-20 microns.

10. The light-emitting diode chip of claim 8, wherein: the reflective layer on the pad electrode and the semiconductor light emitting sequence stack layer may further include an ohmic contact layer therebetween, and the ohmic contact layer forms an ohmic contact with the first conductive type semiconductor layer.

11. The light-emitting diode chip of claim 10, wherein: the thickness of the ohmic contact layer is less than 10 nm.

12. The light-emitting diode chip of claim 1, wherein: the light emitting diode chip is of a flip-chip structure, the semiconductor light emitting sequence layer is further provided with an insulating layer, the insulating layer covers the top surface and the side wall of the semiconductor light emitting sequence, the first electrode and the second electrode are formed on the top surface of the insulating layer and are electrically connected with the first conductive type semiconductor layer and the second conductive type semiconductor layer respectively, and the first electrode and the second electrode respectively comprise a reflecting layer, an intermediate layer and a conductive layer.

13. The light-emitting diode chip of claim 12, wherein: the first and second electrodes each include a pad electrode formed on a top surface of the insulating layer and a contact electrode electrically connected to the first or second conductivity type semiconductor layer, the insulating layer has an opening exposing at least a portion of the contact electrode, and the pad electrode fills the opening and is electrically connected to the contact electrode.

14. The light-emitting diode chip of claim 13, wherein: the contact electrode includes the reflective layer, an intermediate layer, and a conductive layer.

15. The light-emitting diode chip of claim 14, wherein: the pad electrode also includes the reflective layer, an intermediate layer, and a conductive layer.

16. The light-emitting diode chip of claim 15, wherein: the barrier layer in the pad electrode includes a plurality of pairs of repeating stacks, each of which includes a Pt metal layer and a buffer metal layer.

17. The light-emitting diode chip of claim 16, wherein: the buffer metal layer is a Ni metal layer and/or a Ti metal layer.

18. The light-emitting diode chip of claim 15, wherein: the blocking layer in the pad electrode is a single-layer Pt metal layer.

Technical Field

The invention relates to the field of semiconductor devices, in particular to a light-emitting diode chip.

Background

A Light Emitting Diode (LED) is a semiconductor device that emits light by using energy released during carrier recombination, and particularly, a flip-chip LED chip thereof has been widely used due to advantages of low energy consumption, long service life, energy saving, environmental protection, and the like.

In the prior art, in order to increase the light extraction efficiency of the light emitting diode chip and reduce the absorption of the electrode structure to light, a reflective layer is added in the electrode structure to reflect the light from the light emitting layer. In practical applications, a commonly used material of the reflective layer, for example, a metal material such as Al, has a strong metal activity, and is likely to migrate under conditions of high temperature, high humidity, applied voltage, and the like, resulting in failures such as short circuit.

Disclosure of Invention

In order to solve the above problems, the present invention provides a light emitting diode chip.

The specific scheme is as follows:

a light emitting diode chip comprises a semiconductor light emitting sequence layer, a first electrode and a second electrode, wherein the first electrode and the second electrode are arranged on the semiconductor light emitting sequence layer, the semiconductor light emitting sequence layer at least comprises a first conductive type semiconductor layer, a second conductive type semiconductor layer and a light emitting layer positioned between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and the first electrode is electrically connected with the first conductive type semiconductor layer; the method is characterized in that: the first electrode includes a reflective layer for reflecting light from the light emitting layer, an intermediate layer, and a conductive layer; the middle layer comprises a blocking layer, the blocking layer at least comprises a first layer and a second layer, the first layer is closer to the conducting layer than the second layer, the first layer and the second layer both comprise Pt metal layers, and the thickness of the Pt metal layers in the first layer is larger than that of the Pt metal layers in the second layer.

In one embodiment, the barrier layer includes a plurality of pairs of repeating stacks, each of which includes a layer of Pt metal and a layer of buffer metal.

In one embodiment, the buffer metal layer is a Ni metal layer and/or a Ti metal layer.

In one embodiment, the number of pairs of repeating stacks is 2-5 pairs.

In one embodiment, the thickness of the Pt metal layer in each repeating stack is 20-150nm, and the thickness of the buffer metal layer is 40-200 nm.

In one embodiment, the repeating stack closest to the conductive layer is the first layer, and the thickness of the Pt metal layer in the first layer is greater than the thickness of the Pt metal layer in the other single repeating stack.

In one embodiment, the reflective layer is an aluminum reflective layer, and the conductive layer is a gold conductive layer or a gold-tin alloy conductive layer.

In an embodiment, the led chip is a forward-mounted led chip, the first electrode includes a pad electrode and an extension electrode, the pad electrode is used for being connected to an external circuit through a bonding wire, the pad electrode is in a block shape, the extension electrode extends out from an edge of the block-shaped pad electrode and is in a strip shape, and the pad electrode and the extension electrode each include a reflective layer, an intermediate layer, and a conductive layer.

In one embodiment, the width of the extension electrode is generally 1-20 microns.

In an embodiment, an ohmic contact layer may be further included between the reflective layer on the pad electrode and the semiconductor light emitting sequence stack layer, and the ohmic contact layer forms an ohmic contact with the first conductive type semiconductor layer.

In one embodiment, the ohmic contact layer has a thickness of less than 10 nm.

In one embodiment, the light emitting diode chip is a flip chip light emitting diode chip, the semiconductor light emitting sequence layer further has an insulating layer thereon, the insulating layer covers the top surface and the sidewalls of the semiconductor light emitting sequence, the first and second electrodes are formed on the top surface of the insulating layer and are electrically connected to the first conductive type semiconductor layer and the second conductive type semiconductor layer, respectively, and the first and second electrodes each include a reflective layer, an intermediate layer and a conductive layer.

In one embodiment, the first and second electrodes each include a pad electrode formed on a top surface of the insulating layer and a contact electrode electrically connected to the first or second conductive type semiconductor layer, the insulating layer has an opening exposing at least a portion of the contact electrode, and the pad electrode fills the opening and electrically connects to the contact electrode.

In an embodiment, the contact electrode includes the reflective layer, an intermediate layer, and a conductive layer.

In one embodiment, the pad electrode also includes the reflective layer, an intermediate layer, and a conductive layer.

In one embodiment, the barrier layer in the pad electrode includes a plurality of pairs of repeating stacks, each of which includes a Pt metal layer and a buffer metal layer.

In one embodiment, the buffer metal layer is a Ni metal layer and/or a Ti metal layer.

In one embodiment, the barrier layer in the pad electrode is a single layer of Pt metal.

Compared with the prior art, the light-emitting diode chip provided by the invention has the following advantages: the light emitting diode chip provided by the invention has the advantages that the middle layer is inserted between the reflecting layer and the conducting layer of the electrode structure, the middle layer comprises a blocking layer which blocks the conducting layer from being mutually soluble with the reflecting layer, the blocking layer at least comprises a first layer and a second layer, the first layer is closer to the conducting layer than the second layer, the first layer and the second layer both comprise Pt metal layers, the thickness of the Pt metal layer in the first layer is larger than that of the Pt metal layer in the second layer, and the blocking layer can block the conducting layer from being mutually soluble with the reflecting layer.

Drawings

Fig. 1 shows a schematic cross-sectional structure of a light-emitting diode chip in embodiment 1.

Fig. 2 is a schematic plan view showing a light-emitting diode chip in embodiment 1.

Fig. 3 shows a schematic view of an electrode structure of a light-emitting diode chip in embodiment 1.

Fig. 4 shows a schematic view of a barrier layer of the electrode structure in example 1.

Fig. 5 shows a TEM image of the barrier layer of the electrode structure in example 1.

Fig. 6 is a schematic cross-sectional view showing a light-emitting diode chip in embodiment 2.

Fig. 7 is a schematic plan view showing a light-emitting diode chip in embodiment 2.

Fig. 8 is a schematic view showing an electrode structure of a light emitting diode chip in embodiment 2.

Fig. 9 shows a schematic view of a barrier layer of the electrode structure in example 2.

Fig. 10 shows a TEM image of the barrier layer of the electrode structure in example 2.

Detailed Description

To further illustrate the various embodiments, the invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. Those skilled in the art will appreciate still other possible embodiments and advantages of the present invention with reference to these figures. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.

The invention will now be further described with reference to the accompanying drawings and detailed description.

Example 1

The electrode of the LED chip is used as a current injection point, and material selection and structure play a crucial role in the performance of the electrode and the whole chip. The commonly used electrode materials at present comprise Cr, Al, Au and the like, and in practical application, the Al has strong metal activity, so that electromigration is easy to occur, and failure such as short circuit is caused. In order to reduce the probability of migration of active metals such as Al, the upper layer metal of the electrode is generally required to have a good coating effect on the bottom layer Al metal, however, the common metal Au and Al as the upper layer of the electrode are easily dissolved with each other, which results in a reduction in the reflectivity of Al and a reduction in the light emitting effect of the chip. Research shows that mutual solubility of Au and Al generally represents that Au migrates downward and Al dissolves together, so in order to play a role of blocking mutual solubility of Au and Al and reduce stress of Pt, the LED chip disclosed in this embodiment designs a barrier layer formed by multiple stacked layers between the reflective layer and the conductive layer, and the thickness of the uppermost barrier layer is the largest, i.e., Au migrates downward is blocked to the maximum, thereby preventing mutual solubility of Au and Al. The LED chip of the present embodiment is described below with reference to the drawings.

The present embodiment is described by taking a light emitting diode chip with a front-mounted structure as an example.

As shown in fig. 1-2, the light emitting diode chip of the front-loading structure includes a substrate 10, a semiconductor light emitting sequence layer 11 on the substrate 10, and a first electrode 12 and a second electrode 13 disposed on the semiconductor light emitting sequence layer 11.

The substrate 10 may be an insulating substrate or a conductive substrate. The substrate 10 may be a growth substrate, such as a sapphire substrate, a silicon carbide substrate, etc., for growing the semiconductor light emitting sequence 11, or the semiconductor light emitting sequence 11 may be bonded on the substrate 10 through a transparent bonding layer. The substrate 10 has a first surface, a second surface and a sidewall, wherein the first surface and the second surface are opposite, and the substrate 10 may further include a plurality of protrusions formed at least at a partial region of the first surface. For example, the substrate 10 may be a patterned sapphire substrate.

A semiconductor light emitting sequence 11 is stacked on a first surface of the substrate 10, wherein the semiconductor light emitting sequence layer 11 includes at least a first conductive type semiconductor layer 111, a second conductive type semiconductor layer 113, and a light emitting layer 112 between the first conductive type semiconductor layer and the second conductive type semiconductor layer; the light emitting layer 112 includes a Quantum Well (QW) structure, or a Multiple Quantum Well (MQW). The semiconductor light emitting sequence layer may be composed of gallium nitride material, gallium arsenide material, etc., and the element composition ratio of the semiconductor may be adjusted to emit the desired wavelength, such as providing light radiation of ultraviolet, blue, red, infrared, etc. In this embodiment, the first conductive type semiconductor layer 111 is a P-type semiconductor layer, and the second conductive type semiconductor layer 113 is an N-type semiconductor layer.

After the semiconductor light emitting sequence layer is formed on the substrate, a first electrode 12 and a second electrode 13 are formed on the semiconductor light emitting sequence layer, wherein the first electrode 12 is covered on and electrically connected to the first conductive type semiconductor layer 111, and the second electrode 13 is covered on and electrically connected to the second conductive type semiconductor layer 113. In the present embodiment, the first electrode 12 is a P electrode, and the second electrode 13 is an N electrode. The first electrode 12 includes a pad electrode 12a and an extension electrode 12b, wherein the pad electrode 12a is used for external circuit connection through a bonding wire and has a block shape, such as a circular block shape or a square block shape, the extension electrode 12b extends from the edge of the block-shaped pad electrode 12a and has a strip shape, the pad electrode 12a is optionally designed into one or more strips according to the extension efficiency, and the width of the extension electrode 12b is generally between 1-20 μm.

In addition, a partial current blocking layer (not shown) may be formed on the semiconductor light emitting sequence layer, a transparent conductive layer 14 (such as ITO) covers most of the entire surface of the first conductive type semiconductor layer 111, a portion of the pad electrode 12a (e.g., an edge portion) of the first electrode 12 and the extension electrode 12b are formed on the transparent conductive layer 14, and the transparent conductive layer 14 has a horizontal lateral spreading effect on the current.

The semiconductor light emitting sequence layer may further include a protective layer 15 thereon, wherein the protective layer 15 covers the top surface and the sidewalls of the semiconductor light emitting sequence 11, and preferably, the protective layer further covers a portion of the surfaces of the first electrode 12 and the second electrode 13 for isolating moisture. The protective layer 15 covers the top surface of the pad electrode 12a, which is required to expose at least a partial area for bonding connection with an external circuit. The protective layer 15 may be an insulating material such as silicon oxide or silicon nitride.

Referring to fig. 3, the first electrode 12 (the pad electrode 12a and the extension electrode 12b) includes a reflective layer 121, a barrier layer 122, and a conductive layer 123, the reflective layer 121 being disposed adjacent to the first conductive type semiconductor layer 111 and having a reflective power for light emitted from the light emitting layer 112, the conductive layer 123 being located on the surface side of the first electrode 12, and the barrier layer 122 being located between the reflective layer 121 and the conductive layer 123.

An ohmic contact layer 124 may be further included between the reflective layer 121 on the pad electrode 12a and the semiconductor light emitting sequence stacked layer, and the ohmic contact layer 124 may form an ohmic contact with the first conductive type semiconductor layer 111. The ohmic contact layer 124 is thin, preferably less than 10nm, such as 1-8nm, and the ohmic contact layer 124 minimizes the effect on the reflectivity of the reflective layer 121. Preferably, the ohmic contact layer is Ni or Cr. Optionally, an ohmic contact layer 124 is also included between the reflective layer 121 on the extended electrode 12b and the stacked layers of the semiconductor light emitting sequence 11.

Referring to fig. 3, a barrier layer 122 is interposed between the conductive layer 123 and the reflective layer 121 for blocking the conductive layer 123 from contacting and dissolving with the reflective layer 121; the barrier layer 122 includes at least a first layer 1221 and a second layer 1222, the first layer 1221 being closer to the conductive layer 123 than the second layer 1222, and the first layer 1221 being thicker than the second layer 1222.

Preferably, the barrier layer 122 is a multi-pair repeated lamination composed of a Ti metal layer and a Pt metal layer, the number of pairs is preferably 2-5 pairs, the thickness of the single Pt metal layer is 20-150nm, and the thickness of the single titanium metal layer is 40-200 nm.

Preferably, the reflective layer 121 is an aluminum reflective layer, the conductive layer 123 is a gold conductive layer, and referring to fig. 4, the barrier layer in fig. 4 is a repeated stack of 3 pairs of Ti/Pt metal layers, wherein a Pt metal layer is formed on a buffer metal layer (Ti metal layer or Ni metal layer), and a structure of Ti/Pt/Ti/Pt is formed, that is, each layer of the barrier layer is a stack of Ti/Pt metal layers, the uppermost Ti/Pt metal layer is a first layer 1221, the middle Ti/Pt metal layer is a second layer 1222, and the lowermost Ti/Pt metal layer is a third layer 1223, wherein Pt is mainly used for blocking mutual dissolution of Au and Al, so a certain thickness is required. Research shows that due to the fact that the stress ratio of Pt is large, if a metal layer is plated too thick at one time and is easy to split, or curling occurs during plating, a Ti layer is needed to be inserted as a buffer layer to reduce the stress, so that the Pt metal layer can have better quality, and the purpose of better blocking Au and Al from being mutually soluble is achieved. Meanwhile, research finds that mutual solubility of Au and Al is represented by downward migration of Au, so that the layer of Pt metal layer close to Au is thickest, namely the thickness of the Pt metal layer of the first layer is thicker than that of the Pt metal layers of the second layer and the third layer, and the Pt metal layer of the first layer and the third layer have better blocking effect on Au. Referring to fig. 5, fig. 5 shows TEM images of the barrier layer, the thicknesses of the layers can refer to the values marked in fig. 5, and it can be seen from the figures that the thickness of the first Pt metal layer is about 70nm, the thicknesses of the second and third Pt metal layers are both about 50nm, and the thickness of the first Pt metal layer is the largest.

In this embodiment, the barrier layer may also be a plurality of pairs of repeated stacked layers composed of Ni metal layers and Pt metal layers, the number of pairs is preferably 2-5 pairs, the thickness of the single Pt metal layer is 50-150nm, and the thickness of the single titanium metal layer is 40-200 nm. For example, in one embodiment, the barrier layer is a repeating stack of 2 pairs of Ni/Pt metal layers, forming a Ni/Pt/structure, with the upper Ni/Pt metal layer as the first layer and the lower Ti/Pt metal layer as the second layer, with the Pt metal layer in the first layer having a thickness of about 120nm and the Pt metal layer in the second layer having a thickness of about 95 nm.

In this embodiment, the barrier layer may also be a plurality of pairs of repeated stacked layers composed of Ti/Pt metal layers and Ni/Pt metal layers. For example, in one aspect, referring to FIG. 6, the barrier layer is a repeating stack of Ti/Pt/Ni/Pt/Ti/Pt metal layers, with the uppermost Ti/Pt metal layer as the first layer, the middle Ni/Pt metal layer as the second layer, and the lowermost Ti/Pt metal layer as the third layer. The thickness of the Pt metal layer in the first layer was about 120nm, and the thickness of the Pt metal layer in the second and third layers was about 95 nm.

Example 2

The present embodiment is described by taking a light emitting diode chip with a flip-chip structure as an example.

As shown in fig. 6 to 7, the light emitting diode chip of the flip-chip structure includes a substrate 20, a semiconductor light emitting sequence layer 21 on the substrate 20, and a first electrode 22 and a second electrode 23 disposed on the semiconductor light emitting sequence layer 21.

The substrate 20 may be an insulating substrate or a conductive substrate. The substrate 20 may be a growth substrate for growing the semiconductor light-emitting sequence 21, and sapphire (Al) may be selected as the substrate₂O₃) One of SiC, GaAs, GaN, ZnO, GaP, InP and Ge, but not limited to the examples listed herein, a transparent bonding layer of a semiconductor light emitting sequence 21 may be bonded on a light transmissive substrate 20. The substrate 20 has a first surface, a second surface and a sidewall, wherein the first surface and the second surface are opposite, the substrate 20 may further include a first electrode formed at least on the first surfaceA plurality of protrusions of at least a portion of the area of the surface. For example, the substrate 20 may be a patterned sapphire substrate.

A semiconductor light emitting sequence 21 stacked on the first surface of the substrate 20, wherein the semiconductor light emitting sequence layer 21 includes at least a first conductive type semiconductor layer 211, a second conductive type semiconductor layer 213, and a light emitting layer 212 between the first conductive type semiconductor layer and the second conductive type semiconductor layer; the light emitting layer 212 includes a Quantum Well (QW) structure, or a Multiple Quantum Well (MQW). The semiconductor light emitting sequence layer may be composed of gallium nitride material, gallium arsenide material, etc., and the element composition ratio of the semiconductor may be adjusted to emit the desired wavelength, such as providing light radiation of ultraviolet, blue, red, infrared, etc. In this embodiment, the first conductive type semiconductor layer 211 is a P-type semiconductor layer, and the second conductive type semiconductor layer 213 is an N-type semiconductor layer.

After the semiconductor light emitting sequence layer is formed on the substrate, the semiconductor light emitting sequence layer further has an insulating layer 25 thereon, the insulating layer 25 covers the top surface and the sidewall of the semiconductor light emitting sequence 21, and the insulating layer 25 may be an insulating material such as silicon oxide, silicon nitride, etc.

The first electrode 22 includes a first pad electrode 22a and a first contact electrode 22b, the first pad electrode 22a is formed on the top surface of the insulating layer 25, the first contact electrode 22b is in contact with the first conductive type semiconductor layer 211 to form an electrical connection, the insulating layer 25 has a first opening exposing at least a portion of the first contact electrode 22b, and the first pad electrode 22a fills the first opening and is in contact with the first contact electrode 22b to form an electrical connection.

The second electrode 23 includes a second pad electrode 23a and a second contact electrode 23b, the second pad electrode 23a is formed on the top surface of the insulating layer 25, the second contact electrode 23b is in contact with the second conductive type semiconductor layer 213 to form an electrical connection, the insulating layer 25 has a second opening exposing at least a portion of the second contact electrode 23b, and the second pad electrode 23a fills the second opening and is in contact with the second contact electrode 23b to form an electrical connection. In the present embodiment, the first electrode 22 is a P electrode, and the second electrode 23 is an N electrode.

In addition, a local current blocking layer (formed between the transparent conductive layer and the semiconductor light emitting sequence layer, not shown in the figure) and a transparent conductive layer 24 (such as one or a combination of ITO, GTO, GZO, and ZnO) may be formed on the semiconductor light emitting sequence layer to cover most of the entire surface of the first conductive type semiconductor layer 211 (at least 90% of the coverage area), and form an ohmic contact with the first conductive type semiconductor layer 211, and the transparent conductive layer 24 simultaneously realizes a lateral transmission of current in a horizontal direction and allows at least part of the radiation of the light emitting layer to transmit.

The first pad electrode 22a of the first electrode 22 and the second pad electrode 23a of the second electrode 23 each include a reflective layer, a barrier layer, and a conductive layer.

Referring to fig. 8, taking the first electrode 22 as an example, a reflective layer is disposed adjacent to the first conductive type semiconductor layer 211, which has a reflective power for light emitted from the light emitting layer 212, a conductive layer 223 is disposed on the surface side of the first electrode 22, and a barrier layer 222 is disposed between the reflective layer 221 and the conductive layer 223.

Referring to fig. 8, the barrier layer 222 is interposed between the conductive layer 223 and the reflective layer 221 for blocking the contact mutual solubility of the conductive layer 223 and the reflective layer 221; the barrier layer 222 includes at least a first layer 2221 and a second layer 2222, the first layer 2221 being closer to the conductive layer 223 than the second layer 2222, and the first layer 2221 being thicker than the second layer 2222.

Preferably, the barrier layer 222 is a multi-pair repeated lamination composed of a Ti metal layer and a Pt metal layer, the number of pairs is preferably 2-5 pairs, the thickness of the single Pt metal layer is 20-100nm, and the thickness of the single titanium metal layer is 40-200 nm.

Preferably, the reflective layer 221 is an aluminum reflective layer, the conductive layer 223 is a gold conductive layer or a gold-tin alloy, referring to fig. 9, the barrier layer in fig. 9 is a repeated stack of 3 pairs of Ti/Pt metal layers to form a Ti/Pt/Ti/Pt structure, i.e. each layer of the barrier layer is a stack of Ti/Pt metal layers, the uppermost Ti/Pt metal layer is a first layer 2221, the middle Ti/Pt metal layer is a second layer 2222, and the lowermost Ti/Pt metal layer is a third layer 2223, wherein the main purpose of Pt is to block the mutual solubility of Au and Al, so a certain thickness is required. It was found that since Pt itself has a relatively large stress, if the metal layer is plated too thick at one time, it is easily cleaved, or curling occurs at the time of plating, so that insertion of a Ti layer is required to reduce the stress. Meanwhile, research finds that mutual solubility of Au and Al is represented by downward migration of Au, so that the layer of Pt metal layer close to Au is thickest, namely the thickness of the Pt metal layer of the first layer is thicker than that of the Pt metal layers of the second layer and the third layer, and the Pt metal layer of the first layer and the third layer have better blocking effect on Au. Referring to fig. 10, fig. 10 shows TEM images of the barrier layer, and the thicknesses of the respective layers can refer to the values marked in fig. 10, and it can be seen that the thickness of the first Pt metal layer is 609 angstroms, the thickness of the second Pt metal layer is 450 angstroms, the thickness of the third Pt metal layer is 372 angstroms, and the thickness of the first Pt metal layer is the largest.

In this embodiment, the contact electrodes of the first and second electrodes may also have substantially the same structure as the pad electrode, that is, the pad electrode also includes a reflective layer, an intermediate layer and a conductive layer, the intermediate layer has a barrier layer, and the barrier layer may be a plurality of repeated stacked layers of Ti/Pt metal layers and/or Ni/Pt metal layers.

For example, in one embodiment, the barrier layer is a repeating stack of Ti/Pt/Ni/Pt metal layers, with the upper Ti/Pt metal layer as the first layer and the lower Ni/Pt metal layer as the second layer. The thickness of the Pt metal layer in the first layer was about 150nm and the thickness of the Pt metal layer in the second layer was about 120 nm.

In this embodiment, the barrier layer of the contact electrode of the first and second electrodes may also be a separate Pt metal layer. For example, in one embodiment, the barrier layer is a single upper layer of a Pt metal layer, the thickness of the Pt metal layer is about 90nm, a Ni metal layer is interposed between the Pt metal layer and the reflective layer as a buffer layer, and a Ti metal layer is interposed between the Pt metal layer and the conductive layer as a buffer layer.

The reflecting layer in this embodiment may be a plurality of pairs of repeated stacked layers composed of Al metal and Ti metal layers. Preferably, the thickness of the metal stack in the reflective layer decreases in sequence from the light emitting side of the light emitting diode chip to the electrode side. For example, in one scheme, the reflecting layer is a repeated lamination consisting of 3 pairs of Al/Ti metal layers to form an Al/Ti/Al/Ti/Al/Ti structure, the thickness of the Al metal layer in the third metal lamination layer closest to the light emergent side is about 490nm, and the thickness of the Ti metal layer is about 190 nm; the thickness of the Al metal layer in the middle second metal stack is about 410nm and the thickness of the Ti metal layer is about 185 nm; the thickness of the Al metal layer in the first metal stack closest to the electrode side is about 405nm and the thickness of the Ti metal layer is about 175 nm.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.