阅读说明：本技术 半导体发光元件及半导体发光元件的制造方法 (Semiconductor light emitting element and method for manufacturing semiconductor light emitting element ) 是由 丹羽纪隆 稻津哲彦 于 2021-04-22 设计创作，主要内容包括：本发明提供一种抑制因半导体发光元件的通电使用而导致的光输出的降低的半导体发光元件及半导体发光元件的制造方法。半导体发光元件(10)包括：n型半导体层(24)；设于n型半导体层(24)的第1上表面(24a)的活性层(26)；设于活性层(26)上的p型半导体层(28)；与p型半导体层(28)的上表面(28a)接触设置的p侧接触电极(30)；在p侧接触电极(30)上设于比p侧接触电极(30)的形成区域窄的区域内的p侧电流扩散层(32)；设于p侧电流扩散层(32)上的p侧焊盘电极(44)；与n型半导体层(24)的第2上表面(24b)接触设置的n侧接触电极(34)；在n侧接触电极(34)上遍及比n侧接触电极(34)的形成区域大的区域而设置、包含TiN层的n侧电流扩散层(36)；以及设于n侧电流扩散层(36)上的n侧焊盘电极(46)。(The invention provides a semiconductor light emitting element and a method for manufacturing the same, which can prevent the reduction of light output caused by the use of the semiconductor light emitting element. A semiconductor light-emitting element (10) comprises: an n-type semiconductor layer (24); an active layer (26) provided on the 1 st upper surface (24a) of the n-type semiconductor layer (24); a p-type semiconductor layer (28) provided on the active layer (26); a p-side contact electrode (30) provided in contact with the upper surface (28a) of the p-type semiconductor layer (28); a p-side current diffusion layer (32) provided on the p-side contact electrode (30) in a region narrower than a region where the p-side contact electrode (30) is formed; a p-side pad electrode (44) provided on the p-side current diffusion layer (32); an n-side contact electrode (34) provided in contact with the 2 nd upper surface (24b) of the n-type semiconductor layer (24); an n-side current diffusion layer (36) which is provided on the n-side contact electrode (34) over a region larger than the region in which the n-side contact electrode (34) is formed and which includes a TiN layer; and an n-side pad electrode (46) provided on the n-side current diffusion layer (36).)

1. A semiconductor light emitting element, comprising:

an n-type semiconductor layer made of an n-type AlGaN semiconductor material,

an active layer made of an AlGaN semiconductor material and provided on the 1 st upper surface of the n-type semiconductor layer,

a p-type semiconductor layer disposed on the active layer,

a p-side contact electrode disposed in contact with an upper surface of the p-type semiconductor layer,

a p-side current diffusion layer provided on the p-side contact electrode in a region narrower than a region where the p-side contact electrode is formed,

a p-side pad electrode provided on the p-side current diffusion layer,

an n-side contact electrode disposed in contact with the 2 nd upper surface of the n-type semiconductor layer,

an n-side current diffusion layer including a TiN layer and provided on the n-side contact electrode over a region larger than a formation region of the n-side contact electrode, and

an n-side pad electrode provided on the n-side current diffusion layer.

2. The semiconductor light emitting element according to claim 1,

the p-side current diffusion layer and the n-side current diffusion layer each have a laminated structure in which a TiN layer, a metal layer, and a TiN layer are laminated in this order.

3. The semiconductor light emitting element according to claim 1 or 2,

the n-side current diffusion layer comprises a 1 st current diffusion layer arranged on the n-side contact electrode and a 2 nd current diffusion layer arranged on the 1 st current diffusion layer;

the 1 st current diffusion layer and the 2 nd current diffusion layer each have a laminated structure in which a TiN layer, a metal layer, and a TiN layer are laminated in this order.

4. The semiconductor light emitting element according to claim 3,

the 1 st current diffusion layer is provided over a region larger than a formation region of the n-side contact electrode.

5. The semiconductor light emitting element according to claim 3 or 4,

the 2 nd current diffusion layer is provided over a region larger than a formation region of the 1 st current diffusion layer.

6. The semiconductor light emitting element according to any one of claims 2 to 5,

the thickness of the metal layer of the stacked configuration is greater than the thickness of the TiN layer of the stacked configuration.

7. A method for manufacturing a semiconductor light emitting element, comprising:

a step of forming an active layer made of an AlGaN semiconductor material on an n-type semiconductor layer made of an n-type AlGaN semiconductor material,

a step of forming a p-type semiconductor layer on the active layer,

a step of partially removing the p-type semiconductor layer and the active layer to expose an upper surface of a partial region of the n-type semiconductor layer,

a step of forming a p-side contact electrode in contact with the upper surface of the p-type semiconductor layer,

a step of forming a p-side current diffusion layer on the p-side contact electrode in a region narrower than a region where the p-side contact electrode is formed,

a step of forming an n-side contact electrode in contact with the exposed upper surface of the n-type semiconductor layer,

a step of forming an n-side current diffusion layer including a TiN layer on the n-side contact electrode over a region larger than a formation region of the n-side contact electrode,

a step of forming a p-side pad electrode on the p-side current diffusion layer, and

and forming an n-side pad electrode on the n-side current diffusion layer.

8. The method for manufacturing a semiconductor light emitting element according to claim 7,

further comprising a step of annealing the n-side contact electrode;

the n-side current diffusion layer is formed after annealing of the n-side contact electrode.

Technical Field

The present invention relates to a semiconductor light emitting element and a method for manufacturing the semiconductor light emitting element.

Background

The semiconductor light emitting element includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on a substrate, wherein an n-side electrode is provided on the n-type semiconductor layer, and a p-side electrode is provided on the p-type semiconductor layer. In a light-emitting element using a nitride semiconductor such as GaN or AlGaN, an n-side electrode composed of a laminate of Ti and Al may be used (see, for example, patent document 1).

[ Prior art documents ]

[ patent document ]

Patent document 1: japanese patent laid-open publication No. 2019-192908

Disclosure of Invention

[ problems to be solved by the invention ]

By adopting a structure in which Au is not used for the n-side electrode, the ultraviolet reflectance of the n-side electrode can be improved. However, when the n-side electrode is formed using Al, since Au for protecting the electrode is not contained in the n-side electrode, corrosion of Al progresses with the use of energization, resulting in a decrease in ultraviolet reflectance.

The present disclosure has been made in view of the above problems, and an object thereof is to provide a technique for suppressing a decrease in light output due to the use of a semiconductor light emitting element by energization.

[ means for solving the problems ]

A semiconductor light emitting element according to an aspect of the present invention includes: an n-type semiconductor layer made of an n-type AlGaN semiconductor material; an active layer provided on the 1 st upper surface of the n-type semiconductor layer and made of an AlGaN semiconductor material; a p-type semiconductor layer provided on the active layer; a p-side contact electrode provided in contact with an upper surface of the p-type semiconductor layer; a p-side current diffusion layer provided on the p-side contact electrode in a region narrower than a region where the p-side contact electrode is formed; a p-side pad electrode provided on the p-side current diffusion layer; an n-side contact electrode disposed in contact with the 2 nd upper surface of the n-type semiconductor layer; an n-side current diffusion layer which is provided on the n-side contact electrode over a region larger than a formation region of the n-side contact electrode and includes a TiN layer; and an n-side pad electrode provided on the n-side current diffusion layer.

According to this aspect, by providing the p-side current diffusion layer in the region narrower than the p-side contact electrode on the p-side contact electrode, the area occupied by the p-side contact electrode on the upper surface of the p-type semiconductor layer can be maximized, and the light-emitting area contributing to light emission in the light-emitting layer can be maximized. Further, by providing the n-side current diffusion layer including the TiN layer on the n-side contact electrode over a region larger than the region in which the n-side contact electrode is formed, corrosion of the n-side contact electrode due to use for energization can be suppressed. This suppresses a decrease in the reflectance of the n-side contact electrode functioning as the reflective electrode, and can suppress a decrease in the light output due to the use of electricity.

The p-side current diffusion layer and the n-side current diffusion layer may have a multilayer structure in which a TiN layer, a metal layer, and a TiN layer are sequentially stacked.

The n-side current diffusion layer may include a 1 st current diffusion layer provided on the n-side contact electrode and a 2 nd current diffusion layer provided on the 1 st current diffusion layer. The 1 st current diffusion layer and the 2 nd current diffusion layer may have a multilayer structure in which a TiN layer, a metal layer, and a TiN layer are sequentially stacked.

The 1 st current diffusion layer may be provided over a region larger than a region where the n-side contact electrode is formed.

The 2 nd current diffusion layer may be provided over a region larger than the formation region of the 1 st current diffusion layer.

The thickness of the metal layer of the stacked structure may be larger than the thickness of the TiN layer of the stacked structure.

Another embodiment of the present invention is a method for manufacturing a semiconductor light-emitting element. The method comprises the following steps: forming an active layer made of an AlGaN semiconductor material on an n-type semiconductor layer made of an n-type AlGaN semiconductor material; forming a p-type semiconductor layer on the active layer; partially removing the p-type semiconductor layer and the active layer to expose an upper surface of a partial region of the n-type semiconductor layer; forming a p-side contact electrode in contact with an upper surface of the p-type semiconductor layer; forming a p-side current diffusion layer on the p-side contact electrode in a region narrower than a region where the p-side contact electrode is formed; forming an n-side contact electrode in contact with the exposed upper surface of the n-type semiconductor layer; forming an n-side current diffusion layer including a TiN layer over a region larger than a region where the n-side contact electrode is formed, on the n-side contact electrode; forming a p-side pad electrode on the p-side current diffusion layer; and a step of forming an n-side pad electrode on the n-side current diffusion layer.

According to this aspect, by providing the p-side current diffusion layer in the region narrower than the p-side contact electrode on the p-side contact electrode, the area occupied by the p-side contact electrode on the upper surface of the p-type semiconductor layer can be maximized, and the light-emitting area contributing to light emission in the light-emitting layer can be maximized. Further, by providing an n-side current diffusion layer including a TiN layer over a region larger than the region where the n-side contact electrode is formed on the n-side contact electrode, corrosion of the n-side contact electrode due to use for energization can be suppressed. This suppresses a decrease in the reflectance of the n-side contact electrode functioning as the reflective electrode, and can suppress a decrease in the light output due to the use of electricity.

The method may further include annealing the n-side contact electrode. The n-side current diffusion layer may be formed after annealing the n-side contact electrode.

[ Effect of the invention ]

According to the present invention, a decrease in light output due to the use of the semiconductor light emitting element by energization can be suppressed.

Drawings

Fig. 1 is a cross-sectional view schematically showing the structure of a semiconductor light emitting element according to embodiment 1.

Fig. 2 is a view schematically showing a manufacturing process of the semiconductor light emitting element.

Fig. 3 is a view schematically showing a manufacturing process of the semiconductor light emitting element.

Fig. 4 is a view schematically showing a manufacturing process of the semiconductor light emitting element.

Fig. 5 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 6 is a view schematically showing a manufacturing process of the semiconductor light emitting element.

Fig. 7 schematically shows a process for manufacturing a semiconductor light-emitting element.

Fig. 8 is a view schematically showing a manufacturing process of the semiconductor light emitting element.

Fig. 9 is a view schematically showing a manufacturing process of the semiconductor light emitting element.

Fig. 10 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 11 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 12 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 13 is a view schematically showing a manufacturing process of the semiconductor light emitting element.

Fig. 14 is a cross-sectional view schematically showing the structure of the semiconductor light emitting element according to embodiment 2.

Fig. 15 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 16 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 17 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 18 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 19 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 20 schematically shows a manufacturing process of the semiconductor light emitting element.

Fig. 21 is a view schematically showing a manufacturing process of a semiconductor light emitting element.

Detailed Description

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the description, the same elements are denoted by the same reference numerals, and overlapping description is omitted as appropriate. In addition, in order to facilitate understanding of the description, the size ratio of each component in each drawing does not necessarily match the actual size ratio of the light emitting element.

The semiconductor Light Emitting element of the present embodiment is a so-called DUV-LED (Deep UltraViolet Light Emitting Diode) chip configured to emit "Deep UltraViolet Light" having a central wavelength λ of about 360nm or less. In order to output deep ultraviolet light having such a wavelength, an aluminum gallium nitride (AlGaN) semiconductor material having a band gap of about 3.4eV or more is used. In the present embodiment, the case where deep ultraviolet light having a center wavelength λ of about 240nm to 320nm is emitted is particularly shown.

In the present specification, the "AlGaN-based semiconductor material" refers to a semiconductor material containing at least aluminum nitride (AlN) and gallium nitride (GaN), and includes a semiconductor material containing another material such as indium nitride (InN). Therefore, the "AlGaN-based semiconductor material" referred to In the present specification may be, for example, In_1-x-yAl_xGa_yN(0<x+y≦1、0<x<1、0<y<1) The composition of (1) includes AlGaN or InAlGaN. The "AlGaN-based semiconductor material" in the present invention is, for example, AlN and GaN, each having a molar fraction of 1% or more, preferably 5% or more, 10% or more, or 20% or more.

In addition, in order to distinguish a material containing no AlN, it is sometimes referred to as a "GaN-based semiconductor material". The "GaN-based semiconductor material" includes GaN and InGaN. Similarly, in order to distinguish a material containing no GaN, it is sometimes referred to as "AlN-based semiconductor material". The "AlN semiconductor material" includes AlN and InAlN.

(embodiment 1)

Fig. 1 is a cross-sectional view schematically showing the structure of a semiconductor light-emitting element 10 according to embodiment 1. The semiconductor light emitting element 10 includes: substrate 20, foundation layer 22, n-type semiconductor layer 24, active layer 26, p-type semiconductor layer 28, p-side contact electrode 30, p-side current diffusion layer 32, n-side contact electrode 34, n-side current diffusion layer 36, 1 st protective layer 38, 2 nd protective layer 40, 3 rd protective layer 42, p-side pad electrode 44, and n-side pad electrode 46.

In fig. 1, the direction indicated by the arrow a is sometimes referred to as the "up-down direction" or the "thickness direction". In addition, a direction away from the substrate 20 is sometimes referred to as an upper side and a direction toward the substrate 20 is sometimes referred to as a lower side when viewed from the substrate 20.

The substrate 20 has a 1 st main surface 20a and a 2 nd main surface 20b opposite to the 1 st main surface 20 a. The 1 st main surface 20a is a crystal growth plane for growing each layer from the base layer 22 to the p-type semiconductor layer 28. The substrate 20 is made of a material transparent to deep ultraviolet light emitted from the semiconductor light-emitting element 10, and is made of, for example, sapphire (Al)₂O₃) And (4) forming. A fine uneven pattern having a depth and pitch of submicron (1 μm or less) is formed on the 1 st main surface 20 a. Such a Substrate 20 is also referred to as a Patterned Sapphire Substrate (PSS). The 2 nd main surface 20b is a light extraction surface for extracting the deep ultraviolet light emitted from the active layer 26 to the outside. The substrate 20 may be composed of AlN or AlGaN. The substrate 20 may also be a conventional substrate having a 1 st major surface 20a formed of an unpatterned planar surface.

The base layer 22 is provided on the 1 st major surface 20a of the substrate 20. The base layer 22 is a base layer (template layer) for forming the n-type semiconductor layer 24. The underlayer 22 is made of undoped AlN, specifically High Temperature grown AlN (HT-AlN). The base layer 22 may also include an AlN layer and an undoped AlGaN layer formed on the AlN layer. When the substrate 20 is an AlN substrate or an AlGaN substrate, the underlayer 22 may be formed only of an undoped AlGaN layer. The base layer 22 includes at least one of an undoped AlN layer and an AlGaN layer.

The n-type semiconductor layer 24 is provided on the base layer 22. The n-type semiconductor layer 24 is made of an n-type AlGaN semiconductor material. For example, Si is doped as an n-type impurity. The n-type semiconductor layer 24 has a composition ratio selected so as to transmit deep ultraviolet light emitted from the active layer 26, and is formed such that, for example, the molar fraction of AlN is 25% or more, preferably 40% or more, or 50% or more. The n-type semiconductor layer 24 has a band gap larger than the wavelength of deep ultraviolet light emitted from the active layer 26, and is configured to have a band gap of 4.3eV or more, for example. The n-type semiconductor layer 24 is preferably formed such that the molar fraction of AlN is 80% or less, that is, the band gap is 5.5eV or less, and more preferably such that the molar fraction of AlN is 70% or less (that is, the band gap is 5.2eV or less). The n-type semiconductor layer 24 has a thickness of about 1 μm to 3 μm, for example, about 2 μm.

The n-type semiconductor layer 24 is formed so that the concentration of Si as an impurity is 1 × 10¹⁸/cm³Above and 5 × 10¹⁹/cm³The following. The n-type semiconductor layer 24 is preferably formed so that the concentration of Si is 5 × 10¹⁸/cm³Above and 3 × 10¹⁹/cm³Hereinafter, it is more preferably configured to be 7 × 10¹⁸/cm³Above and 2X 10¹⁹/cm³The following. In one embodiment, the n-type semiconductor layer 24 has a Si concentration of 1 × 10¹⁹/cm³Front and rear, specifically 8X 10¹⁸/cm³Above and 1.5X 10¹⁹/cm³The following ranges.

The n-type semiconductor layer 24 has a 1 st upper surface 24a and a 2 nd upper surface 24 b. The 1 st upper surface 24a is a portion where the active layer 26 is formed. The 2 nd upper surface 24b is a portion where the n-side contact electrode 34 is formed without forming the active layer 26. The 1 st upper surface 24a and the 2 nd upper surface 24b are different in height from each other, and the height from the substrate 20 to the 1 st upper surface 24a is larger than the height from the substrate 20 to the 2 nd upper surface 24 b. Here, the region in which the 1 st upper surface 24a is located is defined as "1 st region W1", and the region in which the 2 nd upper surface 24b is located is defined as "2 nd region W2".

The active layer 26 is provided on the 1 st upper surface 24a of the n-type semiconductor layer 24. The active layer 26 is made of an AlGaN semiconductor material, and is sandwiched between the n-type semiconductor layer 24 and the p-type semiconductor layer 28 to form a double heterojunction structure. In order to output deep ultraviolet light having a wavelength of 355nm or less, the active layer 26 is configured to have a band gap of 3.4eV or more, and the AlN composition ratio is selected so that deep ultraviolet light having a wavelength of 320nm or less can be output, for example.

The active layer 26 has, for example, a single-layer or multi-layer quantum well structure, and is composed of a stacked body of a barrier layer made of an undoped AlGaN semiconductor material and a well layer made of an undoped AlGaN semiconductor material. The active layer 26 includes, for example, a 1 st barrier layer directly contacting the n-type semiconductor layer 24 and a 1 st well layer provided on the 1 st barrier layer. One or more pairs of well layers and barrier layers may be additionally provided between the 1 st barrier layer and the 1 st well layer. The barrier layer and the well layer each have a thickness of about 1nm to 20nm, for example, about 2nm to 10 nm.

The active layer 26 may also further include an electron blocking layer in direct contact with the p-type semiconductor layer 28. The electron blocking layer is made of an undoped AlGaN semiconductor material, and is constituted such that, for example, the molar fraction of AlN is 40% or more, preferably 50% or more. The electron blocking layer may be composed of AlN having a molar fraction of 80% or more, or may be composed of an AlN semiconductor material containing no GaN. The electron blocking layer has a thickness of the order of 1nm to 10nm, for example, 2nm to 5 nm.

The p-type semiconductor layer 28 is provided on the active layer 26. The p-type semiconductor layer 28 is made of a p-type AlGaN semiconductor material or a p-type GaN semiconductor material, and is made of, for example, AlGaN or GaN doped with magnesium (Mg) as a p-type impurity. The p-type semiconductor layer 28 has a thickness of about 300nm to 1400nm, for example. For example, the height t from the 2 nd upper surface 24b of the n-type semiconductor layer 24 to the upper surface 28a of the p-type semiconductor layer 28 may be set₀Is 400nm or more and 1500nm or less.

The p-type semiconductor layer 28 may be formed of a plurality of layers. The p-type semiconductor layer 28 may have a p-type cladding layer and a p-type contact layer, for example. The p-type cladding layer is a p-type AlGaN layer having a higher AlN ratio than the p-type contact layer, and is provided so as to be in direct contact with the active layer 26. The p-type contact layer is a p-type AlGaN layer or a p-type GaN layer having a lower AlN ratio than the p-type cladding layer. The p-type contact layer is provided on the p-type cladding layer, and is provided so as to be in direct contact with the p-side contact electrode 30.

The p-type clad layer has a composition ratio selected so as to transmit deep ultraviolet light emitted from the active layer 26. The p-type cladding layer is constituted, for example, such that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The AlN ratio of the p-type cladding layer is, for example, about the same as the AlN ratio of the n-type semiconductor layer 24 or greater than the AlN ratio of the n-type semiconductor layer 24. The AlN ratio of the p-type cladding layer may be 70% or more or 80% or more. The p-type cladding layer has a thickness of about 10nm to 100nm, for example, about 15nm to 70 nm.

In order to obtain a good ohmic contact with the p-side contact electrode 30, the p-type contact layer is configured to have an AlN ratio of 20% or less, preferably 10% or less, 5% or less, or 0%. That is, the p-type contact layer may be made of a p-type GaN semiconductor material containing no AlN. The p-type contact layer has a thickness of the order of 300nm to 1500nm, for example 500nm to 1000 nm.

The p-side contact electrode 30 is provided on the p-type semiconductor layer 28 and contacts the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 is made of a material capable of ohmic contact with the p-type semiconductor layer 28, and is made of, for example, tin oxide (SnO)₂) And Transparent Conductive Oxides (TCO) such as zinc oxide (ZnO) and Indium Tin Oxide (ITO). The thickness of the p-side contact electrode 30 is about 20nm to 500nm, preferably 50nm or more, and more preferably 100nm or more.

The p-side contact electrode 30 is provided so as to close the 1 st p-side contact opening 38p of the 1 st protective layer 38 and the 2 nd p-side contact opening 40p of the 2 nd protective layer 40. The p-side contact electrode 30 is provided so as to overlap the 1 st protective layer 38 and the 2 nd protective layer 40. Therefore, the 4 th region W4 in which the p-side contact electrode 30 is formed is larger than the opening regions of the 1 st p-side contact opening 38p and the 2 nd p-side contact opening 40p, respectively. In a plan view of the semiconductor light-emitting element 10 viewed in the thickness direction, the inside of the 4 th region W4 includes the entire opening region of each of the 1 st p-side contact opening 38p and the 2 nd p-side contact opening 40 p. In addition, the 4 th region W4 where the p-side contact electrode 30 is formed is narrower than the 3 rd region W3 where the upper surface 28a of the p-type semiconductor layer 28 is located. In a plan view when the semiconductor light-emitting element 10 is viewed in the thickness direction, the inside of the 3 rd region W3 includes the entire 4 th region W4. The area of the 4 th region W4 where the p-side contact electrode 30 is formed is, for example, 80% or more or 90% or more of the 3 rd region W3 where the upper surface 28a of the p-type semiconductor layer 28 is located.

The p-side current diffusion layer 32 is provided on the p-side contact electrode 30. The 5 th region where the p-side current diffusion layer 32 is formed is narrower than the 4 th region where the p-side contact electrode 30 is located. In a plan view when the semiconductor light-emitting element 10 is viewed in the thickness direction, the inside of the 4 th region W4 includes the entire 5 th region W5. The area of the 5 th region W5 where the p-side current diffusion layer 32 is formed is, for example, 80% or more or 90% or more of the 4 th region W4 where the p-side contact electrode 30 is located. In order to diffuse the current injected from the p-side pad electrode 44 in the lateral direction (horizontal direction), the p-side current diffusion layer 32 preferably has a certain thickness. The thickness of the p-side current diffusion layer 32 is 300nm or more and 1500nm or less, for example, about 500nm to 1000 nm.

The p-side current diffusion layer 32 has a laminated structure in which a 1 st TiN layer 32a, a metal layer 32b, and a 2 nd TiN layer 32c are laminated in this order. The 1 st TiN layer 32a and the 2 nd TiN layer 32c are made of conductive titanium nitride (TiN). The conductivity of TiN was 1X 10^-5Omega. m or less, e.g. 4X 10^-7Degree of Ω · m. The thickness of each of the 1 st TiN layer 32a and the 2 nd TiN layer 32c is 10nm or more, for example, about 50nm to 200 nm.

The metal layer 32b of the p-side current diffusion layer 32 is composed of a single metal layer or a plurality of metal layers. The metal layer 32b is made of a metal material such as titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), palladium (Pd), or rhodium (Rh). The metal layer 32b may have a structure in which a plurality of metal layers having different materials are stacked. The metal layer 32b may have a structure in which a 1 st metal layer made of a 1 st metal material and a 2 nd metal layer made of a 2 nd metal material are stacked, or may have a structure in which a plurality of the 1 st metal layers and a plurality of the 2 nd metal layers are alternately stacked. The metal layer 32b may further include a 3 rd metal layer made of a 3 rd metal material. The thickness of the metal layer 32b is greater than the thickness of each of the 1 st and 2 nd TiN layers 32a and 32 c. The thickness of the metal layer 32b is 100nm or more, for example, about 300nm to 800 nm.

The n-side contact electrode 34 is provided on the 2 nd upper surface 24b of the n-type semiconductor layer 24, and contacts the n-type semiconductor layer 24. The n-side contact electrode 34 is provided so as to close the n-side contact opening 40n of the 2 nd protective layer 40. The n-side contact electrode 34 is provided so as to overlap the 2 nd protective layer 40. The 6 th region W6 where the n-side contact electrode 34 is formed is larger in opening area than the n-side contact opening 40 n. In a plan view when the semiconductor light emitting element 10 is viewed in the thickness direction, the inside of the 4 th region W4 includes the entire opening region of the n-side contact opening 40 n.

The n-side contact electrode 34 has a metal layer 34a and a TiN layer 34 b. The metal layer 34a is made of a material that can make ohmic contact with the n-type semiconductor layer 24 and has a high reflectance to deep ultraviolet light emitted from the active layer 26. The metal layer 34a includes, for example, a Ti layer directly contacting the n-type semiconductor layer 24 and an aluminum (Al) layer directly contacting the Ti layer. The thickness of the Ti layer is about 1nm to 10nm, preferably 5nm or less, and more preferably 1nm to 2 nm. By reducing the thickness of Ti, the ultraviolet reflectance of the n-side contact electrode 34 when viewed from the n-type semiconductor layer 24 can be improved. The thickness of the Al layer is preferably 200nm or more, for example, about 300nm to 1000 nm. By increasing the thickness of the Al layer, the ultraviolet reflectance of the n-side contact electrode 34 can be improved. The metal layer 34a may further have a Ti layer provided on the Al layer.

The TiN layer 34b is provided on the metal layer 34b and is made of conductive TiN. The conductivity of TiN was 1X 10^-5Omega. m or less, e.g. 4X 10^-7Degree of Ω · m. The TiN layer 34b has a thickness of 10nm or more, for example, about 50nm to 200 nm.

The n-side current diffusion layer 36 is provided on the n-side contact electrode 34. The n-side current diffusion layer 36 is provided over an 8 th region W8 that is larger than the 6 th region W6 where the n-side contact electrode 34 is located. In a plan view when the semiconductor light-emitting element 10 is viewed in the thickness direction, the entire 6 th region W6 is included inside the 8 th region W8. Therefore, the n-side current diffusion layer 36 covers the entire upper surface and side surfaces of the n-side contact electrode 34, and prevents the upper surface or side surfaces of the n-side contact electrode 34 from being exposed.

The n-side current diffusion layer 36 includes a 1 st current diffusion layer 48 and a 2 nd current diffusion layer 50. The 1 st current diffusion layer 48 is provided on the n-side contact electrode 34. The 1 st current diffusion layer 48 is provided over a 7 th region W7 larger than the 6 th region W6 in which the n-side contact electrode 34 is formed. In a plan view when the semiconductor light-emitting element 10 is viewed in the thickness direction, the inner side of the 7 th region W7 includes the entire 6 th region W6. Therefore, the 1 st current diffusion layer 48 covers the entire upper surface and side surfaces of the n-side contact electrode 34, and prevents the upper surface or side surfaces of the n-side contact electrode 34 from being exposed. The 1 st current diffusion layer 48 is provided in contact with the 2 nd protective layer 40, but not in contact with the n-type semiconductor layer 24. The thickness of the 1 st current diffusion layer 48 is about 100nm to 1000nm, for example about 200nm to 800 nm.

The 2 nd current diffusion layer 50 is provided on the 1 st current diffusion layer 48. The 2 nd current diffusion layer 50 is provided over an 8 th region W8 wider than the 7 th region W7 where the 1 st current diffusion layer 48 is formed. In a plan view when the semiconductor light-emitting element 10 is viewed in the thickness direction, the inside of the 8 th region W8 includes the entire 7 th region W7. Therefore, the 2 nd current diffusion layer 50 covers the entire upper surface and side surfaces of the 1 st current diffusion layer 48, and prevents the upper surface or side surfaces of the 1 st current diffusion layer 48 from being exposed. The 2 nd current diffusion layer 50 is provided in contact with the 2 nd protective layer 40, but is not in contact with the n-type semiconductor layer 24. The thickness of the 2 nd current diffusion layer 50 is about 300nm to 1500nm, for example, about 500nm to 1000 nm.

The 1 st current diffusion layer 48 has a laminated structure in which a 1 st TiN layer 48a, a metal layer 48b, and a 2 nd TiN layer 48c are laminated in this order. The 1 st TiN layer 48a and the 2 nd TiN layer 48c are made of TiN having conductivity. The conductivity of TiN was 1X 10^-5Omega. m or less, e.g. 4X 10^-7Degree of Ω · m. The thickness of each of the 1 st TiN layer 48a and the 2 nd TiN layer 48c is 10nm or more, for example, about 50nm to 200 nm.

The metal layer 48b included in the 1 st current diffusion layer 48 is made of a single metal layer or a plurality of metal layers. The metal layer 48b is made of a metal material such as titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), palladium (Pd), or rhodium (Rh). The metal layer 48b may have a structure in which a plurality of metal layers different in material are stacked. The metal layer 48b may have a structure in which a 1 st metal layer made of a 1 st metal material and a 2 nd metal layer made of a 2 nd metal material are stacked, or may have a structure in which a plurality of the 1 st metal layers and a plurality of the 2 nd metal layers are alternately stacked. The metal layer 48b may further include a 3 rd metal layer made of a 3 rd metal material. The thickness of the metal layer 48b is greater than the thickness of each of the 1 st TiN layer 48a and the 2 nd TiN layer 48 c. The thickness of the metal layer 48b is 100nm or more, for example, about 200nm to 800 nm.

The 1 st current diffusion layer 48 is formed so as to be in conformity with the height of the p-side contact electrode 30. That is, the height position of the upper surface 48d of the 1 st current diffusion layer 48 substantially coincides with the height position of the upper surface 30a of the p-side contact electrode 30. Specifically, constitutionThe difference between the height position of the upper surface 48d of the 1 st current diffusion layer 48 and the height position of the upper surface 30a of the p-side contact electrode 30 is 100nm or less, preferably 50nm or less. The height position is not particularly limited, and for example, when the 2 nd upper surface 24b of the n-type semiconductor layer 24 is used as a reference, the thickness t from the 2 nd upper surface 24b to the upper surface 48d of the 1 st current diffusion layer 48 is set to be equal to₁And a thickness t from the 2 nd upper surface 24b to the upper surface 30a of the p-side contact electrode 30₂The difference of (A) is 100nm or less or 50nm or less. The height position of the upper surface 48d of the 1 st current diffusion layer 48 may be higher than the height position of the upper surface 30a of the p-side contact electrode 30, may be lower than the height position of the upper surface 30a of the p-side contact electrode 30, or may be completely uniform.

The 2 nd current diffusion layer 50 has a laminated structure in which a 1 st TiN layer 50a, a metal layer 50b, and a 2 nd TiN layer 50c are laminated in this order. The 2 nd current diffusion layer 50 is configured in the same manner as the p-side current diffusion layer 32, and the thickness t of the 2 nd current diffusion layer 50 is set₃And the thickness t of the p-side current diffusion layer 32₄The same is true. As a result, the height position of the upper surface 50d of the 2 nd current diffusion layer 50 substantially coincides with the height position of the upper surface 32d of the p-side current diffusion layer 32. Specifically, the difference between the height position of the upper surface 50d of the 2 nd current diffusion layer 50 and the height position of the upper surface 32d of the p-side current diffusion layer 32 is 100nm or less, preferably 50nm or less. The height position of the upper surface 50d of the 2 nd current diffusion layer 50 may be higher than the height position of the upper surface 32d of the p-side current diffusion layer 32, may be lower than the height position of the upper surface 32d of the p-side current diffusion layer 32, or may be completely uniform.

The 1 st protective layer 38 is provided on the p-type semiconductor layer 28. The 1 st protective layer 38 covers the upper surface 28a of the p-type semiconductor layer 28 at a position different from the 1 st p-side contact opening 38 p. The 1 st protective layer 38 is made of silicon oxide (SiO)₂) And silicon oxynitride (SiON). The thickness of the 1 st protective layer 38 is 50nm or more, for example, 100nm or more and 500nm or less.

The 2 nd protective layer 40 is provided on the 2 nd upper surface 24b of the n-type semiconductor layer 24, on the 1 st protective layer 38, and on the 1 st mesa 52 of the semiconductor light emitting element 10. The 2 nd protective layer 40 is made of alumina (Al)₂O₃) And the like dielectric material. The thickness of the 2 nd protective layer 40 may be set to 5nm to 50nm, and may be set to about 10nm to 30nm, for example.

The 2 nd protective layer 40 covers the 2 nd upper surface 24b of the n-type semiconductor layer 24 at a position different from the n-side contact opening 40 n. The 2 nd protective layer 40 covers the 1 st protective layer 38 at a different portion from the 2p nd side contact opening 40 p. The opening area of the 2 p-th side contact opening 40p is larger than that of the 1 p-th side contact opening 38 p. In a plan view when the semiconductor light emitting element 10 is viewed in the thickness direction, the inside of the opening region of the 2 p-th contact opening 40p includes the entire opening region of the 1 p-th contact opening 38 p.

The 2 nd protective layer 40 covers the 1 st mesa 52. The 1 st land 52 is located inside the 1 st area W1 at the 1 st angle theta₁The inclined side surfaces include the 1 st side surface of the n-type semiconductor layer 24, the side surface of the active layer 26, the side surface of the p-type semiconductor layer 28, and the side surface of the 1 st protective layer 38. 1 st angle θ of inclination of 1 st mesa 52₁Is 15 degrees or more and 50 degrees or less, for example, 20 degrees or more and 40 degrees or less. Angle of 1 st theta₁The refractive index n, preferably θ, of the active layer 26 is used₁<{π/2+sin^-1(1/n) }/2. By applying a 1 st angle theta₁The value is set so that the ultraviolet light is totally reflected by the 2 nd main surface 20b of the substrate 20, and the ultraviolet light can be prevented from being emitted to the outside of the substrate 20.

The 3 rd protective layer 42 is provided so as to cover the entire semiconductor light emitting element 10. The 3 rd protective layer 42 is made of silicon oxide (SiO)₂) And dielectric materials such as silicon nitride oxide (SiON), silicon nitride (SiN), aluminum nitride (AlN) or aluminum oxynitride (AlON). The thickness of the 3 rd protective layer 42 is 100nm or more, for example, about 500nm to 2000 nm.

The 3 rd protective layer 42 is provided on the p-side contact electrode 30, on the p-side current diffusion layer 32, on the n-side current diffusion layer 36, on the 2 nd protective layer 40, and on the 2 nd mesa 54 of the semiconductor light emitting element 10. The 3 rd protective layer 42 covers the p-side current diffusion layer 32 at a position different from the p-side pad opening 42p, and covers the n-side current diffusion layer 36 at a position different from the n-side pad opening 42 n. The 2 nd mesa 54 is a side surface inclined at the 2 nd angle θ 2 larger than the 1 st angle outside the 1 st region W1 and the 2 nd region W2, and includes the 2 nd side surface of the n-type semiconductor layer 24. The 2 nd angle θ 2 of the inclination of the 2 nd mesa 54 is 55 degrees or more and less than 70 degrees, for example, about 60 degrees to 65 degrees.

The p-side pad electrode 44 and the n-side pad electrode 46 are portions to be bonded when the semiconductor light emitting element 10 is mounted on a package substrate or the like. The p-side pad electrode 44 is provided on the p-side current diffusion layer 32, contacts the p-side current diffusion layer 32, and is electrically connected to the p-side contact electrode 30. The p-side pad electrode 44 is provided so as to close the p-side pad opening 42p, and is overlapped on the 3 rd protective layer 42. The n-side pad electrode 46 is provided on the n-side current diffusion layer 36, contacts the n-side current diffusion layer 36, and is electrically connected to the n-side contact electrode 34. The n-side pad electrode 46 is provided so as to close the n-side pad opening 42n, and is superimposed on the 3 rd protective layer 42.

From the viewpoint of corrosion resistance, the p-side pad electrode 44 and the n-side pad electrode 46 are formed to contain Au, and are formed of a stacked structure of Ni/Au, Ti/Au, or Ti/Pt/Au, for example. The p-side pad electrode 44 and the n-side pad electrode 46 may further include a metal layer made of a metal bonding material for bonding, for example, a gold tin (AuSn) layer, or a laminated structure of a Sn layer and an Au layer.

Next, a method for manufacturing the semiconductor light emitting element 10 will be described. Fig. 2 to 13 schematically illustrate the manufacturing process of the semiconductor light emitting element 10. In fig. 2, first, the base layer 22, the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, and the 1 st protective layer 38 are formed in this order on the 1 st main surface 20a of the substrate 20. The active layer 26 is formed on the 1 st upper surface 24a of the n-type semiconductor layer 24.

The substrate 20 is, for example, a patterned sapphire substrate. The base layer 22 includes, for example, an HT-AlN layer and a doped AlGaN layer. The n-type semiconductor layer 24, the active layer 26, and the p-type semiconductor layer 28 are semiconductor layers made of an AlGaN-based semiconductor material, an AlN-based semiconductor material, or a GaN-based semiconductor material, and can be formed by a known epitaxial growth method such as an organometallic compound Vapor Phase Epitaxy (MOVPE) method or a Molecular Beam Epitaxy (MBE) method. The 1 st protective layer 38 is made of SiO₂Or a composition of SiON,the film can be formed by a known technique such as Chemical Vapor Deposition (CVD).

Next, as shown in fig. 2, a 1 st mask 61 is formed on the 1 st protective layer 38. The 1 st mask 61 is an etching mask for forming the 1 st mesa 52 of fig. 1. The 1 st mask 61 may be formed using a known photolithography technique. The 1 st mask 61 is provided in a portion corresponding to the 1 st region W1 in fig. 1. The side of the 1 st mask 61 is inclined. The inclination angle of the side surface of the 1 st mask 61 is formed at the 1 st angle theta in the subsequent etching process₁The manner of the inclined 1 st land 52.

Next, as shown in fig. 3, the 1 st protective layer 38, the p-type semiconductor layer 28, and the active layer 26 are etched from the 1 st mask 61, so that the n-type semiconductor layer 24 in the region not overlapping with the 1 st mask 61 is exposed. The etching depth d in this etching step corresponds to the total thickness of the active layer 26, the p-type semiconductor layer 28, and the 1 st protective layer 38, and is, for example, 400nm to 1500 nm. By the etching process, the etching liquid is formed at the 1 st angle theta₁The inclined 1 st mesa 52 and the 2 nd upper surface 24b of the n-type semiconductor layer 24.

In the etching step of fig. 3, reactive ion etching using a chlorine-based etching gas may be used, and Inductively Coupled Plasma (ICP) etching may be used. For example, chlorine (Cl) -containing gas may be used as the etching gas₂) Boron trichloride (BCl)₃) Silicon tetrachloride (SiCl)₄) And chlorine-like reactive gases. In addition, dry etching may be performed by combining a reactive gas with an inert gas, or a rare gas such as argon (Ar) may be mixed with a chlorine-based gas. After the 1 st mesa 52 and the 2 nd upper surface 24b are formed, the 1 st mask 61 is removed.

Next, as shown in fig. 4, a 2 nd protective layer 40 is formed. The 2 nd protective layer 40 covers the 2 nd upper surface 24b of the n-type semiconductor layer 24, covers the 1 st protective layer 38, and covers the 1 st side surface of the n-type semiconductor layer 24, the side surface of the active layer 26, and the side surface of the p-type semiconductor layer 28 (i.e., the 1 st mesa 52). The 2 nd protective layer 40 is made of, for example, Al₂O₃The composition can be prepared by mixing Trimethylaluminum (TMA) and O₂Plasma or O₃An Atomic Layer Deposition (ALD) method as a raw material.

Next, as shown in fig. 5, a 2 nd mask 62 is formed on the 2 nd protective layer 40, and the 2 nd protective layer 40 located in the 1 st opening 71 and the 2 nd opening 72 where the 2 nd mask 62 is not provided is removed. The 2 nd mask 62 may be formed using known photolithography techniques. The 2 nd protective layer 40 may be dry etched using a chlorine-based gas or a mixed gas of a chlorine-based gas and a rare gas. By this etching step, the 2 p-th contact opening 40p and the n-th contact opening 40n are formed. In the 2 p-th side contact opening 40p, the 1 st protective layer 38 is exposed. In the n-side contact opening 40n, the 2 nd upper surface 24b of the n-type semiconductor layer 24 is exposed. After the 2 nd p-side contact opening 40p and the n-side contact opening 40n are formed, the 2 nd mask 62 is removed.

Next, as shown in fig. 6, a 3 rd mask 63 is formed on the 2 nd protective layer 40, and the n-side contact electrode 34 is formed on the 3 rd opening 73 where the 3 rd mask 63 is not provided. The 3 rd mask 63 may be formed using a known photolithography technique. The 3 rd opening 73 is located in the 6 th region W6 where the n-side contact electrode 34 should be formed. The opening area of the 3 rd opening 73 is larger than the opening area of the n-side contact opening 40 n. On the 3 rd opening 73, the metal layer 34a is first formed. The metal layer 34a includes a Ti layer, an Al layer, and a Ti layer stacked in this order. Next, a TiN layer 34b is formed on the metal layer 34 a. Each layer of the metal layer 34a and the TiN layer 34b can be formed by sputtering or EB evaporation.

Next, the 3 rd mask 63 is removed, and annealing treatment is performed on the n-side contact electrode 34. The annealing treatment of the n-side contact electrode 34 is performed at a temperature lower than the melting point of Al (about 660 ℃), for example, at a temperature of 500 ℃ or higher and 650 ℃ or lower, preferably 550 ℃ or higher and 625 ℃ or lower. The contact resistance of the n-side contact electrode 34 can be set to 1 × 10 by annealing^-2Ω·cm²The following. Further, by setting the annealing temperature to be lower than the melting point of Al, the flatness of the n-side contact electrode 34 after annealing can be improved, and the ultraviolet reflectance can be set to 80% or more or 90% or more.

Next, as shown in fig. 7, a 4 th mask 64 is formed on the n-side contact electrode 34 and the 2 nd protective layer 40, and the 1 st protective layer 38 located at the 4 th opening 74 where the 4 th mask 64 is not provided is removed. The 4 th mask 64 may be formed using known photolithography techniques. Opening area ratio of the 4 th opening 74The opening area of the 2 p-th side contact opening 40p is narrow. Hydrofluoric acid (HF) and ammonium fluoride (NH) may be used for the first passivation layer 38₄F) The mixed solution of (3) is removed by buffered hydrofluoric acid (BHF). By removing the 1 st protective layer 38 on the 4 th opening 74, the 1 st p-side contact opening 38p is formed. In the 1 p-th side contact opening 38p, the upper surface 28a of the p-type semiconductor layer 28 is exposed. By performing wet etching on the 1 st protective layer 38, damage to the upper surface 28a of the exposed p-type semiconductor layer 28 can be reduced as compared with the case where the 1 st protective layer 38 is dry etched. After the 1 p-th side contact opening 38p is formed, the 4 th mask 64 is removed.

Next, as shown in fig. 8, a 5 th mask 65 is formed on the n-side contact electrode 34 and the 2 nd protective layer 40, and the p-side contact electrode 30 is formed on the 5 th opening 75 where the 5 th mask 65 is not provided. The 5 th opening 75 is located in the 4 th area W4 of fig. 1. The opening area of the 5 th opening 75 is larger than the opening areas of the 1 p-th side contact opening 38p and the 2 p-th side contact opening 40 p. The p-side contact electrode 30 is in contact with the upper surface 28a of the p-type semiconductor layer 28, and is provided so as to close the 1 p-side contact opening 38p and the 2 p-side contact opening 40 p. The p-side contact electrode 30 is made of ITO, for example, and can be formed by a sputtering method.

Next, the 5 th mask 65 is removed, and annealing treatment is performed on the p-side contact electrode 30. The contact resistance of the p-side contact electrode 30 can be made 1 × 10 by annealing^-2Ω·cm²The following.

Next, as shown in fig. 9, a 6 th mask 66 is formed on the p-side contact electrode 30 and the 2 nd protective layer 40, and the 1 st current diffusion layer 48 is formed on the 6 th opening 76 where the 6 th mask 66 is not provided. The 6 th mask 66 may be formed using known photolithography techniques. The 6 th opening 76 is located at the 7 th region W7 where the 1 st current diffusion layer 48 should be formed. The 6 th opening 76 is larger than the 6 th region W6 where the n-side contact electrode 34 is formed. The 1 st current diffusion layer 48 is formed on the n-side contact electrode 34 after the annealing treatment. First, a 1 st TiN layer 48a is formed on the 6 th opening 76, a metal layer 48b is formed on the 1 st TiN layer 48a, and a 2 nd TiN layer 48c is formed on the metal layer 48 b. The 1 st TiN layer 48a, the metal layer 48b, and the 2 nd TiN layer 48c can be formed by sputtering or EB evaporation. The height position of the upper surface 48d of the 1 st current diffusion layer 48 corresponds to the height position of the upper surface 30a of the p-side contact electrode 30. The difference between the height position of the upper surface 30a of the p-side contact electrode 30 and the height position of the upper surface 48d of the 1 st current diffusion layer 48 is 100nm or less or 50nm or less. After the 1 st current diffusion layer 48 is formed, the 6 th mask 66 is removed.

Next, as shown in fig. 10, a 7 th mask 67 is formed on the p-side contact electrode 30, the 2 nd protective layer 40, and the 1 st current diffusion layer 48. The p-side current diffusion layer 32 is formed on the 7 th opening 77 where the 7 th mask 67 is not provided, and the 2 nd current diffusion layer 50 is formed on the 8 th opening 78 where the 7 th mask 67 is not provided. The 7 th opening 77 is located at the 5 th area W5 of fig. 1. The opening region of the 7 th opening 77 is narrower than the 4 th region W4 where the p-side contact electrode 30 is formed. The 8 th opening 78 is located in the 8 th area W8 of fig. 1. The opening area of the 8 th opening 78 is larger than the 7 th area W7 where the 1 st current diffusion layer 48 is formed.

The p-side current diffusion layer 32 is formed on the p-side contact electrode 30 over the 7 th opening 77. The 2 nd current spreading layer 50 is formed on the 1 st current spreading layer 48 on the 8 th opening 78. The p-side current diffusion layer 32 and the 2 nd current diffusion layer 50 may be formed simultaneously. First, the 1 st TiN layer 32a, 50a is formed, then the metal layer 32b, 50b is formed, and then the 2 nd TiN layer 32c, 50c is formed. The 1 st TiN layers 32a and 50a, the metal layers 32b and 50b, and the 2 nd TiN layers 32c and 50c may be formed by sputtering or EB evaporation. By forming the p-side current diffusion layer 32 and the 2 nd current diffusion layer 50 at the same time, the p-side current diffusion layer 32 and the 2 nd current diffusion layer 50 can be made to have the same thickness, and the height position of the upper surface 32d of the p-side current diffusion layer 32 and the height position of the upper surface 50d of the 2 nd current diffusion layer 50 can be made to coincide. After the p-side current diffusion layer 32 and the 2 nd current diffusion layer 50 are formed, the 7 th mask 67 is removed.

Note that the p-side current diffusion layer 32 and the 2 nd current diffusion layer 50 may be formed separately, instead of being formed at the same time. For example, after the p-side current diffusion layer 32 is formed using the mask for forming the p-side current diffusion layer 32, the 2 nd current diffusion layer 50 may be formed using the mask for forming the 2 nd current diffusion layer 50. The order of forming the p-side current diffusion layer 32 and the 2 nd current diffusion layer 50 is not particularly limited, and the p-side current diffusion layer 32 may be formed after the 2 nd current diffusion layer 50 is formed. For example, the p-side current diffusion layer 32 may be formed after the 1 st current diffusion layer 48 and the 2 nd current diffusion layer 50 are formed in succession.

Next, as shown in fig. 11, an 8 th mask 68 is formed so as to cover the p-side contact electrode 30, the p-side current diffusion layer 32, the 2 nd protective layer 40, and the n-side current diffusion layer 36. The 8 th mask 68 is provided over the 1 st region W1 and the 2 nd region W2 in fig. 1. The side of the 8 th mask 68 is inclined to be able to form a 2 nd angle theta₂The manner of the sloped 2 nd mesa 54 sets the slope angle of the side of the 8 th mask 68. The 8 th mask 68 may be formed using known photolithography techniques. Next, the 2 nd protective layer 40 and the n-type semiconductor layer 24 are etched from the 8 th mask 68, and the base layer 22 in the region not overlapping with the 8 th mask 68 is exposed. By the etching process, the 2 nd angle theta is formed₂A sloped 2 nd mesa 54. The 2 nd protective layer 40 and the n-type semiconductor layer 24 can be dry-etched using a chlorine-based gas or a mixed gas of a chlorine-based gas and a rare gas. After the 2 nd mesa 54 is formed, the 8 th mask 68 is removed.

Next, as shown in fig. 12, the 3 rd protective layer 42 is formed so as to cover the 2 nd side surface (the 2 nd mesa 54) of the n-type semiconductor layer 24, the p-side contact electrode 30, the p-side current diffusion layer 32, the 2 nd protective layer 40, and the n-side current diffusion layer 36. The 3 rd protective layer 42 is formed over both the 1 st region W1 and the 2 nd region W2 so as to cover the entire upper surface of the element structure. The 3 rd protective layer 42 is made of, for example, SiO₂Or SiON, and may be formed by a known technique such as compound vapor phase epitaxy (CVD).

Next, as shown in fig. 13, a 9 th mask 69 is formed on the 3 rd protective layer 42, and the 3 rd protective layer 42 located at the 9 th opening 79, the 10 th opening 80, and the 11 th opening 81 where the 9 th mask 69 is not provided is removed. The 3 rd protective layer 42 may be dry etched using a CF-based etching gas, for example, hexafluoroethane (C2F6) may be used. By this etching step, p-side pad opening 42p where p-side current diffusion layer 32 is exposed is formed in 9 th opening 79, and n-side pad opening 42n where n-side current diffusion layer 36 is exposed is formed in 10 th opening 80. In addition, the base layer 22 is exposed in the 11 th opening 81. The 11 th opening 81 is located in an element separating region in the case where a plurality of semiconductor light emitting elements 10 are formed from 1 substrate. After performing an etching process of partially removing the 3 rd protective layer 42, the 9 th mask 69 is removed.

In the dry etching step shown in fig. 13, the p-side current diffusion layer 32 and the n-side current diffusion layer 36 function as etching stoppers. More specifically, the 2 nd TiN layer 32c of the p-side current diffusion layer 32 and the 2 nd TiN layer 48c of the 1 st current diffusion layer 48 function as etching stoppers. The TiN has low reactivity with the fluorine-based etching gas for removing the 3 rd protective layer 42, and by-products due to etching are less likely to be generated. Therefore, damage to the p-side contact electrode 30 and the n-side contact electrode 34 can be prevented. In addition, even after the dry etching is performed, the exposed surfaces of the p-side current diffusion layer 32 and the n-side current diffusion layer 36 can be maintained at high quality.

Next, a p-side pad electrode 44 is formed on the p-side current diffusion layer 32 on the p-side pad opening 42p, and an n-side pad electrode 46 is formed on the n-side current diffusion layer 36 on the n-side pad opening 42 n. The p-side pad electrode 44 and the n-side pad electrode 46 can be formed, for example, by depositing a Ni layer or a Ti layer on the p-side current diffusion layer 32 and the n-side current diffusion layer 36, and depositing an Au layer thereon. Further, another metal layer may be provided on the Au layer, and for example, a Sn layer, an AuSn layer, or a Sn/Au stacked structure may be formed.

The p-side pad electrode 44 and the n-side pad electrode 46 may be formed simultaneously or separately. For example, after the p-side pad electrode 44 is formed using a mask for forming the p-side pad electrode 44, the n-side pad electrode 46 may be formed using a mask for forming the n-side pad electrode 46. The order of forming the p-side pad electrode 44 and the n-side pad electrode 46 is not particularly limited, and the p-side pad electrode 44 may be formed after the n-side pad electrode 46 is formed.

Through the above steps, the semiconductor light emitting element 10 shown in fig. 1 is formed.

According to the present embodiment, by providing the p-side current diffusion layer 32, the current injected from the p-side pad electrode 44 can be diffused in the lateral direction (horizontal direction), and the light emitting area of the active layer 26 can be enlarged. This can improve the light output of the semiconductor light-emitting element 10.

According to the present embodiment, by making the 5 th region W5 in which the p-side current diffusion layer 32 is formed narrower than the 4 th region W4 in which the p-side contact electrode 30 is formed, the maximum value of the area occupied by the p-side contact electrode 30 on the upper surface 28a of the p-type semiconductor layer 28 can be further increased. If the 5 th region W5 in which the p-side current diffusion layer 32 is formed is made larger than the 4 th region W4 in which the p-side contact electrode 30 is formed, the 5 th region W5 is narrower than the 3 rd region W3 in which the upper surface 28a of the p-type semiconductor layer 28 is located, and the 4 th region W4 is narrower than the 5 th region W5, so that the maximum area that the 4 th region W4 can take is reduced. On the other hand, according to the present embodiment, the area occupied by the p-side contact electrode 30 on the upper surface 28a of the p-type semiconductor layer 28 can be increased as much as possible, and the light emitting area of the active layer 26 can be enlarged. This can improve the light output of the semiconductor light-emitting element 10.

According to the present embodiment, by making the 8 th region W8 in which the n-side current diffusion layer 36 is formed larger than the 6 th region W6 in which the n-side contact electrode 34 is formed, the n-side current diffusion layer 36 can cover the entire n-side contact electrode 34. Further, since the n-side current diffusion layer 36 is composed of the 1 st current diffusion layer 48 and the 2 nd current diffusion layer 50, the function of covering and sealing the n-side contact electrode 34 can be further improved. This can prevent the Al layer included in the n-side contact electrode 34 from being corroded by oxidation or the like during current application. As a result, a decrease in the ultraviolet light reflectance of the n-side contact electrode 34 can be suppressed, the function as a reflective electrode can be maintained for a long period of time, and a decrease in the light output used with energization can be suppressed. That is, the semiconductor light emitting element 10 capable of maintaining a high light output for a long period of time can be realized.

According to the present embodiment, a multilayer structure in which a TiN layer, a metal layer, and a TiN layer are sequentially stacked is used as the p-side current diffusion layer 32 and the n-side current diffusion layer 36, whereby high conductivity can be achieved and metal migration can be prevented. For example, specifically, migration of metal can be prevented by using a TiN layer, and conductivity can be improved by interposing a metal layer between the TiN layer and the TiN layer.

According to this embodiment, the p-side can be contacted by providing the 1 st current diffusion layer 48The height position of the upper surface 30a of the pole 30 coincides with the height position of the upper surface 48d of the 1 st current diffusion layer 48. In particular, in this embodiment, the thickness t from the 2 nd upper surface 24b of the n-type semiconductor layer 24 to the upper surface 28a of the p-type semiconductor layer 28 is larger than the thickness t₀Since the thickness is about 400nm to 1500nm, the p-side pad electrode 44 and the n-side pad electrode 46 are greatly deviated in height when the 1 st current diffusion layer 48 for height adjustment is not provided. When the p-side pad electrode 44 and the n-side pad electrode 46 are largely deviated in height, uneven force may be applied to the semiconductor light emitting element and damage may occur to the semiconductor light emitting element when the semiconductor light emitting element is bonded to a mounting substrate or the like. In particular, when the height deviation between the p-side pad electrode 44 and the n-side pad electrode 46 is 200nm or more or 500nm or more, the defect rate at the time of mounting tends to increase. On the other hand, according to the present embodiment, by setting the difference between the height position of the upper surface 30a of the p-side contact electrode 30 and the height position of the upper surface 48d of the 1 st current diffusion layer 48 to 100nm or less, the difference in height between the p-side pad electrode 44 and the n-side pad electrode 46 can be set to 100nm or less, and the fraction defective during mounting can be reduced.

According to the present embodiment, by making the structures and thicknesses of the p-side current diffusion layer 32 and the 2 nd current diffusion layer 50 substantially the same, it is possible to make the forces applied to the p-side contact electrode 30 and the 1 st current diffusion layer 48 uniform at the time of mounting the semiconductor light emitting element 10, and it is possible to reduce the fraction defective at the time of mounting.

According to the present embodiment, by using a TiN layer for the p-side current diffusion layer 32 and the n-side current diffusion layer 36, the adhesion to the 3 rd protective layer 42 made of a dielectric material can be improved. This can prevent the 3 rd protective layer 42 from peeling off from the p-side contact electrode 30 and the n-side contact electrode 34, which leads to a reduction in sealing function. This can realize the semiconductor light emitting element 10 in which the light output is not easily reduced for a long period of time.

According to the present embodiment, by performing the annealing treatment in a state where the TiN layer 34b is provided on the metal layer 34a of the n-side contact electrode 34, oxidation of the metal layer 34a during the annealing treatment can be prevented. This can prevent a decrease in the ultraviolet light reflectance of the n-side contact electrode 34 and a decrease in the flatness of the upper surface of the n-side contact electrode 34.

According to the present embodiment, by forming the 1 st current diffusion layer 48 and the 2 nd current diffusion layer 50 after the annealing treatment of the n-side contact electrode 34, it is possible to prevent the 1 st current diffusion layer 48 and the 2 nd current diffusion layer 50 from being deteriorated by the annealing treatment. Similarly, by forming the p-side current diffusion layer 32 after the annealing treatment of the p-side contact electrode 30, the p-side current diffusion layer 32 can be prevented from being degraded by the annealing treatment.

[ 2 nd embodiment ]

Fig. 14 is a cross-sectional view schematically showing the structure of a semiconductor light emitting element 110 according to embodiment 2. The semiconductor light emitting element 110 in fig. 14 differs from the above embodiment in the configuration of the p-side contact electrode 130, the p-side current diffusion layer 132, the n-side current diffusion layer 136, the 1 st protective layer 138, and the 2 nd protective layer 140. Hereinafter, the present embodiment will be described mainly focusing on differences from embodiment 1 described above, and overlapping description will be omitted as appropriate.

The semiconductor light emitting element 110 includes: the semiconductor device includes a substrate 20, a base layer 22, an n-type semiconductor layer 24, an active layer 26, a p-type semiconductor layer 28, a p-side contact electrode 130, a p-side current diffusion layer 132, an n-side contact electrode 34, an n-side current diffusion layer 136, a 1 st protective layer 138, a 2 nd protective layer 140, a 3 rd protective layer 42, a p-side pad electrode 44, and an n-side pad electrode 46.

The p-side contact electrode 130 is provided on the upper surface 28a of the p-type semiconductor layer 28 and between the p-type semiconductor layer 28 and the 1 st protective layer 138. The p-side contact electrode 130 is different from the p-side contact electrode 30 of the above embodiment in a point provided on the lower side of the 1 st protective layer 138. The p-side contact electrode 130 has a metal layer 130b and a TiN layer 130 c. The metal layer 130b is formed of a platinum group metal such as Rh or a laminated structure of Ni/Au. The TiN layer 130c is made of conductive TiN and provided to cover the upper surface and the side surface of the metal layer 130 b. The height position of the upper surface 130a of the p-side contact electrode 130 coincides with the height position of the upper surface 48d of the 1 st current diffusion layer 48. The difference between the height position of the upper surface 130a of the p-side contact electrode 130 and the height position of the upper surface 48d of the 1 st current diffusion layer 48 is 100nm or less, preferably 50nm or less.

The p-side current diffusion layer 132 is provided on the upper surface 130a of the p-side contact electrode 130. The p-side current diffusion layer 132 is provided so as to close the 1 st p-side contact opening 138p provided in the 1 st protective layer 138 and the n-side contact opening 140p provided in the 2 nd protective layer 140. The p-side current diffusion layer 132 is provided so as to overlap the 1 st protective layer 138 and the 2 nd protective layer 140. The p-side current diffusion layer 132 has a laminated structure in which a 1 st TiN layer 132a, a metal layer 132b, and a 2 nd TiN layer 132c are laminated in this order.

The n-side current diffusion layer 136 is provided over a 7 th region W7 larger than the 6 th region W6 in which the n-side contact electrode 34 is formed. The n-side current diffusion layer 136 includes the 1 st current diffusion layer 48 and the 2 nd current diffusion layer 150. The 1 st current diffusion layer 48 is configured in the same manner as in the above embodiment. Unlike the above embodiment, the 2 nd current diffusion layer 150 is provided in the 9 th region W9 narrower than the 7 th region W7 in which the 1 st current diffusion layer 48 is formed. In a plan view of the semiconductor light emitting element 110 viewed in the thickness direction, the inner side of the 7 th region W7 includes the entire 9 th region W9. In the illustrated example, the 9 th region W9 in which the 2 nd current diffusion layer 150 is provided is narrower than the 6 th region W6 in which the n-side contact electrode 34 is provided. The 9 th region W9 in which the 2 nd current diffusion layer 150 is provided may coincide with the 6 th region W6, or may be larger than the 6 th region W6.

The 2 nd current diffusion layer 150 has a laminated structure in which a 1 st TiN layer 150a, a metal layer 150b, and a 2 nd TiN layer 150c are laminated in this order. The 2 nd current diffusion layer 150 is configured in the same manner as the p-side current diffusion layer 132, and the thickness t of the 2 nd current diffusion layer 150₃And the thickness t of the p-side current diffusion layer 132₄The same is true. As a result, the height position of the upper surface 150d of the 2 nd current diffusion layer 150 substantially coincides with the height position of the upper surface 132d of the p-side current diffusion layer 132. Specifically, the difference between the height position of the upper surface 150d of the 2 nd current diffusion layer 150 and the height position of the upper surface 132d of the p-side current diffusion layer 132 is 100nm or less, preferably 50nm or less.

Next, a method for manufacturing the semiconductor light emitting element 110 will be described. Fig. 15 is a view schematically showing the steps of manufacturing the semiconductor light emitting element 110. In fig. 15, first, the foundation layer 22, the n-type semiconductor layer 24, the active layer 26, and the p-type semiconductor layer 28 are formed on the 1 st main surface 20a of the substrate 20. The formation method of these layers is the same as the process of fig. 2.

Next, a p-side contact electrode 130 is formed on the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 130 is formed in the 4 th region W4 of fig. 14. First, a mask is formed on the upper surface 28a of the p-type semiconductor layer 28 except for the 4 th region W4. Next, the metal layer 130b is formed in the 4 th region W4, and the TiN layer 130c is formed on the metal layer 130 b. The p-side contact electrode 130 can be formed by sputtering or EB evaporation. Thereby, the p-side contact electrode 130 is formed. After the p-side contact electrode 130 is formed, the mask may be removed, and the p-side contact electrode 130 may be annealed.

Next, as shown in fig. 16, a 1 st protective layer 138 is formed on the p-type semiconductor layer 28 and the p-side contact electrode 130. The 1 st protective layer 138 is made of SiO₂Or SiON, and may be formed by a known technique such as CVD.

Next, as shown in fig. 17, the 1 st mesa 52 is formed. The 1 st mesa 52 is formed in the same manner as in the step of fig. 3.

Next, as shown in fig. 18, a 2 nd protective layer 140 is formed so as to cover the 2 nd upper surface 24b of the n-type semiconductor layer 24 and the 1 st protective layer 138. The 2 nd protective layer 140 may be formed in the same manner as the process of fig. 4. Next, the 2 nd protective film 140 is partially removed, and a 2 nd p-side contact opening 140p and an n-side contact opening 140n are formed. The 2 p-side contact opening 140p and the n-side contact opening 140n can be formed in the same manner as in the step of fig. 5.

Next, as shown in fig. 19, the n-side contact electrode 34 is formed in the n-side contact opening 140n, and the 1 st current diffusion layer 48 is formed on the n-side contact electrode 34. The n-side contact electrode 34 can be formed in the same manner as in the step of fig. 6. The 1 st current diffusion layer 48 can be formed in the same manner as in the step of fig. 9.

Next, as shown in fig. 20, a 1 st p-side contact opening 138p is formed in the 1 st protective layer 138, and the upper surface 130a of the p-side contact electrode 130 is exposed. The 1 p-th contact opening 138p may be formed in the same manner as in the step of fig. 7.

Next, as shown in fig. 21, a p-side current diffusion layer 132 is formed on the p-side contact electrode 130, and a 2 nd current diffusion layer 150 is formed on the 1 st current diffusion layer 48. The 5 th region W5 where the p-side current diffusion layer 132 is formed is narrower than the 4 th region W4 where the p-side contact electrode 130 is formed. In addition, the 9 th region W9 where the 2 nd current diffusion layer 150 is formed is narrower than the 7 th region W7 where the 1 st current diffusion layer 48 is formed. The p-side current diffusion layer 132 and the 2 nd current diffusion layer 150 may be formed simultaneously, and may be formed in the same manner as in the step of fig. 10.

Next, in the same manner as in the steps of fig. 11 to 13, the 2 nd land 54 is formed, the 3 rd protective layer 42 is formed, the n-side pad opening 42n and the p-side pad opening 42p are formed in the 3 rd protective layer 42, and the p-side pad electrode 44 and the n-side pad electrode 46 are formed. Through the above steps, the semiconductor light emitting element 110 shown in fig. 14 is formed.

The semiconductor light emitting element 110 of the present embodiment can also exhibit the same effects as those of the above-described embodiments. In addition, according to this embodiment, since the p-side contact electrode 130 includes the TiN layer 130c, the adhesion of the p-side contact electrode 130 to the 1 st protective layer 138 can be improved.

The present invention has been described above based on the embodiments. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, various design changes may be made, and various modifications may be made, and such modifications are also included in the scope of the present invention.

In other embodiments, the structures of the semiconductor light emitting elements 10 and 110 of the above embodiments may be appropriately replaced. For example, the semiconductor light emitting element 10 of fig. 1 may include an n-side current diffusion layer 136 shown in fig. 14 instead of the n-side current diffusion layer 36 shown in fig. 1. Similarly, the semiconductor light emitting element 110 shown in fig. 14 may be provided with the n-side current diffusion layer 36 shown in fig. 1 instead of the n-side current diffusion layer 136 shown in fig. 14.

In one embodiment, at least one of the 1 st current diffusion layer 48 and the 2 nd current diffusion layers 50 and 150 is provided over a region larger than the 6 th region W6 where the n-side contact electrode 34 is formed. For example, as shown in fig. 14, the 1 st current diffusion layer 48 is provided in a region larger than the 6 th region W6, and the 2 nd current diffusion layers 50 and 150 are provided in a region corresponding to the 6 th region W6 or in a region narrower than the 6 th region W6. The 2 nd current diffusion layer 50, 150 may be provided in a region larger than the 6 th region W6 than the 1 st current diffusion layer 48 provided in a region corresponding to the 6 th region W6 or a region narrower than the 6 th region W6. In these cases, the 7 th region W7 where the 1 st current diffusion layer 48 is formed may coincide with the 8 th region W8 or the 9 th region W9 where the 2 nd current diffusion layers 50 and 150 are formed, may be narrower than the 8 th region W8 or the 9 th region W9, or may be larger than the 8 th region W8 or the 9 th region W9.

In the above embodiment, the case where the n-side current diffusion layers 36 and 136 include the 1 st current diffusion layer 48 and the 2 nd current diffusion layers 50 and 150 is shown. In another embodiment, the n-side current diffusion layers 36 and 136 may be formed of only 1 current diffusion layer. That is, the n-side current diffusion layer 36 or 136 may have a laminated structure including only 1 st TiN layer, a metal layer, and a 2 nd TiN layer. The n-side current diffusion layers 36 and 136 may have a laminated structure of 3 or more layers of the 1 st TiN layer, the metal layer, and the 2 nd TiN layer. The p-side current diffusion layers 32 and 132 may have a laminated structure of 2 or more layers of the 1 st TiN layer, the metal layer, and the 2 nd TiN layer.

[ description of reference numerals ]

10 … semiconductor light emitting element, 24 … n-type semiconductor layer, 24a … first upper surface, 24b … second upper surface …, 26 … active layer, 28 … P-type semiconductor layer, 28a … upper surface, 30 … P-side contact electrode, 30a … upper surface, 30P … P-side contact electrode, 32 … P-side current diffusion layer, 32a … first TiN layer, 32b … metal layer, 32c … second TiN layer, 32d … upper surface, 34 … n-side contact electrode, 34a … metal layer, 34b … TiN layer, 36 … n-side current diffusion layer, 44 … P-side pad electrode, 46 … n-side pad electrode, 48 … first current diffusion layer, 48a … first TiN layer, 48b … metal layer, 48c … second layer, 48d … upper surface, 50 second current diffusion layer, 50a … first TiN layer, … second TiN layer, … upper surface 3650 c … c layer, … upper surface … c 50c … c layer, … upper surface.