阅读说明：本技术 反激式均衡电路的电流采样装置、方法和电池均衡系统 (Current sampling device and method of flyback equalization circuit and battery equalization system ) 是由 陈建清 胡友涛 滕云龙 张振沣 于 2021-07-26 设计创作，主要内容包括：本发明公开了一种反激式均衡电路的电流采样装置、方法和电池均衡系统,该装置包括：第一采样模块,采集变压器的原边线圈锁在支路上的原边均衡电流；第一均衡电流调理单元,对原边均衡电流进行调理,以得到原边均衡电流的瞬时值；第二采样模块,采集变压器的副边线圈所在支路上的副边均衡电流；第二均衡电流调理单元,对第二采样模块采样得到的所述副边均衡电流进行调理,以得到副边均衡电流的瞬时值；控制单元,基于相应均衡电流的瞬时值、以及相应开关管的驱动信号的占空比进行计算,得到相应均衡电流的有效值。该方案,通过设置反激式均衡电流采集电路,能够提高均衡电流的采样精度,进而提高在电池均衡管理中对电池荷电状态的估算准确性。(The invention discloses a current sampling device and a method of a flyback equalizing circuit and a battery equalizing system, wherein the device comprises: the first sampling module is used for acquiring primary side balanced current of a primary side coil of a transformer locked on a branch circuit; the first equalizing current conditioning unit is used for conditioning the primary equalizing current to obtain an instantaneous value of the primary equalizing current; the second sampling module is used for collecting secondary side balance current on a branch where a secondary side coil of the transformer is located; the second equalizing current conditioning unit is used for conditioning the secondary equalizing current sampled by the second sampling module to obtain an instantaneous value of the secondary equalizing current; and the control unit calculates based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube to obtain the effective value of the corresponding equalizing current. According to the scheme, the flyback type balanced current acquisition circuit is arranged, so that the sampling precision of balanced current can be improved, and the estimation accuracy of the state of charge of the battery in the battery balance management is further improved.)

1. A current sampling device of a flyback equalization circuit, the flyback equalization circuit comprising: a transformer and a switching tube unit; the switching tube unit includes: the first switch tube and/or the second switch tube; the first switching tube is arranged on a branch circuit where a primary coil of the transformer is located; the second switching tube is arranged on a branch circuit where the secondary coil of the transformer is located;

the current sampling device of the flyback equalizing circuit comprises: a sampling module; the sampling module comprises: a first sampling module and/or a second sampling module;

the current sampling device of the flyback equalizing circuit further comprises: the device comprises a balance current conditioning unit and a control unit; the balanced current conditioning unit comprises: the first equalizing current conditioning unit and/or the second equalizing current conditioning unit; wherein the content of the first and second substances,

the first sampling module is configured to acquire a primary side balanced current of a primary side coil of the transformer locked on a branch circuit;

the first equalizing current conditioning unit is configured to condition the primary equalizing current sampled by the first sampling module to obtain an instantaneous value of the primary equalizing current sampled by the first sampling module;

the second sampling module is configured to collect secondary side equalizing current on a branch where a secondary side coil of the transformer is located;

the second equalizing current conditioning unit is configured to condition the secondary equalizing current sampled by the second sampling module to obtain an instantaneous value of the secondary equalizing current sampled by the second sampling module;

the control unit is configured to, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, perform calculation based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube to obtain the effective value of the corresponding equalizing current sampled by the corresponding sampling module.

2. The current sampling device of the flyback equalization circuit of claim 1, wherein the first equalization current conditioning unit and the second equalization current conditioning unit have the same structure.

3. The current sampling device of the flyback equalization circuit of claim 1, wherein the first equalization current conditioning unit comprises: a biasing module;

the bias module is configured to process the amplitude of the primary side equalization current of the transformer sampled by the first sampling module, so as to adjust the voltage, expressed on the first sampling module, of the primary side equalization current of the transformer sampled by the first sampling module, to be within a set sampling range.

4. The current sampling device of the flyback equalization circuit of claim 3, wherein the bias module comprises: an adder circuit and a bias circuit;

the addition circuit includes: a first operational amplifier and its peripheral circuits; the bias circuit includes: a second operational amplifier and its peripheral circuits;

the output end of the first sampling module is input to the non-inverting input end of the first operational amplifier; the inverting input end of the second operational amplifier and the output end of the second operational amplifier are both connected to the non-inverting input end of the first operational amplifier; and the output end of the second operational amplifier can be output to the first AD sampling end of the control unit.

5. The current sampling device of the flyback equalization circuit of claim 1, wherein the first equalization current conditioning unit further comprises: an isolation module;

the isolation module is configured to isolate an input end of the isolation module and an output end of the isolation module so as to isolate a current sampling device of the flyback equalization circuit from the flyback equalization circuit.

6. The current sampling device of the flyback equalization circuit of claim 5, wherein the isolation module comprises: the isolation chip, the third operational amplifier and peripheral circuits thereof;

under the condition that the first equalizing current conditioning unit comprises an adding circuit and a biasing circuit, the output end of a second operational amplifier in the adding circuit passes through the isolating chip and the third operational amplifier, and then is output to the first AD sampling end of the control unit from the output end of the third operational amplifier.

7. The current sampling device of the flyback equalization circuit of claim 1, wherein the first equalization current conditioning unit further comprises: a filtering module;

the filtering module is configured to filter the primary side balanced current of the transformer sampled by the first sampling module;

wherein, in the case that the first equalizing current conditioning unit includes at least one of a bias module and an isolation module, the filtering module is disposed at an output end of at least one of the bias module and the isolation module.

8. The current sampling device of the flyback equalization circuit of claim 1, wherein the first equalization current conditioning unit further comprises: a clamping module;

the first sampling module samples the primary side equalizing current of the transformer and is embodied in the form of voltage applied to the first sampling module; the clamping module is configured to clamp the voltage on the first sampling module;

wherein, in the case that the first equalizing current conditioning unit includes at least one of a bias module, an isolation module and a filter module, the clamping module is disposed at an output end of at least one of the bias module, the isolation module and the filter module.

9. The current sampling device of the flyback equalization circuit of any of claims 1 to 8, further comprising:

the control unit is further configured to synchronously control the sampling timing of the sampling module for at least one of the primary side equalizing current and the secondary side equalizing current of the transformer and the driving signal of the switching tube unit, so that the sampling timing of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer is at least one of on and off of a corresponding switching tube in the switching tube unit in each set equalization period under the condition that the duty ratio and the phase of the driving signal of the switching tube unit are changed;

under the condition that a first switching tube in the switching unit is conducted, the primary side balance current of the flyback balance circuit is the maximum; under the condition that a first switching tube in the switching unit is turned off, the primary side equalizing current of the flyback equalizing circuit is the minimum;

under the condition that a second switching tube in the switching unit is conducted, the secondary side of the flyback equalizing circuit has the maximum equalizing current; and under the condition that a second switching tube in the switching unit is turned off, the secondary side equalizing current of the flyback equalizing circuit is the minimum.

10. The current sampling device of the flyback equalization circuit according to claim 9, wherein the control unit synchronously controls a sampling timing of the sampling module for at least one of the primary side equalization current and the secondary side equalization current of the transformer and the driving signal of the switching tube unit, and the sampling timing comprises:

setting trigger signals of sampling channels of primary side equalizing current and secondary side equalizing current of the transformer, setting driving signals of the first switching tube and the second switching tube, and enabling the trigger signals to be synchronous with the driving signals; the period of the trigger signal is the same as that of the driving signal;

the method for setting the trigger signals of the sampling channels of the primary side equalizing current and the secondary side equalizing current of the transformer comprises the following steps:

triggering a first trigger signal generated by a first control signal on a sampling channel of primary side equalizing current of the transformer;

triggering a second trigger signal generated by a second control signal on a sampling channel of secondary side equalizing current of the transformer;

setting drive signals of the first switching tube and the second switching tube, including:

taking a third control signal as a driving signal of the first switch tube and taking a fourth control signal as a driving signal of the second switch tube;

the control unit, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, the control unit calculates based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube to obtain the effective value of the corresponding equalizing current obtained by the sampling of the corresponding sampling module, and the method comprises the following steps:

in a set equalization period, if the first sampling module samples to obtain two instantaneous values of the primary side equalization current, namely a first instantaneous value of the primary side equalization current and a second instantaneous value of the primary side equalization current, and under the condition that the duty ratio of the first switching tube is a first duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the first instantaneous value of the primary side equalization current and the second instantaneous value of the primary side equalization current and the first duty ratio;

in a set equalization period, if the second sampling module samples two instantaneous values of the primary side equalization current, that is, a third instantaneous value of the primary side equalization current and a fourth instantaneous value of the primary side equalization current, and if the duty ratio of the second switching tube is a second duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the third instantaneous value of the primary side equalization current and the fourth instantaneous value of the primary side equalization current and the second duty ratio.

11. The current sampling device of the flyback equalization circuit of claim 10, wherein the control unit synchronously controls a sampling timing of the sampling module for at least one of the primary side equalization current and the secondary side equalization current of the transformer and the driving signal of the switching tube unit, and further comprises:

if at least one of the effective value of the primary side equalizing current and the effective value of the secondary side equalizing current of the transformer is different from the target value of the equalizing current, adjusting the duty ratio and the phase of the driving signal of the corresponding switching tube, and adjusting the phase of the trigger signal of the corresponding sampling channel in each set equalizing period, so that the first control signal generates a first trigger signal in a preset number of periods before the rising edge and the falling edge of the third control signal in each set equalizing period, and/or the second control signal generates a second trigger signal in a preset number of periods before the rising edge and the falling edge of the fourth control signal in each set equalizing period.

12. A battery equalization system, comprising: a current sampling arrangement for a flyback equalization circuit as in any of claims 1 to 11.

13. A current sampling method of a flyback equalization circuit is characterized in that the flyback equalization circuit comprises the following steps: a transformer and a switching tube unit; the switching tube unit includes: the first switch tube and/or the second switch tube; the first switching tube is arranged on a branch circuit where a primary coil of the transformer is located; the second switching tube is arranged on a branch circuit where the secondary coil of the transformer is located;

the current sampling method of the flyback equalizing circuit comprises the following steps:

acquiring primary side balanced current of a primary side coil of the transformer locked on a branch circuit through a first sampling module;

conditioning the primary side balance current sampled by the first sampling module through a first balance current conditioning unit to obtain an instantaneous value of the primary side balance current sampled by the first sampling module;

acquiring secondary side balance current on a branch where a secondary side coil of the transformer is located through a second sampling module;

conditioning the secondary side equalizing current sampled by the second sampling module through a second equalizing current conditioning unit to obtain an instantaneous value of the secondary side equalizing current sampled by the second sampling module;

through the control unit, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, the calculation is carried out based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube, and the effective value of the corresponding equalizing current obtained by the sampling of the corresponding sampling module is obtained.

14. The method of current sampling for a flyback equalization circuit of claim 13, wherein,

through first balanced current conditioning unit, take care of the primary side balanced current that first sampling module sample obtained, and/or, through second balanced current conditioning unit, take care of the vice limit balanced current that second sampling module sample obtained, include:

and carrying out at least one of amplitude adjustment, isolation, filtering and clamping on the corresponding equalizing current electrified by the corresponding sampling module.

15. The method for sampling current of the flyback equalization circuit of claim 13 or 14, further comprising:

the sampling timing of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer by the sampling module and the driving signal of the switching tube unit are synchronously controlled by the control unit, so that the sampling timing of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer is at least one of on and off of the corresponding switching tube in the switching tube unit in each set equalizing period under the condition that the duty ratio and the phase of the driving signal of the switching tube unit are changed;

under the condition that a first switching tube in the switching unit is conducted, the primary side balance current of the flyback balance circuit is the maximum; under the condition that a first switching tube in the switching unit is turned off, the primary side equalizing current of the flyback equalizing circuit is the minimum;

under the condition that a second switching tube in the switching unit is conducted, the secondary side of the flyback equalizing circuit has the maximum equalizing current; and under the condition that a second switching tube in the switching unit is turned off, the secondary side equalizing current of the flyback equalizing circuit is the minimum.

16. The method of claim 15, wherein the step of synchronously controlling, by the control unit, a sampling timing of the sampling module for at least one of the primary side equalizing current and the secondary side equalizing current of the transformer and the driving signal of the switching tube unit comprises:

setting trigger signals of sampling channels of primary side equalizing current and secondary side equalizing current of the transformer, setting driving signals of the first switching tube and the second switching tube, and enabling the trigger signals to be synchronous with the driving signals; the period of the trigger signal is the same as that of the driving signal;

the method for setting the trigger signals of the sampling channels of the primary side equalizing current and the secondary side equalizing current of the transformer comprises the following steps:

triggering a first trigger signal generated by a first control signal on a sampling channel of primary side equalizing current of the transformer;

triggering a second trigger signal generated by a second control signal on a sampling channel of secondary side equalizing current of the transformer;

setting drive signals of the first switching tube and the second switching tube, including:

taking a third control signal as a driving signal of the first switch tube and taking a fourth control signal as a driving signal of the second switch tube;

through the control unit, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, the effective value of the corresponding equalizing current obtained by the sampling of the corresponding sampling module is obtained based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube through calculation, and the effective value comprises:

in a set equalization period, if the first sampling module samples to obtain two instantaneous values of the primary side equalization current, namely a first instantaneous value of the primary side equalization current and a second instantaneous value of the primary side equalization current, and under the condition that the duty ratio of the first switching tube is a first duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the first instantaneous value of the primary side equalization current and the second instantaneous value of the primary side equalization current and the first duty ratio;

in a set equalization period, if the second sampling module samples two instantaneous values of the primary side equalization current, that is, a third instantaneous value of the primary side equalization current and a fourth instantaneous value of the primary side equalization current, and if the duty ratio of the second switching tube is a second duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the third instantaneous value of the primary side equalization current and the fourth instantaneous value of the primary side equalization current and the second duty ratio.

17. The method of sampling current in a flyback equalization circuit of claim 16, wherein a timing of sampling at least one of a primary side equalization current and a secondary side equalization current of the transformer by the sampling module is synchronously controlled by a control unit with a driving signal of the switching tube unit, further comprising:

if at least one of the effective value of the primary side equalizing current and the effective value of the secondary side equalizing current of the transformer is different from the target value of the equalizing current, adjusting the duty ratio and the phase of the driving signal of the corresponding switching tube, and adjusting the phase of the trigger signal of the corresponding sampling channel in each set equalizing period, so that the first control signal generates a first trigger signal in a preset number of periods before the rising edge and the falling edge of the third control signal in each set equalizing period, and/or the second control signal generates a second trigger signal in a preset number of periods before the rising edge and the falling edge of the fourth control signal in each set equalizing period.

Technical Field

The invention belongs to the technical field of battery management, and particularly relates to a current sampling device and method of a flyback equalizing circuit and a battery equalizing system, in particular to a current sampling circuit and method of a flyback equalizing circuit and a battery equalizing system.

Background

The batteries are often operated in series to improve output capacity, and the series batteries cause a problem in charging and discharging processes due to the inconsistency of the batteries: the high-power battery is fully charged firstly during charging, and the low-power battery is discharged firstly during discharging, so that the battery cannot be fully charged or fully discharged, or risks of overcharging and overdischarging are encountered, and the residual power, namely the charge state of the battery, of the battery needs to be subjected to balanced management during the use process of the battery.

The significance of battery equalization is to realize equalization of the battery state of charge, the battery state of charge cannot be acquired immediately and can only be acquired through estimation, and the accuracy of battery state of charge estimation depends on the accuracy of a battery model and the sampling accuracy of battery voltage, working current and equalization current. The sampling precision of the balance current has important significance on the balance of the charge state of the battery. If the sampling precision of the equalizing current is low, the estimation accuracy of the state of charge of the battery is influenced.

The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.

Disclosure of Invention

The invention aims to provide a current sampling device and method of a flyback equalization circuit and a battery equalization system, which are used for solving the problem that the estimation accuracy of the state of charge of a battery in battery equalization management is influenced if the sampling accuracy of equalization current is low in the estimation of the state of charge of the battery in battery equalization management, and achieve the effects that the sampling accuracy of the equalization current can be improved by arranging an equalization current acquisition circuit suitable for a flyback equalization scheme, and the estimation accuracy of the state of charge of the battery in battery equalization management is further improved.

The invention provides a current sampling device of a flyback equalizing circuit, wherein the flyback equalizing circuit comprises: a transformer and a switching tube unit; the switching tube unit includes: the first switch tube and/or the second switch tube; the first switching tube is arranged on a branch circuit where a primary coil of the transformer is located; the second switching tube is arranged on a branch circuit where the secondary coil of the transformer is located; the current sampling device of the flyback equalizing circuit comprises: a sampling module; the sampling module comprises: a first sampling module and/or a second sampling module; the current sampling device of the flyback equalizing circuit further comprises: the device comprises a balance current conditioning unit and a control unit; the balanced current conditioning unit comprises: the first equalizing current conditioning unit and/or the second equalizing current conditioning unit; the first sampling module is configured to collect a primary side balanced current on a branch where a primary side coil of the transformer is located; the first equalizing current conditioning unit is configured to condition the primary equalizing current sampled by the first sampling module to obtain an instantaneous value of the primary equalizing current sampled by the first sampling module; the second sampling module is configured to collect secondary side equalizing current on a branch where a secondary side coil of the transformer is located; the second equalizing current conditioning unit is configured to condition the secondary equalizing current sampled by the second sampling module to obtain an instantaneous value of the secondary equalizing current sampled by the second sampling module; the control unit is configured to, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, perform calculation based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube to obtain the effective value of the corresponding equalizing current sampled by the corresponding sampling module.

In some embodiments, the first equalizing current conditioning unit is structurally identical to the second equalizing current conditioning unit.

In some embodiments, the first balancing current conditioning unit comprises: a biasing module; the bias module is configured to process the amplitude of the primary side equalization current of the transformer sampled by the first sampling module, so as to adjust the voltage, expressed on the first sampling module, of the primary side equalization current of the transformer sampled by the first sampling module, to be within a set sampling range.

In some embodiments, the biasing module comprises: an adder circuit and a bias circuit; the addition circuit includes: a first operational amplifier and its peripheral circuits; the bias circuit includes: a second operational amplifier and its peripheral circuits; the output end of the first sampling module is input to the non-inverting input end of the first operational amplifier; the inverting input end of the second operational amplifier and the output end of the second operational amplifier are both connected to the non-inverting input end of the first operational amplifier; and the output end of the second operational amplifier can be output to the first AD sampling end of the control unit.

In some embodiments, the first balancing current conditioning unit further comprises: an isolation module; the isolation module is configured to isolate an input end of the isolation module and an output end of the isolation module so as to isolate a current sampling device of the flyback equalization circuit from the flyback equalization circuit.

In some embodiments, the isolation module comprises: the isolation chip, the third operational amplifier and peripheral circuits thereof; under the condition that the first equalizing current conditioning unit comprises an adding circuit and a biasing circuit, the output end of a second operational amplifier in the adding circuit passes through the isolating chip and the third operational amplifier, and then is output to the first AD sampling end of the control unit from the output end of the third operational amplifier.

In some embodiments, the first balancing current conditioning unit further comprises: a filtering module; the filtering module is configured to filter the primary side balanced current of the transformer sampled by the first sampling module; wherein, in the case that the first equalizing current conditioning unit includes at least one of a bias module and an isolation module, the filtering module is disposed at an output end of at least one of the bias module and the isolation module.

In some embodiments, the first balancing current conditioning unit further comprises: a clamping module; the first sampling module samples the primary side equalizing current of the transformer and is embodied in the form of voltage applied to the first sampling module; the clamping module is configured to clamp the voltage on the first sampling module; wherein, in the case that the first equalizing current conditioning unit includes at least one of a bias module, an isolation module and a filter module, the clamping module is disposed at an output end of at least one of the bias module, the isolation module and the filter module.

In some embodiments, further comprising: the control unit is further configured to synchronously control the sampling timing of the sampling module for at least one of the primary side equalizing current and the secondary side equalizing current of the transformer and the driving signal of the switching tube unit, so that the sampling timing of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer is at least one of on and off of a corresponding switching tube in the switching tube unit in each set equalization period under the condition that the duty ratio and the phase of the driving signal of the switching tube unit are changed; under the condition that a first switching tube in the switching unit is conducted, the primary side balance current of the flyback balance circuit is the maximum; under the condition that a first switching tube in the switching unit is turned off, the primary side equalizing current of the flyback equalizing circuit is the minimum; under the condition that a second switching tube in the switching unit is conducted, the secondary side of the flyback equalizing circuit has the maximum equalizing current; and under the condition that a second switching tube in the switching unit is turned off, the secondary side equalizing current of the flyback equalizing circuit is the minimum.

In some embodiments, the controlling unit synchronously controls the sampling timing of the sampling module for at least one of the primary side equalizing current and the secondary side equalizing current of the transformer and the driving signal of the switching tube unit, and includes: setting trigger signals of sampling channels of primary side equalizing current and secondary side equalizing current of the transformer, setting driving signals of the first switching tube and the second switching tube, and enabling the trigger signals to be synchronous with the driving signals; the period of the trigger signal is the same as that of the driving signal; the method for setting the trigger signals of the sampling channels of the primary side equalizing current and the secondary side equalizing current of the transformer comprises the following steps: triggering a first trigger signal generated by a first control signal on a sampling channel of primary side equalizing current of the transformer; triggering a second trigger signal generated by a second control signal on a sampling channel of secondary side equalizing current of the transformer; setting drive signals of the first switching tube and the second switching tube, including: taking a third control signal as a driving signal of the first switch tube and taking a fourth control signal as a driving signal of the second switch tube; the control unit, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, the control unit calculates based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube to obtain the effective value of the corresponding equalizing current obtained by the sampling of the corresponding sampling module, and the method comprises the following steps: in a set equalization period, if the first sampling module samples to obtain two instantaneous values of the primary side equalization current, namely a first instantaneous value of the primary side equalization current and a second instantaneous value of the primary side equalization current, and under the condition that the duty ratio of the first switching tube is a first duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the first instantaneous value of the primary side equalization current and the second instantaneous value of the primary side equalization current and the first duty ratio; in a set equalization period, if the second sampling module samples two instantaneous values of the primary side equalization current, that is, a third instantaneous value of the primary side equalization current and a fourth instantaneous value of the primary side equalization current, and if the duty ratio of the second switching tube is a second duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the third instantaneous value of the primary side equalization current and the fourth instantaneous value of the primary side equalization current and the second duty ratio.

In some embodiments, the control unit synchronously controls sampling timing of at least one of a primary equalizing current and a secondary equalizing current of the transformer by the sampling module and a driving signal of the switching tube unit, and further includes: if at least one of the effective value of the primary side equalizing current and the effective value of the secondary side equalizing current of the transformer is different from the target value of the equalizing current, adjusting the duty ratio and the phase of the driving signal of the corresponding switching tube, and adjusting the phase of the trigger signal of the corresponding sampling channel in each set equalizing period, so that the first control signal generates a first trigger signal in a preset number of periods before the rising edge and the falling edge of the third control signal in each set equalizing period, and/or the second control signal generates a second trigger signal in a preset number of periods before the rising edge and the falling edge of the fourth control signal in each set equalizing period.

In accordance with the above apparatus, a battery equalization system according to another aspect of the present invention includes: the current sampling device of the flyback equalization circuit is described above.

In a matching manner with the battery equalization system, in another aspect of the present invention, a current sampling method for a flyback equalization circuit is provided, where the flyback equalization circuit includes: a transformer and a switching tube unit; the switching tube unit includes: the first switch tube and/or the second switch tube; the first switching tube is arranged on a branch circuit where a primary coil of the transformer is located; the second switching tube is arranged on a branch circuit where the secondary coil of the transformer is located; the current sampling method of the flyback equalizing circuit comprises the following steps: acquiring primary side balance current on a branch where a primary side coil of the transformer is located through a first sampling module; conditioning the primary side balance current sampled by the first sampling module through a first balance current conditioning unit to obtain an instantaneous value of the primary side balance current sampled by the first sampling module; acquiring secondary side balance current on a branch where a secondary side coil of the transformer is located through a second sampling module; conditioning the secondary side equalizing current sampled by the second sampling module through a second equalizing current conditioning unit to obtain an instantaneous value of the secondary side equalizing current sampled by the second sampling module; through the control unit, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, the calculation is carried out based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube, and the effective value of the corresponding equalizing current obtained by the sampling of the corresponding sampling module is obtained.

In some embodiments, the conditioning, by a first equalizing current conditioning unit, the primary equalizing current sampled by the first sampling module, and/or the conditioning, by a second equalizing current conditioning unit, the secondary equalizing current sampled by the second sampling module, includes: and carrying out at least one of amplitude adjustment, isolation, filtering and clamping on the corresponding equalizing current electrified by the corresponding sampling module.

In some embodiments, further comprising: the sampling timing of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer by the sampling module and the driving signal of the switching tube unit are synchronously controlled by the control unit, so that the sampling timing of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer is at least one of on and off of the corresponding switching tube in the switching tube unit in each set equalizing period under the condition that the duty ratio and the phase of the driving signal of the switching tube unit are changed; under the condition that a first switching tube in the switching unit is conducted, the primary side balance current of the flyback balance circuit is the maximum; under the condition that a first switching tube in the switching unit is turned off, the primary side equalizing current of the flyback equalizing circuit is the minimum; under the condition that a second switching tube in the switching unit is conducted, the secondary side of the flyback equalizing circuit has the maximum equalizing current; and under the condition that a second switching tube in the switching unit is turned off, the secondary side equalizing current of the flyback equalizing circuit is the minimum.

In some embodiments, the controlling, by a control unit, synchronously controlling, with a driving signal of the switching tube unit, a sampling timing of at least one of a primary equalizing current and a secondary equalizing current of the transformer by the sampling module, includes: setting trigger signals of sampling channels of primary side equalizing current and secondary side equalizing current of the transformer, setting driving signals of the first switching tube and the second switching tube, and enabling the trigger signals to be synchronous with the driving signals; the period of the trigger signal is the same as that of the driving signal; the method for setting the trigger signals of the sampling channels of the primary side equalizing current and the secondary side equalizing current of the transformer comprises the following steps: triggering a first trigger signal generated by a first control signal on a sampling channel of primary side equalizing current of the transformer; triggering a second trigger signal generated by a second control signal on a sampling channel of secondary side equalizing current of the transformer; setting drive signals of the first switching tube and the second switching tube, including: taking a third control signal as a driving signal of the first switch tube and taking a fourth control signal as a driving signal of the second switch tube; through the control unit, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, the effective value of the corresponding equalizing current obtained by the sampling of the corresponding sampling module is obtained based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube through calculation, and the effective value comprises: in a set equalization period, if the first sampling module samples to obtain two instantaneous values of the primary side equalization current, namely a first instantaneous value of the primary side equalization current and a second instantaneous value of the primary side equalization current, and under the condition that the duty ratio of the first switching tube is a first duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the first instantaneous value of the primary side equalization current and the second instantaneous value of the primary side equalization current and the first duty ratio; in a set equalization period, if the second sampling module samples two instantaneous values of the primary side equalization current, that is, a third instantaneous value of the primary side equalization current and a fourth instantaneous value of the primary side equalization current, and if the duty ratio of the second switching tube is a second duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the third instantaneous value of the primary side equalization current and the fourth instantaneous value of the primary side equalization current and the second duty ratio.

In some embodiments, the controlling unit synchronously controls, with the driving signal of the switching tube unit, a sampling timing of at least one of the primary equalizing current and the secondary equalizing current of the transformer by the sampling module, and further includes: if at least one of the effective value of the primary side equalizing current and the effective value of the secondary side equalizing current of the transformer is different from the target value of the equalizing current, adjusting the duty ratio and the phase of the driving signal of the corresponding switching tube, and adjusting the phase of the trigger signal of the corresponding sampling channel in each set equalizing period, so that the first control signal generates a first trigger signal in a preset number of periods before the rising edge and the falling edge of the third control signal in each set equalizing period, and/or the second control signal generates a second trigger signal in a preset number of periods before the rising edge and the falling edge of the fourth control signal in each set equalizing period.

Therefore, in the scheme of the invention, the balanced current acquisition circuit suitable for the flyback balanced scheme is arranged to synchronously control the balanced current sampling and the balanced MOS driving signal, when the duty ratio and the phase of the balanced MOS driving signal change, the balanced current is always sampled in each balanced period, and the sampling is finished when the two balanced MOS tubes are just switched on and just switched off, and the effective value of the balanced current in the balanced period is obtained by calculating the two sampling values and the duty ratio of the balanced MOS driving signal; therefore, by arranging the balanced current acquisition circuit suitable for the flyback balancing scheme, the sampling precision of the balanced current can be improved, and the estimation accuracy of the state of charge of the battery in the battery balancing management is further improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

Fig. 1 is a schematic structural diagram of a current sampling device of a flyback equalizing circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a topology of an embodiment of a flyback equalization circuit;

fig. 3 is a schematic diagram of a topology of an embodiment of a sampling circuit of a flyback equalization circuit;

FIG. 4 is a timing diagram of an equalizing MOS drive signal and an equalizing current sampling trigger signal;

fig. 5 is a flowchart illustrating a current sampling method of a flyback equalizing circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Equalization refers to transferring charge from battery to achieve almost equal charge (good consistency) across all batteries. A loop needs to be constructed between the batteries and the transfer of charge is represented by the flow of current into and out of the batteries. Difference of the equalizing current from the operating current: the batteries operate in series-parallel connection and are boosted in series. And the parallel capacity expansion is carried out, and a main line is an external interface of the battery system and is called as a bus. For example: when the new energy bus works, the bus of the battery system outputs current outwards, and when the bus is charged, the current flows into the battery system from the bus, namely the working current, and the working current is sampled on the bus. And the balancing is that when the consistency condition among all batteries in the battery system reaches a balancing starting condition, a balancing loop is constructed among balancing target batteries in the battery system, and the current flowing on the balancing loop. The balance current is used for transferring charges to enable the charges among the batteries in the battery system to be consistent, and the balance current is sampled on a balance loop. The balance current is the current flowing between the batteries in the battery system, and the working current is the current flowing between the battery system and the external system.

According to an embodiment of the invention, a current sampling device of a flyback equalizing circuit is provided. Referring to fig. 1, a schematic diagram of an embodiment of the apparatus of the present invention is shown. The flyback equalizing circuit comprises: transformer and switch tube unit. The switching tube unit includes: the first switch tube and/or the second switch tube. The first switching tube is arranged on a branch circuit where a primary coil of the transformer is located. And the second switching tube is arranged on a branch circuit where the secondary coil of the transformer is located. Fig. 2 is a schematic diagram of a topology of an embodiment of a flyback equalization circuit. The transformer T is shown as transformer T1 in fig. 2. The first switch transistor is for example a MOS transistor M1, and the second switch transistor is for example a MOS transistor M2.

The current sampling device of the flyback equalizing circuit comprises: and a sampling module. The sampling module comprises: the first sampling module and/or the second sampling module.

The first sampling module, such as the sampling resistor R1. The second sampling module, such as the sampling resistor R2. As shown in fig. 2, a flyback equalizing circuit is provided between the first battery E1 and the second battery E2. The flyback equalizing circuit comprises: transformer T and equalizing MOS drive circuit. An equalizing MOS drive circuit comprising: a first MOS transistor M1 and a second MOS transistor M2.

In a flyback equalization circuit (i.e., an equalization topology of flyback equalization), sampling resistors, such as resistor R1 and resistor R2, are provided. The synonym terminal of the first coil of the transformer T is connected to the drain of the first MOS transistor M1. The source of the first MOS transistor M1 is connected to one end of the partial device of the first battery E1 through the resistor R1, and one end of the partial device of the first battery E1 is connected to the cathode of the first battery E1. The dotted terminal of the first coil of the transformer T is connected to the other terminal of the partial device of the first battery E1, and the other terminal of the partial device of the first battery E1 is connected to the positive electrode of the first battery E1. The dotted terminal of the second coil of the transformer T is connected to the drain of the second MOS transistor M2. The source of the second MOS transistor M2 is connected to the cathode of the second battery E2 through a resistor R3. The positive electrode of the second battery E2 is connected to the synonym terminal of the second coil of the transformer T. The common terminal of the first MOS transistor M1 and the resistor R1 is a first sampling point Ur 1. The common terminal of the second MOS transistor M1 and the resistor R2 is a first sampling point Ur 2. In the flyback equalizing circuit, a sampling resistor (such as a resistor R1 and a resistor R2) is added to enable equalizing current to be represented as voltage drop on the sampling resistor (such as a resistor R1 and a resistor R2), and an equalizing current instantaneous value is calculated by voltage collected by a sampling circuit of the flyback equalizing circuit.

That is, as shown in fig. 2, sampling resistors, such as a resistor R1 and a resistor R2, are added to the flyback equalization circuit. The resistor R1 and the resistor R2 are respectively located on a primary side and a secondary side of a transformer T in the flyback equalization circuit, the current flowing through the resistor R1 and the resistor R2 is the current flowing into or out of a battery being equalized, that is, the current flowing through the resistor R1 and the resistor R2 is the primary and secondary side equalization current, voltage acquisition is respectively performed on the right side of the resistor R1 and the left side of the resistor R2 in fig. 2, and the acquisition circuit of the flyback equalization circuit is shown in fig. 3, and the acquired voltage is divided by the resistance values of the resistor R1 and the resistor R2 to obtain the instantaneous value of the primary and secondary side equalization current.

Fig. 3 is a schematic diagram of a topology of an embodiment of a sampling circuit of a flyback equalization circuit. In order to reduce heat generation and energy loss, the resistor R1 and the resistor R2 have smaller resistance values. Since the current flowing through the resistor R1 and the resistor R2 has two polarities, the voltage across the resistor R1 and the resistor R2 also has two polarities, and most voltage sampling chips have a positive and certain sampling range, the voltages across the resistor R1 and the resistor R2 need to be biased and scaled, and the voltage across the resistor R1 and the resistor R2 is conditioned by the circuit shown in fig. 3.

The current sampling device of the flyback equalizing circuit further comprises: the device comprises an equalizing current conditioning unit and a control unit. The number of the equalizing current units is the same as the number of the sampling modules, that is, the equalizing current conditioning unit comprises: the first equalizing current conditioning unit and/or the second equalizing current conditioning unit. The control unit, such as a DSP processor. Wherein the content of the first and second substances,

under the condition that the sampling module comprises a first sampling module, the first sampling module is arranged at one connecting end of the first switching tube, which is far away from the primary coil of the transformer, and is configured to collect primary balance current of the primary coil of the transformer locked on a branch.

Under the condition that the sampling module comprises a first sampling module and the balanced current conditioning unit comprises a first balanced current conditioning unit, the first balanced current conditioning unit is arranged at the output end of the first sampling module, such as a first sampling point Ur1, and is configured to condition the primary balanced current sampled by the first sampling module so as to obtain an instantaneous value of the primary balanced current sampled by the first sampling module.

In a case that the sampling module includes a second sampling module, the second sampling module is disposed at a connection end of the second switch tube far away from the secondary coil of the transformer, and is configured to collect the secondary equalizing current on a branch where the secondary coil of the transformer is located.

Under the condition that the sampling module comprises a second sampling module and the balance current conditioning unit comprises a second balance current conditioning unit, the second balance current conditioning unit is arranged at an output end of the second sampling module, such as a second sampling point Ur2 point, and is configured to condition the secondary balance current sampled by the second sampling module so as to obtain an instantaneous value of the secondary balance current sampled by the second sampling module.

The control unit is configured to, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, perform calculation based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube to obtain the effective value of the corresponding equalizing current sampled by the corresponding sampling module.

Specifically, the control unit is configured to, under the condition that a primary side equalizing current of the flyback equalizing circuit is minimum or maximum, if an instantaneous value of the primary side equalizing current is obtained based on the sampling of the first sampling module, perform calculation based on the instantaneous value of the primary side equalizing current and a duty ratio of a driving signal of the first switching tube, and obtain an effective value of the primary side equalizing current obtained by the sampling of the first sampling module.

The control unit is further configured to, under the condition that the secondary side equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the primary side equalizing current is obtained based on the sampling of the second sampling module, perform calculation based on the instantaneous value of the primary side equalizing current and the duty ratio of the driving signal of the second switching tube to obtain the effective value of the secondary side equalizing current obtained by the sampling of the second sampling module.

The scheme of the invention provides an equalizing current acquisition circuit and an equalizing current acquisition method suitable for a flyback equalizing scheme, which can effectively realize equalizing current acquisition in flyback equalization, improve the acquisition precision of equalizing current and further improve the estimation accuracy of the battery charge state in battery equalization management.

According to the scheme, by setting a sampling method for acquiring the effective value of the equalizing current, for example, when the equalizing current is minimum and maximum, the change state of the equalizing current is acquired by sampling, and the effective value of the equalizing current is calculated, so that the estimation accuracy and the equalizing accuracy of the state of charge of the battery can be improved, and the complexity of the equalizing current control method can be reduced. By providing a sampling method for balancing the current effective value, the current sampling frequency requirement is reduced, and the estimation accuracy of the state of charge of the battery is improved.

In the sampling method in the related scheme, the sampling circuit can directly obtain sampling values which are all instantaneous values, and in flyback equalization (including other equalization methods), equalization currents are changed (flyback equalization changes faster), the equalization currents are sampled mainly for protection and battery electric quantity (or battery residual electric quantity or battery charge state) estimation. However, in the related scheme, the effective value in the period of time is directly replaced by the instantaneous value, a large deviation is generated, or the effective value is approached by a mode of sampling and averaging for multiple times in the period of time, but the flyback equalization current changes quickly, and the sampling frequency is difficult to be increased to the degree, so the sampling method in the related scheme is not suitable for flyback equalization for a moment. According to the sampling method in the scheme, the minimum value and the maximum value of the equalizing current are obtained by controlling the sampling phase, the effective value of the equalizing current is obtained according to the minimum value and the maximum value, the sampling precision of the equalizing current (effective value) can be improved, and the sampling frequency is reduced relative to an oversampling averaging mode. The sampling method in the scheme of the invention has a principle difference with an oversampling averaging method, the oversampling averaging is a infinitesimal fitting idea, and the sampling method in the scheme of the invention is a method which uses the flyback equalizing circuit characteristic to linearly change the equalizing current and linearly solve the equalizing current by the minimum value and the maximum value.

In this method, the oversampling averaging is performed by averaging over a plurality of samples, or the plurality of samples are summed every short time (infinitesimal fitting).

The flyback equalization circuit characteristics, namely the change relationship between the battery voltage and the equalization current during equalization, which is determined by a flyback equalization hardware circuit, are different from one circuit to another in a specific formula. For example: if the resistance value of the sampling resistor is small, the most basic flyback equalization topology is adopted, loops at two sides of a flyback converter in the equalization topology are not provided with energy storage capacitors and other branches such as soft switches, an input voltage can be regarded as being added to the converter during equalization, the flyback converter can be regarded as two mutual inductance inductors (influences of leakage inductance, stray inductance capacitors and the like are ignored), the current and voltage relation on the loops is U-L-di/dt + M-di/dt, the equalization current is a straight line with U/L + M as a slope, specific parameters of devices need to be considered actually, and whether a starting auxiliary circuit of the soft switches exists or not is needed. I.e. the relation between voltage and current in the loop and time obtained by specific device parameters and circuits, so that an effective value in the whole time can be obtained by substituting a sampling value at a certain point.

In some embodiments, the first equalizing current conditioning unit is structurally identical to the second equalizing current conditioning unit.

In some embodiments, the first balancing current conditioning unit comprises: and a biasing module.

The bias module is arranged at an output end of the first sampling module for outputting the sampled instantaneous value of the primary side equalizing current of the transformer, and is configured to process the amplitude of the primary side equalizing current of the transformer sampled by the first sampling module so as to adjust the voltage, expressed on the first sampling module, of the primary side equalizing current of the transformer sampled by the first sampling module to a set sampling range.

The range of the equalizing current is set by a development target (the transformer and the MOS are controlled), the equalizing current can be measured by adc only through the expression that the sampling resistor is converted into voltage, and therefore the expressed voltage is determined by the range of the equalizing current and the resistance value of the sampling resistor. The balance current has a range (development target determination), the resistance value of the sampling resistor has a range (power control type selection determination), the two ranges determine the range of the voltage expressed by the balance current on the sampling resistor, and the adc also has a sampling input range, the two ranges are different, the voltage expressed by the balance current on the sampling resistor cannot be directly input into the adc, so that a conditioning circuit is needed.

By arranging the bias circuit, the problem that the voltage on the balanced current sampling resistor has positive and negative polarities which exceed the sampling range can be solved.

In some embodiments, the biasing module comprises: an adder circuit and a bias circuit. The addition circuit includes: an in-phase addition circuit or an inverting addition circuit.

The addition circuit includes: a first operational amplifier and peripheral circuits thereof. The bias circuit includes: a second operational amplifier and peripheral circuits thereof.

And the output end of the first sampling module is input to the non-inverting input end of the first operational amplifier. The inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier are both connected to the non-inverting input terminal of the first operational amplifier. And the output end of the second operational amplifier can be output to the first AD sampling end of the control unit.

In the example shown in fig. 3, the first operational amplifier a1 and its peripheral circuits form a non-inverting addition circuit, and have the effect of voltage scaling. A peripheral circuit of an in-phase addition circuit, comprising: resistance R3, resistance R4, resistance R5 and resistance R6. The sampled voltage (i.e. the voltage representing the instantaneous value of the primary and secondary side equalizing currents) output by the first sampling point Ur1 or the second sampling point Ur2 passes through the resistor R4 and is input to the non-inverting input terminal of the first operational amplifier a 1. And the resistor R3 is arranged between the non-inverting input end of the first operational amplifier A1 and the output end of the second operational amplifier A2 in the bias circuit. The inverting input terminal of the first operational amplifier A1 is grounded to GND _ B via a resistor R6. The inverting input terminal of the first operational amplifier a1 is further connected to the output terminal Uout of the first operational amplifier a1 through a resistor R5. The grounding end of the first operational amplifier A1 is grounded GND _ B, and the battery equalization system of the first operational amplifier A1 is connected with the direct-current battery equalization system VCC.

The Ur1/Ur2 means that for the circuit, the input is Ur1 or Ur2, only one value of Ur1 or Ur2 is input, and the two values need to be adopted, so that two sampling circuits are needed, one input is Ur1, and the other input is Ur 2.

The second operational amplifier a2 and its peripheral circuits constitute a voltage bias circuit as a bias circuit. The resistor R3 and the resistor R4 are configured resistors of a resistor R1 and a summing coefficient of voltage and bias voltage on the resistor R2. The bias circuit solves the problem that the balance current has two polarities of positive and negative caused by the balance of charging and discharging. Peripheral circuitry for a bias circuit, comprising: resistor R7, resistor R8 and capacitor C2. The non-inverting input terminal of the second operational amplifier A2 is grounded to GND _ B through a resistor R7. The capacitor C2 is connected in parallel with the resistor R7. And the direct-current battery equalization system VCC is connected to the non-inverting input end of the second operational amplifier A2 after passing through the resistor R8. The inverting input terminal of the second operational amplifier A2 is connected to the output terminal of the second operational amplifier A2. The output of the second operational amplifier a2 outputs a voltage VP. The battery equalization system end of the second operational amplifier A2 is connected with a direct current battery equalization system VCC. The ground terminal of the second operational amplifier a2 is grounded to GND _ B.

The voltage on the resistor R1 and the resistor R2 is a summation coefficient of the voltage and a bias voltage, the voltage on the resistor R1 and the resistor R2 refers to Ur1 or Ur2 (one of the two), namely the voltage (namely our sampling target) expressed by the primary side equalizing current or the secondary side equalizing current on the sampling resistor, the bias voltage is a fixed voltage and is connected to an adding circuit, namely the voltage is added to the Ur1 or the Ur2 to shift the negative part of the Ur1 or the Ur2 to a positive part, the sampling part is subtracted, and the summation coefficient is that the two parts are multiplied by a coefficient before being added.

In some embodiments, the first balancing current conditioning unit further comprises: an isolation module, such as an isolation circuit.

The isolation module is configured to isolate an input end of the isolation module and an output end of the isolation module so as to isolate a current sampling device of the flyback equalization circuit from the flyback equalization circuit. The stability of the battery equalization system is improved by isolating the sampling circuit from the equalization circuit.

In some embodiments, the isolation module comprises: an isolation chip, and a third operational amplifier and its peripheral circuits. And an isolation chip, such as isolation chip U1.

Under the condition that the first equalizing current conditioning unit comprises an adding circuit and a biasing circuit, the output end of a second operational amplifier in the adding circuit passes through the isolating chip and the third operational amplifier, and then is output to the first AD sampling end of the control unit from the output end of the third operational amplifier.

In the example shown in fig. 3, the isolation chip U1 constitutes an isolation circuit with the third operational amplifier A3 and its peripheral circuits. The isolation circuit solves the problem of strong and weak current interference between the flyback equalization circuit and the sampling circuit. A peripheral circuit of the third operational amplifier a3, comprising: the circuit comprises a resistor R10, a resistor R11, a resistor R12, a resistor R13, a capacitor C3 and a capacitor C4. The output terminal of the first operational amplifier A1 in the non-inverting addition circuit is connected to the 2 nd connection terminal of the isolation chip U1. The 6 th connection terminal of the isolation chip U1 is connected to the inverting input terminal of the third operational amplifier A3 through a resistor R10. The 7 th connection terminal of the isolation chip U1 is connected to the non-inverting input terminal of the third operational amplifier A3 through a resistor R11. The battery equalization system of the third operational amplifier A3 is connected with the DC battery equalization system VCC, and the grounding end of the third operational amplifier A3 is grounded GND _ S. The inverting input terminal of the third operational amplifier A3 is grounded to GND _ S through a resistor R12. The capacitor C3 is connected in parallel with the resistor R12. The third operational amplifier A3 is connected to the output terminal of the third operational amplifier A3 through a resistor R13, and a capacitor C4 is connected in parallel with the resistor R13. The output terminal of the third operational amplifier a3 is connected to the filter circuit.

The isolation chip U1 is an optical coupling chip with model number ACPL-C87H.

In some embodiments, the first balancing current conditioning unit further comprises: a filtering module, such as an RC filter.

The filtering module is configured to filter the primary side balanced current of the transformer sampled by the first sampling module.

Wherein, in the case that the first equalizing current conditioning unit includes at least one of a bias module and an isolation module, the filtering module is disposed at an output end of at least one of the bias module and the isolation module.

In the example shown in fig. 3, the resistor R9 and the capacitor C1 are low-pass filters and serve as filter circuits. The filter circuit can filter high-frequency interference generated by oscillation caused by the switching device. The output end of the third operational amplifier A3 is connected to the clamp circuit through the resistor R9. The resistor R9 is connected to ground GND _ S through a capacitor C1 at a terminal remote from the third operational amplifier A3.

In some embodiments, the first balancing current conditioning unit further comprises: clamping means, such as diode clamps.

The first sampling module samples the primary side equalizing current of the transformer in the form of voltage applied to the first sampling module. The clamping module is configured to clamp a voltage on the first sampling module.

Wherein, in the case that the first equalizing current conditioning unit includes at least one of a bias module, an isolation module and a filter module, the clamping module is disposed at an output end of at least one of the bias module, the isolation module and the filter module. By adding clamping to the sampling voltage, the device is prevented from being burnt out by impulse generated by equalization or by equalization misoperation, and the safety of the battery equalization system is improved.

In the example shown in fig. 3, a diode D1 and a diode D2, which form a clamping circuit, are provided. The output of the clamping circuit is connected to the voltage acquisition chip or the ADC module. The clamp circuit can protect the device and prevent the sampling voltage from exceeding the sampling range. The output terminal of the third operational amplifier a3 is connected to the sampling terminal of the ADC module (e.g., the first sampling terminal ADC1 or the second sampling terminal ADC2) via the resistor R9. The common terminal of the resistor R9 and the capacitor C1 is connected to the cathode of the diode D1 and the anode of the diode D2, and is connected to the sampling terminal of the ADC module (e.g., the first sampling terminal ADC1 or the second sampling terminal ADC 2). The anode of the diode D1 is grounded GND _ S. The cathode of the diode D2 is connected to the dc battery balancing system VCC.

That is, as shown in fig. 3, the sampling circuit of the flyback equalization circuit includes: the circuit comprises a bias circuit, an in-phase addition circuit, an isolation circuit, a filter circuit and a clamping circuit. The bias circuit, the in-phase addition circuit, the isolation circuit, the filter circuit and the clamping circuit are sequentially arranged. And an offset part consisting of the in-phase addition circuit and the offset circuit. A sampling resistor is connected in series in the equalizing loop, the voltage on the sampling resistor is conditioned through an addition circuit, a bias circuit, an isolation circuit, a filter circuit and a clamping circuit, and the conditioned voltage on the sampling resistor is collected through an ADC (analog-to-digital converter) module and is divided by the resistance value of the sampling resistor to obtain the instantaneous value of the equalizing current.

In some schemes, the sampling resistor and the differential amplifier are directly input into the singlechip to carry out balanced current sampling. But the balance current has two polarities without bias and clamp, and exceeds the acquisition range of the ADC of the single chip microcomputer. And the sampling circuit is not isolated from the equalizing circuit, so that the stability of the battery system is influenced.

In other schemes, ampere-hour integration is performed by sampling current multiple times during an equalization period for battery state of charge estimation. But the method is not suitable for a flyback equalization mode, the equalization frequency is high in flyback equalization, current sampling cannot be completed for multiple times in an equalization period, and the sampling frequency is higher. The shorter the sampling width, the lower the sampling accuracy.

According to the scheme, the sampling hardware circuit for acquiring the instantaneous value of the equalizing current in the equalizing circuit is arranged, for example, the sampling hardware circuit is provided with the sampling resistor, the biasing circuit, the adding circuit, the isolating circuit, the filter circuit, the clamping circuit, the ADC module and the like, so that the sampling of the instantaneous value of the equalizing current is realized, the sampling cost can be reduced, the sampling sensitivity is improved, the sampling and equalizing are isolated, and the safety and the stability of a battery equalization management system are improved.

Therefore, in the sampling circuit, the sampling resistor converts the equalizing current into voltage drop, the bias circuit solves the problems of positive and negative polarities of the current caused by equalizing charge and discharge, the isolation circuit solves the problems of coupling between the equalizing circuit and the sampling circuit and mutual interference between strong and weak currents, the clamping circuit protects the ADC or the voltage sampling chip to prevent devices from being burnt, the main improvement is embodied in biasing, isolation and coupling, the scaling effect of other schemes is also realized, and the voltage on the sampling resistor can be reasonably reduced or amplified. Other balanced current acquisition schemes either use current sensors that are expensive or lack the above-described benefits.

In an embodiment of the present invention, the voltage range of the resistors R1 and R2 is plus or minus 200mv, and the ADC module on a controller, such as a DSP (digital signal processor), collects the filtered and clamped voltage signal, and the voltage collection range of the ADC resistor is 0 to 3.3V, so that the amplified bias voltage is set to 1.65V for reasonable utilization of the range, and the equalization current has a certain impulse, so that a certain margin is left for the sampling range, and assuming that the amplification factor is set to be 5 times, the in-phase addition circuit formed by the first operational amplifier a1 has a two-stage scaling effect, i.e. the resistor R3 and the resistor R4 can configure a coefficient for summing the voltage on the resistor R1 and the bias voltage on the resistor R2, and the configuration relationship is U +/Ur 1 (or Ur 2)/(R3R 3+ R8937) + R3638/(VP 3638R 3638), the sum is input to the non-inverting terminal of the first operational amplifier a1, and the second is that the first operational amplifier a1 has negative feedback, and negative feedback resistors such as a resistor R5 and a resistor R6 can configure the ratio of the output of the first operational amplifier a1 to the input of the non-inverting terminal, and the configuration relationship is UOUT ═ (U +) (R5+ R6)/R6. The bias voltage is provided by a bias circuit formed by the second operational amplifier a2, the relationship of the bias circuit is VP VCC R7/(R7+ R8), the product of the two-stage scaling is the total scaling multiple, thereby the specific parameters of the circuit can be determined, and the diode D1 and the diode D2 can be determined as a 3.3V zener diode by the sampling range of the ADC module being 0 to 3.3V. The low-pass filter can design specific parameters according to the switching frequency of the battery equalization system and the equalized switching frequency, and filter high-frequency interference. The sampling circuit in the scheme of the invention can realize the acquisition of the voltage on the resistor R1 and the resistor R2 in the equalizing loop, and compared with the acquisition mode of other voltage sampling chips or current sensors, the circuit has the advantages of simple realization mode, low cost and isolation effect.

The voltage range of the R1 and the R2 is plus or minus 200mv, namely, the voltage represented on the resistor is determined by the development target equalization current range and the resistance value of the resistor, and is the equalization current range set by the development scheme, which is determined by the battery characteristics, so that the battery is suitable for charging and discharging of several C batteries, if the battery is suitable for 2A, some batteries are suitable for 10A, and the equalization current range is set according to the requirements of people and then developed. I is the range of U ═ I × R, I is the development requirement, R is determined by the power control, and the range of voltage I represents on R is determined by I and R.

Instantaneous voltages on the resistor R1 and the resistor R2 can be collected, and the collected instantaneous voltages are divided by the resistances of the resistor R1 and the resistor R2 to obtain the instantaneous balance current. In flyback equalization, the equalization current is changed, and if the sampling frequency is much greater than the equalization frequency, the equalization current can be sampled for many times in the equalization period by adopting an approximation method to obtain more accurate equalization current, but in practice, the equalization frequency determined by the flyback converter, the battery voltage and the equalization current is often higher, and the sampling frequency of the voltage acquisition chip and the ADC is not enough to sample the voltage on the resistor R1 for many times in the equalization period. The scheme of the invention provides a current acquisition method and a strategy based on the flyback equalization circuit characteristic, and can realize that the effective value of the current in the equalization period can be obtained at low sampling frequency.

In some embodiments, further comprising: the control unit is further configured to synchronously control sampling timing of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer by the sampling module and a driving signal of the switching tube unit, so that the sampling timing of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer is at least one of on and off of a corresponding switching tube in the switching tube unit in each set equalization period under the condition that a duty ratio and a phase of the driving signal of the switching tube unit are changed.

And under the condition that a first switching tube in the switching unit is switched on, the primary side equalizing current of the flyback equalizing circuit is the maximum. And under the condition that a first switching tube in the switching unit is turned off, the primary side equalizing current of the flyback equalizing circuit is the minimum.

And under the condition that a second switching tube in the switching unit is conducted, the secondary side of the flyback equalizing circuit has the maximum equalizing current. And under the condition that a second switching tube in the switching unit is turned off, the secondary side equalizing current of the flyback equalizing circuit is the minimum.

According to the scheme, by synchronously controlling the equalizing current sampling (namely the sampling action of the equalizing current) and the equalizing MOS driving signal (namely the driving signal of the equalizing MOS tube), when the duty ratio and the phase of the equalizing MOS driving signal change, the equalizing current is always sampled in each equalizing period, and the sampling is finished when two equalizing MOS tubes (such as the MOS tube M1 and the MOS tube M2) are just switched on and just switched off, and the effective value of the equalizing current in the equalizing period is obtained by calculating the two sampling values and the duty ratio of the equalizing MOS driving signal. By the balanced current sampling method, the balanced current effective value of the period can be obtained in the balanced period, and the method is high in response speed and accurate.

Wherein the equalizing MOS drive signal is actually an active action made in the control, i.e. it is known when it changes. The part belongs to a control strategy of equalization, the equalization is to control the magnitude of equalization current by controlling the on-off time and phase of an equalization MOS, namely, the phase and the period of an MOS driving signal are set according to the magnitude of the equalization current required by development, and the phase and the period of the driving signal are updated by obtaining a feedback value obtained by sampling, so that the change of the duty ratio and the phase of the driving signal is the initiative behavior of a user, and the user knows when the change occurs. For example: and setting a timer, wherein the timer is set to be a fixed period of 20us according to the target value calculation of the equalizing current, when the timing time is up, the driving signal is updated according to the sampling value, the trigger point of the sampling signal is synchronously updated, and the updating is continued when the next period is reached. The timing time is not necessarily fixed but may be varied, but the change of the drive signal is actively set.

In some embodiments, the controlling unit synchronously controls the sampling timing of the sampling module for at least one of the primary side equalizing current and the secondary side equalizing current of the transformer and the driving signal of the switching tube unit, and includes: and setting trigger signals of sampling channels of primary side equalizing current and secondary side equalizing current of the transformer, setting driving signals of the first switching tube and the second switching tube, and enabling the trigger signals and the driving signals to be synchronous. The trigger signal has the same period as the drive signal.

The control unit is used for setting trigger signals of sampling channels of primary side equalizing current and secondary side equalizing current of the transformer, and comprises the following setting conditions:

the first setting scenario: the control unit is specifically further configured to trigger a first trigger signal generated by a first control signal for a sampling channel of a primary side equalization current of the transformer. A first control signal, such as a first PWM1 signal. The first trigger signal is generated by a first control signal, such as a first SOC1 signal generated by a first PWM1 signal.

The second setting scenario: the control unit is specifically further configured to trigger a second trigger signal generated by a second control signal for a sampling channel of the secondary side equalizing current of the transformer. A first control signal, such as a second PWM2 signal. The second trigger signal is generated by a second control signal, such as a second SOC2 signal generated by a second PWM2 signal. SOC is the trigger signal for equalizing current sampling, and SOC1 and SOC2 are the trigger signals for two sampling channels.

The control unit sets the driving signals of the first switch tube and the second switch tube, and comprises: the control unit is specifically configured to use a third control signal as a driving signal of the first switching tube, and use a fourth control signal as a driving signal of the second switching tube. A third control signal, such as a PWM3 signal. A fourth control signal, such as a PWM4 signal.

In flyback equalization, equalization current changes linearly in the processes of switching on the primary side equalization MOS tube and switching off the secondary side equalization MOS tube, or switching on the primary side equalization MOS tube and switching off the secondary side MOS tube.

In the scheme of the invention, two ADC channels in an ADC module are adopted to sample the balance current, a first ADC channel ADC1 is adopted to sample the primary side balance current, and a second ADC channel ADC2 is adopted to sample the secondary side balance current. Wherein, the SOC signal can be generated using a PWM (pulse width modulation) signal to trigger ADC sampling by the ADC sampling module, the first ADC channel ADC1 is triggered by the first SOC1 signal generated by the first PWM1 signal, and the second ADC channel ADC2 is triggered by the second SOC2 signal generated by the second PWM 2.

The control unit, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, the control unit calculates based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube to obtain the effective value of the corresponding equalizing current sampled by the corresponding sampling module, and the control method comprises the following control situations:

the first control scenario: the control unit is specifically configured to, within a set equalization period, if the first sampling module samples two instantaneous values of the primary side equalization current, that is, a first instantaneous value of the primary side equalization current and a second instantaneous value of the primary side equalization current, and if the duty ratio of the first switching tube is a first duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of a sum of the first instantaneous value of the primary side equalization current and the second instantaneous value of the primary side equalization current and the first duty ratio.

The second control scenario: the control unit is specifically configured to, within a set equalization period, obtain instantaneous values of the two primary side equalization currents, that is, a third primary side equalization current instantaneous value and a fourth primary side equalization current instantaneous value, by sampling with the second sampling module, and when the duty ratio of the second switching tube is a second duty ratio, an effective value of the primary side equalization current of the transformer is a product of a half of a sum of the third primary side equalization current instantaneous value and the fourth primary side equalization current instantaneous value and the second duty ratio.

In the scheme of the invention, if the signal for driving the first MOS transistor M1 is PWM3, the signal for driving the second MOS transistor M2 is PWM 4. The PWM1, PWM2 are configured to be synchronized with PWM3, PWM4, and PWM1, PWM2 are configured to have the same period as PWM3, PWM 4. The PWM1 is configured to generate the SOC1 signal N clock cycles before the rising and falling edges of the PWM3, the PWM2 generates the SOC2 signal N clock cycles before the rising and falling edges of the PWM4, and N is the sampling width configured by the ADC1 and the ADC 2.

In an equalization period, two times of SOC1 trigger sampling to obtain two primary side equalization current sampling values I1 and I2, two times of SOC2 trigger ADC2 sampling to obtain two secondary side sampling values I3 and I4, if the duty ratios of PWM3 and PWM4 are Q1 and Q2, the primary side equalization current average value is obtained from (I1+ I2)/2 x Q1, and the effective value of the secondary side equalization current is obtained from (I3+ I4)/2 x Q2.

In some embodiments, the control unit synchronously controls sampling timing of at least one of a primary equalizing current and a secondary equalizing current of the transformer by the sampling module and a driving signal of the switching tube unit, and further includes: the control unit is specifically configured to adjust a duty ratio and a phase of a driving signal of a corresponding switching tube and adjust a phase of a trigger signal of a corresponding sampling channel in each set equalization period if at least one of an effective value of a primary side equalization current and an effective value of a secondary side equalization current of the transformer is different from a target value of the equalization current, so that the first control signal generates a first trigger signal in a set number of periods before a rising edge and a falling edge of a third control signal in each set equalization period, and/or the second control signal generates a second trigger signal in a set number of periods before a rising edge and a falling edge of a fourth control signal in each set equalization period.

FIG. 4 is a timing diagram of an equalizing MOS driving signal and an equalizing current sampling trigger signal. In the scheme of the invention, when the calculated equalization current effective value is not equal to the equalization current target value, the duty ratio and the phase of the PWM3 and the PWM4 are adjusted according to an equalization method. In each cycle, the phases of the SOC1 and the SOC2 generated by the PWM1 and the PWM2 are adjusted, so that the SOC1 is generated by the PWM1 in each cycle N cycles before the rising edge and the falling edge of the PWM3, and the SOC2 is generated by the PWM2 in each cycle N cycles before the rising edge and the falling edge of the PWM4, and fig. 4 illustrates the timing of the equalizing MOS driving signal and the equalizing current sampling trigger signal.

In the scheme of the invention, the effective values of the primary and secondary equalizing currents in each period can be obtained from I1, I2, I3 and I4, so that the effective values and the periods of the equalizing currents can accurately reflect the change of the battery charge and can be used for estimating the state of charge of the battery.

In some embodiments, in addition to using an in-phase addition circuit, an inverted addition circuit may be employed in the sampling circuit. In the sampling method, primary sampling can be omitted from the primary side and the secondary side, sampling is only carried out when the equalizing MOS is switched off, the current of the charged side is 0 when the MOS is switched off by controlling equalization, the current of the other charged side is 0 when the other charged side is switched on, and then the current of the charged side is calculated by the current of the charged side when the charging side is switched off through the turn ratio of the flyback converter.

Through a large number of tests, the technical scheme of the invention is adopted, the balance current sampling and balance MOS driving signals are synchronously controlled by arranging the balance current acquisition circuit suitable for the flyback balance scheme, when the duty ratio and the phase of the balance MOS driving signals are changed, the balance current is always sampled in each balance period, the sampling is completed when the two balance MOS tubes are just switched on and just switched off, and the effective value of the balance current in the balance period is obtained by calculating the two sampling values and the duty ratio of the balance MOS driving signals. Therefore, by arranging the balanced current acquisition circuit suitable for the flyback balancing scheme, the sampling precision of the balanced current can be improved, and the estimation accuracy of the state of charge of the battery in the battery balancing management is further improved.

According to the embodiment of the invention, the battery equalization system corresponding to the current sampling device of the flyback equalization circuit is also provided. The battery equalization system may include: the current sampling device of the flyback equalization circuit is described above.

Since the processing and functions implemented by the battery equalization system of the present embodiment substantially correspond to the embodiments, principles, and examples of the foregoing devices, reference may be made to the related descriptions in the foregoing embodiments without being detailed in the description of the present embodiment.

Through a large number of tests, the technical scheme of the invention is adopted, and the balance current sampling and balance MOS driving signals are synchronously controlled by arranging the balance current acquisition circuit suitable for the flyback balance scheme, when the duty ratio and the phase of the balance MOS driving signals are changed, the balance current is always sampled in each balance period when two balance MOS tubes are just switched on and just switched off, the sampling is completed, the effective value of the balance current in the balance period is obtained by calculating the duty ratio of the two sampling values and the balance MOS driving signals, the instantaneous value sampling of the balance current is realized, the sampling cost can be reduced, the sampling sensitivity is improved, the sampling and balance isolation are realized, and the safety and the stability of the battery balance management system are improved.

According to an embodiment of the present invention, a current sampling method of a flyback equalization circuit corresponding to a battery equalization system is further provided, as shown in fig. 5, which is a schematic flow diagram of an embodiment of the method of the present invention. The flyback equalizing circuit comprises: transformer and switch tube unit. The switching tube unit includes: the first switch tube and/or the second switch tube. The first switching tube is arranged on a branch circuit where a primary coil of the transformer is located. And the second switching tube is arranged on a branch circuit where the secondary coil of the transformer is located. Fig. 2 is a schematic diagram of a topology of an embodiment of a flyback equalization circuit. The transformer T is shown as transformer T1 in fig. 2. The first switch transistor is for example a MOS transistor M1, and the second switch transistor is for example a MOS transistor M2.

The current sampling method of the flyback equalizing circuit comprises the following steps: step S110 to step S150.

In step S110, when the sampling module includes the first sampling module, the first sampling module is disposed at a connection end of the first switching tube, which is far away from the primary coil of the transformer, and is used to collect a primary balanced current of the primary coil of the transformer locked to the branch.

In step S120, when the sampling module includes a first sampling module and the balanced current conditioning unit includes a first balanced current conditioning unit, the first balanced current conditioning unit is disposed at an output end of the first sampling module, such as a first sampling point Ur1, and conditions the primary side balanced current sampled by the first sampling module, so as to obtain an instantaneous value of the primary side balanced current sampled by the first sampling module.

In step S130, in a case that the sampling module includes a second sampling module, the second sampling module is disposed at a connection end of the second switch tube, which is far away from the secondary winding of the transformer, and is used for collecting a secondary balancing current on a branch where the secondary winding of the transformer is located.

In step S140, when the sampling module includes a second sampling module and the balanced current conditioning unit includes a second balanced current conditioning unit, the second balanced current conditioning unit is disposed at an output end of the second sampling module, for example, at a second sampling point Ur2, and conditions the secondary balanced current sampled by the second sampling module, so as to obtain an instantaneous value of the secondary balanced current sampled by the second sampling module.

In step S150, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on the sampling of the corresponding sampling module, the control unit calculates based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube, so as to obtain the effective value of the corresponding equalizing current obtained by the sampling of the corresponding sampling module.

Specifically, by the control unit, under the condition that the primary side equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the primary side equalizing current is obtained based on the sampling of the first sampling module, the calculation is performed based on the instantaneous value of the primary side equalizing current and the duty ratio of the driving signal of the first switching tube, so as to obtain the effective value of the primary side equalizing current obtained by the sampling of the first sampling module. And under the condition that the secondary side equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the primary side equalizing current is obtained based on the sampling of the second sampling module, calculating based on the instantaneous value of the primary side equalizing current and the duty ratio of the driving signal of the second switching tube by the control unit to obtain the effective value of the secondary side equalizing current obtained by the sampling of the second sampling module.

Wherein the sampling module comprises: the first sampling module and/or the second sampling module. A first sampling module, such as a sampling resistor R1. The second sampling module, such as the sampling resistor R2. The number of the equalizing current units is the same as the number of the sampling modules, that is, the equalizing current conditioning unit comprises: the first equalizing current conditioning unit and/or the second equalizing current conditioning unit. The control unit, such as a DSP processor.

As shown in fig. 2, a flyback equalizing circuit is provided between the first battery E1 and the second battery E2. The flyback equalizing circuit comprises: transformer T and equalizing MOS drive circuit. An equalizing MOS drive circuit comprising: a first MOS transistor M1 and a second MOS transistor M2. In a flyback equalization circuit (i.e., an equalization topology of flyback equalization), sampling resistors, such as resistor R1 and resistor R2, are provided. The synonym terminal of the first coil of the transformer T is connected to the drain of the first MOS transistor M1. The source of the first MOS transistor M1 is connected to one end of the partial device of the first battery E1 through the resistor R1, and one end of the partial device of the first battery E1 is connected to the cathode of the first battery E1. The dotted terminal of the first coil of the transformer T is connected to the other terminal of the partial device of the first battery E1, and the other terminal of the partial device of the first battery E1 is connected to the positive electrode of the first battery E1. The dotted terminal of the second coil of the transformer T is connected to the drain of the second MOS transistor M2. The source of the second MOS transistor M2 is connected to the cathode of the second battery E2 through a resistor R3. The positive electrode of the second battery E2 is connected to the synonym terminal of the second coil of the transformer T. The common terminal of the first MOS transistor M1 and the resistor R1 is a first sampling point Ur 1. The common terminal of the second MOS transistor M1 and the resistor R2 is a first sampling point Ur 2. In the flyback equalizing circuit, a sampling resistor (such as a resistor R1 and a resistor R2) is added to enable equalizing current to be represented as voltage drop on the sampling resistor (such as a resistor R1 and a resistor R2), and an equalizing current instantaneous value is calculated by voltage collected by a sampling circuit of the flyback equalizing circuit.

That is, as shown in fig. 2, sampling resistors, such as a resistor R1 and a resistor R2, are added to the flyback equalization circuit. The resistor R1 and the resistor R2 are respectively located on a primary side and a secondary side of a transformer T in the flyback equalization circuit, the current flowing through the resistor R1 and the resistor R2 is the current flowing into or out of a battery being equalized, that is, the current flowing through the resistor R1 and the resistor R2 is the primary and secondary side equalization current, voltage acquisition is respectively performed on the right side of the resistor R1 and the left side of the resistor R2 in fig. 2, and the acquisition circuit of the flyback equalization circuit is shown in fig. 3, and the acquired voltage is divided by the resistance values of the resistor R1 and the resistor R2 to obtain the instantaneous value of the primary and secondary side equalization current.

Fig. 3 is a schematic diagram of a topology of an embodiment of a sampling circuit of a flyback equalization circuit. In order to reduce heat generation and energy loss, the resistor R1 and the resistor R2 have smaller resistance values. Since the current flowing through the resistor R1 and the resistor R2 has two polarities, the voltage across the resistor R1 and the resistor R2 also has two polarities, and most voltage sampling chips have a positive and certain sampling range, the voltages across the resistor R1 and the resistor R2 need to be biased and scaled, and the voltage across the resistor R1 and the resistor R2 is conditioned by the circuit shown in fig. 3.

The scheme of the invention provides an equalizing current acquisition circuit and an equalizing current acquisition method suitable for a flyback equalizing scheme, which can effectively realize equalizing current acquisition in flyback equalization, improve the acquisition precision of equalizing current and further improve the estimation accuracy of the battery charge state in battery equalization management.

According to the scheme, by setting a sampling method for acquiring the effective value of the equalizing current, for example, when the equalizing current is minimum and maximum, the change state of the equalizing current is acquired by sampling, and the effective value of the equalizing current is calculated, so that the estimation accuracy and the equalizing accuracy of the state of charge of the battery can be improved, and the complexity of the equalizing current control method can be reduced. By providing a sampling method for balancing the current effective value, the current sampling frequency requirement is reduced, and the estimation accuracy of the state of charge of the battery is improved.

In the sampling method in the related scheme, the sampling circuit can directly obtain sampling values which are all instantaneous values, and in flyback equalization (including other equalization methods), equalization currents are changed (flyback equalization changes faster), the equalization currents are sampled mainly for protection and battery electric quantity (or battery residual electric quantity or battery charge state) estimation. However, in the related scheme, the effective value in the period of time is directly replaced by the instantaneous value, a large deviation is generated, or the effective value is approached by a mode of sampling and averaging for multiple times in the period of time, but the flyback equalization current changes quickly, and the sampling frequency is difficult to be increased to the degree, so the sampling method in the related scheme is not suitable for flyback equalization for a moment. According to the sampling method in the scheme, the minimum value and the maximum value of the equalizing current are obtained by controlling the sampling phase, the effective value of the equalizing current is obtained according to the minimum value and the maximum value, the sampling precision of the equalizing current (effective value) can be improved, and the sampling frequency is reduced relative to an oversampling averaging mode. The sampling method in the scheme of the invention has a principle difference with an oversampling averaging method, the oversampling averaging is a infinitesimal fitting idea, and the sampling method in the scheme of the invention is a method which uses the flyback equalizing circuit characteristic to linearly change the equalizing current and linearly solve the equalizing current by the minimum value and the maximum value.

In some embodiments, in step S120, the conditioning, by the first equalizing current conditioning unit, the primary equalizing current sampled by the first sampling module, and/or, in step S140, the conditioning, by the second equalizing current conditioning unit, the secondary equalizing current sampled by the second sampling module, includes: and carrying out at least one of amplitude adjustment, isolation, filtering and clamping on the corresponding equalizing current electrified by the corresponding sampling module.

Specifically, the bias module is disposed at an output end of the first sampling module, where the output end outputs an instantaneous value of the sampled primary side equalizing current of the transformer, and is configured to process the amplitude of the primary side equalizing current of the transformer sampled by the first sampling module, so as to adjust a voltage, which is expressed by the primary side equalizing current of the transformer sampled by the first sampling module on the first sampling module, to a set sampling range. By arranging the bias circuit, the problem that the voltage on the balanced current sampling resistor has positive and negative polarities which exceed the sampling range can be solved.

The biasing module, comprising: an adder circuit and a bias circuit. The addition circuit includes: an in-phase addition circuit or an inverting addition circuit.

The isolation module is configured to isolate an input end of the isolation module and an output end of the isolation module so as to isolate a current sampling method of the flyback equalization circuit from the flyback equalization circuit. The stability of the battery equalization system is improved by isolating the sampling circuit from the equalization circuit.

And the filtering module is configured to filter the primary side equalization current of the transformer sampled by the first sampling module.

Wherein, in the case that the first equalizing current conditioning unit includes at least one of a bias module and an isolation module, the filtering module is disposed at an output end of at least one of the bias module and the isolation module.

In the example shown in fig. 3, the resistor R9 and the capacitor C1 are low-pass filters and serve as filter circuits. The filter circuit can filter high-frequency interference generated by oscillation caused by the switching device.

The first sampling module samples the primary side equalizing current of the transformer in the form of voltage applied to the first sampling module. The clamping module is configured to clamp a voltage on the first sampling module.

Wherein, in the case that the first equalizing current conditioning unit includes at least one of a bias module, an isolation module and a filter module, the clamping module is disposed at an output end of at least one of the bias module, the isolation module and the filter module. By adding clamping to the sampling voltage, the device is prevented from being burnt out by impulse generated by equalization or by equalization misoperation, and the safety of the battery equalization system is improved.

In the example shown in fig. 3, a diode D1 and a diode D2, which form a clamping circuit, are provided. The output of the clamping circuit is connected to the voltage acquisition chip or the ADC module. The clamp circuit can protect the device and prevent the sampling voltage from exceeding the sampling range.

That is, as shown in fig. 3, the sampling circuit of the flyback equalization circuit includes: the circuit comprises a bias circuit, an in-phase addition circuit, an isolation circuit, a filter circuit and a clamping circuit. The bias circuit, the in-phase addition circuit, the isolation circuit, the filter circuit and the clamping circuit are sequentially arranged. And an offset part consisting of the in-phase addition circuit and the offset circuit. A sampling resistor is connected in series in the equalizing loop, the voltage on the sampling resistor is conditioned through an addition circuit, a bias circuit, an isolation circuit, a filter circuit and a clamping circuit, and the conditioned voltage on the sampling resistor is collected through an ADC (analog-to-digital converter) module and is divided by the resistance value of the sampling resistor to obtain the instantaneous value of the equalizing current.

In some schemes, the sampling resistor and the differential amplifier are directly input into the singlechip to carry out balanced current sampling. But the balance current has two polarities without bias and clamp, and exceeds the acquisition range of the ADC of the single chip microcomputer. And the sampling circuit is not isolated from the equalizing circuit, so that the stability of the battery system is influenced.

In other schemes, ampere-hour integration is performed by sampling current multiple times during an equalization period for battery state of charge estimation. But the method is not suitable for a flyback equalization mode, the equalization frequency is high in flyback equalization, current sampling cannot be completed for multiple times in an equalization period, and the sampling frequency is higher. The shorter the sampling width, the lower the sampling accuracy.

According to the scheme, the sampling hardware circuit for acquiring the instantaneous value of the equalizing current in the equalizing circuit is arranged, for example, the sampling hardware circuit is provided with the sampling resistor, the biasing circuit, the adding circuit, the isolating circuit, the filter circuit, the clamping circuit, the ADC module and the like, so that the sampling of the instantaneous value of the equalizing current is realized, the sampling cost can be reduced, the sampling sensitivity is improved, the sampling and equalizing are isolated, and the safety and the stability of a battery equalization management system are improved.

Therefore, in the sampling circuit, the sampling resistor converts the equalizing current into voltage drop, the bias circuit solves the problems of positive and negative polarities of the current caused by equalizing charge and discharge, the isolation circuit solves the problems of coupling between the equalizing circuit and the sampling circuit and mutual interference between strong and weak currents, the clamping circuit protects the ADC or the voltage sampling chip to prevent devices from being burnt, the main improvement is embodied in biasing, isolation and coupling, the scaling effect of other schemes is also realized, and the voltage on the sampling resistor can be reasonably reduced or amplified. Other balanced current acquisition schemes either use current sensors that are expensive or lack the above-described benefits.

In an embodiment of the present invention, the equalizing current range set by the sampling scheme of the present invention is determined by the resistances of the resistors R1 and R2, the voltage ranges of the resistors R1 and R2 are plus or minus 200mv, an ADC module on a controller, such as a DSP (digital signal processor), is used to collect the filtered and clamped voltage signal, the voltage collection range of the ADC resistor is 0 to 3.3V, so that the amplified bias voltage is set to be 1.65V for reasonable utilization of the range, a certain margin is left for the sampling range due to a certain impulse of the equalizing current, assuming that the amplification factor is set to be 5 times, the non-inverting adder circuit formed by the first operational amplifier a1 has a two-stage scaling effect, i.e., the resistor R3 and the resistor R4 can configure a coefficient of the sum of the voltage on the resistor R1 and the resistor R2 and the bias voltage, and the configuration relationship of U + ═ Ur1 (or Ur 2)/(+ 25R 3+ R96r 4) + R3638/(3638), the sum is input to the non-inverting terminal of the first operational amplifier a1, and the second is that the first operational amplifier a1 has negative feedback, and negative feedback resistors such as a resistor R5 and a resistor R6 can configure the ratio of the output of the first operational amplifier a1 to the input of the non-inverting terminal, and the configuration relationship is UOUT ═ (U +) (R5+ R6)/R6. The bias voltage is provided by a bias circuit formed by the second operational amplifier a2, the relationship of the bias circuit is VP VCC R7/(R7+ R8), the product of the two-stage scaling is the total scaling multiple, thereby the specific parameters of the circuit can be determined, and the diode D1 and the diode D2 can be determined as a 3.3V zener diode by the sampling range of the ADC module being 0 to 3.3V. The low-pass filter can design specific parameters according to the switching frequency of the battery equalization system and the equalized switching frequency, and filter high-frequency interference. The sampling circuit in the scheme of the invention can realize the acquisition of the voltage on the resistor R1 and the resistor R2 in the equalizing loop, and compared with the acquisition mode of other voltage sampling chips or current sensors, the circuit has the advantages of simple realization mode, low cost and isolation effect.

Instantaneous voltages on the resistor R1 and the resistor R2 can be collected, and the collected instantaneous voltages are divided by the resistances of the resistor R1 and the resistor R2 to obtain the instantaneous balance current. In flyback equalization, the equalization current is changed, and if the sampling frequency is much greater than the equalization frequency, the equalization current can be sampled for many times in the equalization period by adopting an approximation method to obtain more accurate equalization current, but in practice, the equalization frequency determined by the flyback converter, the battery voltage and the equalization current is often higher, and the sampling frequency of the voltage acquisition chip and the ADC is not enough to sample the voltage on the resistor R1 for many times in the equalization period. The scheme of the invention provides a current acquisition method and a strategy based on the flyback equalization circuit characteristic, and can realize that the effective value of the current in the equalization period can be obtained at low sampling frequency.

In some embodiments, further comprising: and synchronously controlling the sampling time of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer and the driving signal of the switching tube unit by the sampling module through the control unit, so that the sampling time of at least one of the primary side equalizing current and the secondary side equalizing current of the transformer is at least one of on and off of the corresponding switching tube in the switching tube unit in each set equalizing period under the condition that the duty ratio and the phase of the driving signal of the switching tube unit are changed.

And under the condition that a first switching tube in the switching unit is switched on, the primary side equalizing current of the flyback equalizing circuit is the maximum. And under the condition that a first switching tube in the switching unit is turned off, the primary side equalizing current of the flyback equalizing circuit is the minimum.

And under the condition that a second switching tube in the switching unit is conducted, the secondary side of the flyback equalizing circuit has the maximum equalizing current. And under the condition that a second switching tube in the switching unit is turned off, the secondary side equalizing current of the flyback equalizing circuit is the minimum.

According to the scheme, by synchronously controlling the equalizing current sampling (namely the sampling action of the equalizing current) and the equalizing MOS driving signal (namely the driving signal of the equalizing MOS tube), when the duty ratio and the phase of the equalizing MOS driving signal change, the equalizing current is always sampled in each equalizing period, and the sampling is finished when two equalizing MOS tubes (such as the MOS tube M1 and the MOS tube M2) are just switched on and just switched off, and the effective value of the equalizing current in the equalizing period is obtained by calculating the two sampling values and the duty ratio of the equalizing MOS driving signal. By the balanced current sampling method, the balanced current effective value of the period can be obtained in the balanced period, and the method is high in response speed and accurate.

In some embodiments, the controlling, by a control unit, synchronously controlling, with a driving signal of the switching tube unit, a sampling timing of at least one of a primary equalizing current and a secondary equalizing current of the transformer by the sampling module, includes: and setting trigger signals of sampling channels of primary side equalizing current and secondary side equalizing current of the transformer, setting driving signals of the first switching tube and the second switching tube, and enabling the trigger signals and the driving signals to be synchronous. The trigger signal has the same period as the drive signal.

The trigger signals of the sampling channels for setting the primary side equalizing current and the secondary side equalizing current of the transformer comprise the following setting conditions:

the first setting scenario: and triggering a sampling channel of the primary side equalizing current of the transformer by a first trigger signal generated by a first control signal. A first control signal, such as a first PWM1 signal. The first trigger signal is generated by a first control signal, such as a first SOC1 signal generated by a first PWM1 signal.

The second setting scenario: and triggering a second trigger signal generated by a second control signal on a sampling channel of the secondary side equalizing current of the transformer. A first control signal, such as a second PWM2 signal. The second trigger signal is generated by a second control signal, such as a second SOC2 signal generated by a second PWM2 signal.

Setting drive signals of the first switching tube and the second switching tube, including: and taking a third control signal as a driving signal of the first switching tube and taking a fourth control signal as a driving signal of the second switching tube. A third control signal, such as a PWM3 signal. A fourth control signal, such as a PWM4 signal.

In flyback equalization, equalization current changes linearly in the processes of switching on the primary side equalization MOS tube and switching off the secondary side equalization MOS tube, or switching on the primary side equalization MOS tube and switching off the secondary side MOS tube.

In the scheme of the invention, two ADC channels in an ADC module are adopted to sample the balance current, a first ADC channel ADC1 is adopted to sample the primary side balance current, and a second ADC channel ADC2 is adopted to sample the secondary side balance current. Wherein, the SOC signal can be generated using a PWM (pulse width modulation) signal to trigger ADC sampling by the ADC sampling module, the first ADC channel ADC1 is triggered by the first SOC1 signal generated by the first PWM1 signal, and the second ADC channel ADC2 is triggered by the second SOC2 signal generated by the second PWM 2.

In some embodiments, by the control unit, under the condition that the corresponding equalizing current of the flyback equalizing circuit is minimum or maximum, if the instantaneous value of the corresponding equalizing current is obtained based on sampling of the corresponding sampling module, the calculation is performed based on the instantaneous value of the corresponding equalizing current and the duty ratio of the driving signal of the corresponding switching tube, so as to obtain the effective value of the corresponding equalizing current obtained by sampling of the corresponding sampling module, where the control includes the following control situations:

the first control scenario: in a set equalization period, if the first sampling module samples to obtain two instantaneous values of the primary side equalization current, namely a first instantaneous value of the primary side equalization current and a second instantaneous value of the primary side equalization current, and under the condition that the duty ratio of the first switching tube is a first duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the first instantaneous value of the primary side equalization current and the second instantaneous value of the primary side equalization current and the first duty ratio.

The second control scenario: in a set equalization period, if the second sampling module samples two instantaneous values of the primary side equalization current, that is, a third instantaneous value of the primary side equalization current and a fourth instantaneous value of the primary side equalization current, and if the duty ratio of the second switching tube is a second duty ratio, the effective value of the primary side equalization current of the transformer is a product of a half of the sum of the third instantaneous value of the primary side equalization current and the fourth instantaneous value of the primary side equalization current and the second duty ratio.

In the scheme of the invention, if the signal for driving the first MOS transistor M1 is PWM3, the signal for driving the second MOS transistor M2 is PWM 4. The PWM1, PWM2 are configured to be synchronized with PWM3, PWM4, and PWM1, PWM2 are configured to have the same period as PWM3, PWM 4. The PWM1 is configured to generate the SOC1 signal N clock cycles before the rising and falling edges of the PWM3, the PWM2 generates the SOC2 signal N clock cycles before the rising and falling edges of the PWM4, and N is the sampling width configured by the ADC1 and the ADC 2.

In an equalization period, two times of SOC1 trigger sampling to obtain two primary side equalization current sampling values I1 and I2, two times of SOC2 trigger ADC2 sampling to obtain two secondary side sampling values I3 and I4, if the duty ratios of PWM3 and PWM4 are Q1 and Q2, the primary side equalization current average value is obtained from (I1+ I2)/2 x Q1, and the effective value of the secondary side equalization current is obtained from (I3+ I4)/2 x Q2.

In some embodiments, the controlling unit synchronously controls, with the driving signal of the switching tube unit, a sampling timing of at least one of the primary equalizing current and the secondary equalizing current of the transformer by the sampling module, and further includes: if at least one of the effective value of the primary side equalizing current and the effective value of the secondary side equalizing current of the transformer is different from the target value of the equalizing current, adjusting the duty ratio and the phase of the driving signal of the corresponding switching tube, and adjusting the phase of the trigger signal of the corresponding sampling channel in each set equalizing period, so that the first control signal generates a first trigger signal in a preset number of periods before the rising edge and the falling edge of the third control signal in each set equalizing period, and/or the second control signal generates a second trigger signal in a preset number of periods before the rising edge and the falling edge of the fourth control signal in each set equalizing period.

FIG. 4 is a timing diagram of an equalizing MOS driving signal and an equalizing current sampling trigger signal. In the scheme of the invention, when the calculated equalization current effective value is not equal to the equalization current target value, the duty ratio and the phase of the PWM3 and the PWM4 are adjusted according to an equalization method. In each cycle, the phases of the SOC1 and the SOC2 generated by the PWM1 and the PWM2 are adjusted, so that the SOC1 is generated by the PWM1 in each cycle N cycles before the rising edge and the falling edge of the PWM3, and the SOC2 is generated by the PWM2 in each cycle N cycles before the rising edge and the falling edge of the PWM4, and fig. 4 illustrates the timing of the equalizing MOS driving signal and the equalizing current sampling trigger signal.

In the scheme of the invention, the effective values of the primary and secondary equalizing currents in each period can be obtained from I1, I2, I3 and I4, so that the effective values and the periods of the equalizing currents can accurately reflect the change of the battery charge and can be used for estimating the state of charge of the battery.

In some embodiments, in addition to using an in-phase addition circuit, an inverted addition circuit may be employed in the sampling circuit. In the sampling method, primary sampling can be omitted from the primary side and the secondary side, sampling is only carried out when the equalizing MOS is switched off, the current of the charged side is 0 when the MOS is switched off by controlling equalization, the current of the other charged side is 0 when the other charged side is switched on, and then the current of the charged side is calculated by the current of the charged side when the charging side is switched off through the turn ratio of the flyback converter.

Since the processing and functions implemented by the method of the present embodiment substantially correspond to the embodiments, principles, and examples of the battery balancing system, reference may be made to the related descriptions in the foregoing embodiments without being detailed in the description of the present embodiment.

Through a large number of tests, the technical scheme of the embodiment is adopted, the balance current sampling and balance MOS driving signals are synchronously controlled by arranging the balance current acquisition circuit suitable for the flyback balance scheme, when the duty ratio and the phase of the balance MOS driving signals are changed, the balance current is always sampled in each balance period, the sampling is completed when two balance MOS tubes are just switched on and just switched off, the effective value of the balance current in the balance period is obtained by calculating the two sampling values and the duty ratio of the balance MOS driving signals, the current sampling frequency requirement is reduced, and the estimation accuracy of the battery charge state is improved.

In summary, it is readily understood by those skilled in the art that the advantageous modes described above can be freely combined and superimposed without conflict.

The above description is only an example of the present invention, and is not intended to limit the present invention, and it is obvious to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.