阅读说明：本技术 一种时间校正系统和方法 (Time correction system and method ) 是由 范凤军 圣冬冬 肖寅枫 王茜茜 张威 于 2021-09-24 设计创作，主要内容包括：本发明提供了一种时间校正系统,包括客户端和参考端：客户端包括时间频率源、相位微调器、本地GNSS时间频率传递装置和驯服控制系统；时间频率源将待校准时间输入通过相位微调器,相位微调器处理后形成1PPS信号,并将1PPS信号输入到本地GNSS时间频率传递装置；本地GNSS时间频率传递装置将通过天线接收的卫星信号和1PPS信号进行比对,生成单站时差数据,并输入到驯服控制系统；参考端包括参考GNSS时间频率传递装置和UTC装置；UTC装置向参考GNSS时间频率装置提供参考时间；参考GNSS时间频率传递装置将通过天线接收的卫星信号和参考时间进行比对,生成时差参考数据,并上传至FTP服务器进行存储。(The invention provides a time correction system, which comprises a client and a reference end: the client comprises a time frequency source, a phase trimmer, a local GNSS time frequency transfer device and a taming control system; the time frequency source inputs time to be calibrated through the phase trimmer, the phase trimmer processes the time to form a 1PPS signal, and the 1PPS signal is input to the local GNSS time frequency transfer device; the local GNSS time frequency transfer device compares the satellite signals received by the antenna with the 1PPS signals to generate single station time difference data, and inputs the single station time difference data to the taming control system; the reference end comprises a reference GNSS time frequency transfer device and a UTC device; the UTC device provides reference time to the reference GNSS time frequency device; the reference GNSS time frequency transfer device compares the satellite signals received by the antenna with the reference time to generate time difference reference data, and uploads the time difference reference data to the FTP server for storage.)

1. A time correction system, characterized in that the time correction system comprises a client and a reference end:

the client comprises a time frequency source, a phase trimmer, a local GNSS time frequency transfer device and a taming control system; the time frequency source inputs time to be calibrated through the phase trimmer, the phase trimmer processes the time to form a 1PPS signal, and the 1PPS signal is input to the local GNSS time frequency transfer device; the local GNSS time frequency transfer device compares the satellite signal received by the first antenna with the 1PPS signal to generate single station time difference data, and inputs the single station time difference data to the taming control system;

the reference end comprises a reference GNSS time frequency transfer device and a UTC device; the UTC device provides reference time to the reference GNSS time frequency device; the reference GNSS time frequency transfer device compares the satellite signals received by the second antenna with reference time to generate time difference reference data, and uploads the time difference reference data to the FTP server for storage;

the taming control system downloads time difference reference data stored on the FTP server through a network, processes the time difference reference data with single station time difference data generated by a local GNSS time frequency transfer device, acquires an adjustment amount, adjusts the phase and frequency of a phase trimmer through a serial port, enables the time difference measurement value between the time to be calibrated of a time frequency source and the reference time provided by the UTC device to reach a set value, and completes time correction;

the taming control system comprises a time interval measuring module, an FPGA, a digital-to-analog conversion module and a single chip microcomputer; the time interval module receives the time difference reference data and the single-station time difference data, compares the time difference reference data with the single-station time difference data, sends the time difference data to the FPGA, receives and processes the data in the FPGA, obtains the adjustment quantity from the FPGA by the singlechip, and sends the adjustment quantity to the phase trimmer after passing through the digital-to-analog conversion module.

2. The time correction system of claim 1, wherein said disciplined control system further comprises a power module for powering the FPGA and the single-chip microcomputer; the power supply module adopts a TPS54310 chip, the input voltage is 5V, and the output voltage is adjusted between 0.9V and 3.3V; the power module specifically comprises the following components:

one ends of decoupling capacitors C1 and C3 are grounded in parallel, and the other ends of the decoupling capacitors are connected with a VIN port of a TPS54310 chip; one end of the resistor R1 is connected with the RT port of the TPS54310 chip, and the other end is grounded and used for setting the switching frequency of the module; one end of an inductor L1 is connected with a PH port of the TPS54310 chip, and the other end of the inductor L1 is connected with a capacitor C2 and then grounded and used for filtering output voltage; one end of the capacitor C4 is connected with a VBIAS port of the TPS54310 chip, and the other end of the capacitor C4 is grounded; one end of the capacitor C6 is connected with an SS/ENA port of the TPS54310 chip, and the other end is grounded; the capacitor C5 is connected between the PH port and the BOOT port of the TPS54310 chip; resistors R2, R3, R5, capacitors C7, C8 and C9 form a loop compensation circuit, wherein a capacitor C8 is connected in parallel with the resistor R5 and the capacitor C9 and is connected between a VSENSE port and a COMP port of a TPS54310 chip, and a resistor R2 is connected in parallel with the capacitor C7 and the resistor R3 and is connected between the VSENSE port and a PH port of the TPS54310 chip; the resistor R4 and the resistor R2 are used as voltage dividing resistors to control the output voltage of the power supply module, and the voltage dividing resistors are specifically as follows:

wherein V_outIs the output voltage.

3. The time correction system of claim 2, wherein the FPGA power supply includes a core power supply and an I/O power supply, the core power supply voltage being less than the I/O power supply voltage; the diode is connected in series between the core power supply and the I/O power supply, wherein the anode of the diode is connected with the I/O power supply, the cathode of the diode is connected with the core power supply, and the power-on time of the core power supply is ensured to be not later than that of the I/O power supply through the tube voltage drop generated when the diode is conducted in the forward direction.

4. The time correction system according to claim 1, wherein the phase fine-tuning unit is connected with a visualization system, the time correction result is displayed through the visualization system, the visualization system comprises a data source adaptation system, a database, a real-time calculation frame and a configuration information template, and third-party data leads the data into the database in the system through the data source adaptation system, and generates a corresponding data model at the same time; after data are imported into a database and a data model is generated, the real-time computing frame automatically outputs corresponding chart information according to the generated data model and in combination with a configuration information template; the database is a MongoDB database.

5. A time correction method, characterized by comprising the steps of:

the time frequency source inputs time to be calibrated through the phase trimmer, the phase trimmer processes the time to form a 1PPS signal, and the 1PPS signal is input to the local GNSS time frequency transfer device; the local GNSS time frequency transfer device compares the satellite signal received by the first antenna with the 1PPS signal to generate single station time difference data, and inputs the single station time difference data to the taming control system;

the UTC device provides reference time to the reference GNSS time frequency device; the reference GNSS time frequency transfer device compares the satellite signals received by the second antenna with reference time to generate time difference reference data, and uploads the time difference reference data to the FTP server for storage;

the taming control system downloads time difference reference data stored on the FTP server through a network, processes the time difference reference data with single station time difference data generated by a local GNSS time frequency transfer device, acquires an adjustment amount, adjusts the phase and frequency of a phase trimmer through a serial port, enables the time difference measurement value between the time to be calibrated of a time frequency source and the reference time provided by the UTC device to reach a set value, and completes time correction;

the taming control system comprises a time interval measuring module, an FPGA, a digital-to-analog conversion module and a single chip microcomputer; the time interval module receives the time difference reference data and the single-station time difference data, compares the time difference reference data with the single-station time difference data, sends the time difference data to the FPGA, receives and processes the data in the FPGA, obtains the adjustment quantity from the FPGA by the singlechip, and sends the adjustment quantity to the phase trimmer after passing through the digital-to-analog conversion module.

6. The method for time correction according to claim 5, wherein the disciplined control system disciplines the time, comprising the steps of:

step S1, setting 1 initial adjustment judgment threshold in the FPGA, receiving time difference data by the FPGA, and performing integer period adjustment on an internal counter by the FPGA when the time difference is greater than the initial adjustment judgment threshold;

step S2, finding out the point with zero time difference data through zero point search, and entering into a preliminary frequency locking state;

step S3, removing wild value of error point in the data received by the time interval module, setting flag bit, and judging whether the variation of time difference data is larger than 1 set value, if so, removing the second time difference data and replacing the second time difference data;

step S4, processing the error data and entering into algorithm frequency locking to obtain real adjustment quantity; in the locking mode, if the external pulse per second is lost, the taming and clocking control system is in an unlocking state; at the moment, the locking flag position is in a low position; when the external reference second pulse is recovered, the time taming process will return to the zero point search process and enter the locking process again.

7. The method for time correction according to claim 5, wherein the time frequency source is from a client hydrogen clock, the UTC device is from a reference hydrogen clock, and the relative deviation between the client hydrogen clock and the reference hydrogen clock is calculated by the time difference measurement, and the method comprises the following steps:

calculating the time difference measurement values of all tracking sections observed every day, calculating the fitting value of 00:00:00 of UTC time of the day by least square normal linear fitting to obtain the time difference fitting value of the ith day zero hour, and using delta T_iExpressed in units of ns;

if n time difference fitting values are obtained by measuring n days, the n time difference fitting values delta T are obtained_iFitting according to least square normative to obtain a fitting slope a₁The calculation formula is as follows:

wherein, t_iThe time of the ith day is the time of day,n balance mean time;

is the average value of the time difference of n days;

from a to a₁Obtaining the relative deviation between the client hydrogen clock and the reference end hydrogen clock as follows:

where Δ f is the frequency offset, f is the frequency nominal value, τ is the sampling time interval, and τ is 86400.

8. The method according to claim 5, wherein kalman filtering is required for the satellite signals received by the local GNSS time-frequency transfer device and the satellite signals received by the reference GNSS time-frequency transfer device, and the method comprises the following steps:

establishing a Kalman filtering model as follows:

wherein a (t) is an acceleration value with respect to time t, α is a preset constant,is the mean of the current acceleration, w (t) is a noise function of time t, in filteringUsing current predicted value of accelerationInstead, k is the current state and k +1 is the next state, then the equation of state is obtained:

wherein x is a state prediction value;

discretizing to obtain a discrete state equation as follows:

wherein X (k +1) is a next state prediction value, X (k) is a current state prediction value, phi (k +1, k) is a state transition matrix, U (k) is an input matrix, and W (k) is a noise matrix;

handleBy usingInstead of deriving

X(k+1)＝Φ₁(k+1,k)X(k)+W(k)

Wherein T is an output value;

when α tends to 0, the covariance matrix q (k) of the noise matrix w (k) is reduced to:

whereinWherein a is_maxThe acceleration is the maximum acceleration, and the acceleration is the maximum acceleration,is an acceleration estimate.

9. A memory storing a computer program, the computer program performing the steps of:

the time frequency source inputs time to be calibrated through the phase trimmer, the phase trimmer processes the time to form a 1PPS signal, and the 1PPS signal is input to the local GNSS time frequency transfer device; the local GNSS time frequency transfer device compares the satellite signal received by the first antenna with the 1PPS signal to generate single station time difference data, and inputs the single station time difference data to the taming control system;

the UTC device provides reference time to the reference GNSS time frequency device; the reference GNSS time frequency transfer device compares the satellite signals received by the second antenna with reference time to generate time difference reference data, and uploads the time difference reference data to the FTP server for storage;

the taming control system downloads time difference reference data stored on the FTP server through a network, processes the time difference reference data with single station time difference data generated by a local GNSS time frequency transfer device, acquires an adjustment amount, adjusts the phase and frequency of a phase trimmer through a serial port, enables the time difference measurement value between the time to be calibrated of a time frequency source and the reference time provided by the UTC device to reach a set value, and completes time correction;

the taming control system comprises a time interval measuring module, an FPGA, a digital-to-analog conversion module and a single chip microcomputer; the time interval module receives the time difference reference data and the single-station time difference data, compares the time difference reference data with the single-station time difference data, sends the time difference data to the FPGA, receives and processes the data in the FPGA, obtains the adjustment quantity from the FPGA by the singlechip, and sends the adjustment quantity to the phase trimmer after passing through the digital-to-analog conversion module.

Technical Field

The invention belongs to the technical field of time frequency correction, and particularly relates to a time correction system and a time correction method.

Background

The national defense time frequency quantity transmission networking mainly comprises a national defense time frequency center and a plurality of secondary station time frequency nodes, wherein the time frequency center comprises a center time frequency standard system, a GNSS time transmission receiver and a time information processing and distributing server, and the time frequency nodes comprise a secondary time frequency standard system and a GNSS time transmission receiver. And the time transfer receiver measures the difference between the local time of the center and each time-frequency node and the GNSS standard time, and then each time-frequency node uploads comparison data through the time information processing and distributing server. The server sorts and analyzes the data, calculates and uploads the comparison data, and releases the time difference and frequency difference information of each node after the comparison data is completed to form an integrated quantity transmission service network which is used as one of research units, and a time-frequency laboratory mainly works to cooperate with a center to carry out related technical research of time parameters.

In recent years, the maintenance level of the Universal Time Coordinated (UTC) of the time reference of China has been greatly improved, and the comprehensive strength is in the front of the world. With the development of technology, in the application of standard time frequency signals, such as: the method has the advantages that higher requirements for short-term stability of a reference source are provided for measurement of a high-stability crystal oscillator, a rubidium clock and the like, calibration of a receiver, high-precision time real-time synchronization of a subnanosecond level and the like, and therefore the method has important application value for improving the short-term stability of UTC.

As Global Navigation Satellite System (GNSS) technology has matured, terminals receiving GNSS satellite signals have become increasingly diverse and mass-produced. Besides the positioning function, the satellite navigation system also has important timing capability, and the positioning accuracy depends on the system timing accuracy. In order to ensure that a time system terminal for receiving satellite navigation signals outputs accurate and reliable time and frequency information, a GNSS high-precision time and frequency detection system needs to be established to perform function and performance detection on the time and frequency signals output by the terminal. Since time-frequency is one of legal measurement parameters specified by the international bureau of metrology (BIPM), a time-frequency detection system needs to trace to an upper-level time-frequency source, i.e., a GNSS time reference, and perform uncertainty evaluation on the result of tracing.

Conventional time-frequency metering establishes a traceback link primarily through frequency traceback. Time tracing is usually realized by a method of indirectly receiving satellite signals, the time tracing method is limited by environmental conditions, space wireless signals are easily subjected to electromagnetic interference, and stability and reliability are low. In addition, satellite receiving equipment errors are introduced and the accuracy is limited. With the development of satellite navigation technology and system construction, a time frequency correction system is constructed on the GNSS time reference in parallel, and direct source tracing from a time frequency detection system to the time reference can be realized.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a time correction system and method, which solves the problem of low correction accuracy of the prior time correction system.

The technical scheme adopted by the invention is as follows:

the invention provides a time correction system, which comprises a client and a reference end:

the client comprises a time frequency source, a phase trimmer, a local GNSS time frequency transfer device and a taming control system; the time frequency source inputs time to be calibrated through a phase trimmer, the phase trimmer processes the time to form a 1PPS signal (pulse per second signal), and the 1PPS signal is input to a local GNSS time frequency transfer device; the local GNSS time frequency transfer device compares the satellite signal received by the first antenna with the 1PPS signal to generate single station time difference data, and inputs the single station time difference data to the taming control system;

the reference end comprises a reference GNSS time frequency transfer device and a UTC device; the UTC device provides reference time to the reference GNSS time frequency device; the reference GNSS time frequency transfer device compares the satellite signals received by the second antenna with reference time to generate time difference reference data, and uploads the time difference reference data to the FTP server for storage;

the taming control system downloads time difference reference data stored on the FTP server through a network, processes the time difference reference data with single station time difference data generated by a local GNSS time frequency transfer device, acquires an adjustment amount, adjusts the phase and frequency of a phase trimmer through a serial port, enables the time difference measurement value between the time to be calibrated of a time frequency source and the reference time provided by the UTC device to reach a set value, and completes time correction;

the taming control system comprises a time interval measuring module, an FPGA, a digital-to-analog conversion module and a single chip microcomputer; the time interval module receives the time difference reference data and the single-station time difference data, compares the time difference reference data with the single-station time difference data, sends the time difference data to the FPGA, receives and processes the data in the FPGA, obtains the adjustment quantity from the FPGA by the singlechip, and sends the adjustment quantity to the phase trimmer after passing through the digital-to-analog conversion module.

Furthermore, the taming control system also comprises a power supply module which is used for supplying power to the FPGA and the singlechip; the power supply module adopts a TPS54310 chip, the input voltage is 5V, and the output voltage is adjusted between 0.9V and 3.3V; the power module specifically comprises the following components:

one ends of decoupling capacitors C1 and C3 are grounded in parallel, and the other ends of the decoupling capacitors are connected with a VIN port of a TPS54310 chip; one end of the resistor R1 is connected with the RT port of the TPS54310 chip, and the other end is grounded and used for setting the switching frequency of the module; one end of an inductor L1 is connected with a PH port of the TPS54310 chip, and the other end of the inductor L1 is connected with a capacitor C2 and then grounded and used for filtering output voltage; one end of the capacitor C4 is connected with a VBIAS port of the TPS54310 chip, and the other end of the capacitor C4 is grounded; one end of the capacitor C6 is connected with an SS/ENA port of the TPS54310 chip, and the other end is grounded; the capacitor C5 is connected between the PH port and the BOOT port of the TPS54310 chip; resistors R2, R3, R5, capacitors C7, C8 and C9 form a loop compensation circuit, wherein a capacitor C8 is connected in parallel with the resistor R5 and the capacitor C9 and is connected between a VSENSE port and a COMP port of a TPS54310 chip, and a resistor R2 is connected in parallel with the capacitor C7 and the resistor R3 and is connected between the VSENSE port and a PH port of the TPS54310 chip; the resistor R4 and the resistor R2 are used as voltage dividing resistors to control the output voltage of the power supply module, and the voltage dividing resistors are specifically as follows:

wherein V_outIs the output voltage.

Furthermore, the FPGA power supply comprises a core power supply and an I/O power supply, and the voltage of the core power supply is less than that of the I/O power supply; the diode is connected in series between the core power supply and the I/O power supply, wherein the anode of the diode is connected with the I/O power supply, the cathode of the diode is connected with the core power supply, and the power-on time of the core power supply is ensured to be not later than that of the I/O power supply through the tube voltage drop generated when the diode is conducted in the forward direction.

Furthermore, the phase trimmer is connected with a visualization system, the time correction result is displayed through the visualization system, the visualization system comprises a data source adaptation system, a database, a real-time calculation frame and a configuration information template, and third-party data leads the data into the database in the system through the data source adaptation system and generates a corresponding data model at the same time; after data are imported into a database and a data model is generated, the real-time computing frame automatically outputs corresponding chart information according to the generated data model and in combination with a configuration information template; the database is a MongoDB database.

The invention also provides a time correction method, which comprises the following steps:

the time frequency source inputs time to be calibrated through the phase trimmer, the phase trimmer processes the time to form a 1PPS signal, and the 1PPS signal is input to the local GNSS time frequency transfer device; the local GNSS time frequency transfer device compares the satellite signal received by the first antenna with the 1PPS signal to generate single station time difference data, and inputs the single station time difference data to the taming control system;

the UTC device provides reference time to the reference GNSS time frequency device; the reference GNSS time frequency transfer device compares the satellite signals received by the second antenna with reference time to generate time difference reference data, and uploads the time difference reference data to the FTP server for storage;

the taming control system downloads time difference reference data stored on the FTP server through a network, processes the time difference reference data with single station time difference data generated by a local GNSS time frequency transfer device, acquires an adjustment amount, adjusts the phase and frequency of a phase trimmer through a serial port, enables the time difference measurement value between the time to be calibrated of a time frequency source and the reference time provided by the UTC device to reach a set value, and completes time correction;

the taming control system comprises a time interval measuring module, an FPGA, a digital-to-analog conversion module and a single chip microcomputer; the time interval module receives the time difference reference data and the single-station time difference data, compares the time difference reference data with the single-station time difference data, sends the time difference data to the FPGA, receives and processes the data in the FPGA, obtains the adjustment quantity from the FPGA by the singlechip, and sends the adjustment quantity to the phase trimmer after passing through the digital-to-analog conversion module.

Further, the taming control system is used for taming the time and specifically comprises the following steps:

step S1, setting 1 initial adjustment judgment threshold in the FPGA, receiving time difference data by the FPGA, and performing integer period adjustment on an internal counter by the FPGA when the time difference is greater than the initial adjustment judgment threshold;

step S2, finding out the point with zero time difference data through zero point search, and entering into a preliminary frequency locking state;

step S3, removing wild value of error point in the data received by the time interval module, setting flag bit, and judging whether the variation of time difference data is larger than 1 set value, if so, removing the second time difference data and replacing the second time difference data;

step S4, processing the error data and entering into algorithm frequency locking to obtain real adjustment quantity; in the locking mode, if the external pulse per second is lost, the taming and clocking control system is in an unlocking state; at the moment, the locking flag position is in a low position; when the external reference second pulse is recovered, the time taming process will return to the zero point search process and enter the locking process again.

Further, the time frequency source is from a client hydrogen clock, the UTC device is from a reference end hydrogen clock, and the relative deviation between the client hydrogen clock and the reference end hydrogen clock is calculated through the time difference measurement value, specifically comprising the following steps:

calculating the time difference measurement values of all tracking sections observed every day, calculating the fitting value of 00:00:00 of UTC time of the day by least square normal linear fitting to obtain the time difference fitting value of the ith day zero hour, and using delta T_iExpressed in units of ns;

if n time difference fitting values are obtained by measuring n days, the n time difference fitting values delta T are obtained_iFitting according to least square normative to obtain a fitting slope a₁The calculation formula is as follows:

t_ithe time of the ith day is the time of day,n balance mean time;

wherein the content of the first and second substances,is the average value of the time difference of n days;

from a to a₁Obtaining the relative deviation between the client hydrogen clock and the reference end hydrogen clock as follows:

where Δ f is the frequency offset, f is the frequency nominal value, τ is the sampling time interval, and τ is 86400.

Further, kalman filtering is required to be performed on the satellite signal received by the local GNSS time-frequency transfer device and the satellite signal received by the reference GNSS time-frequency transfer device, and the method specifically includes the following steps:

establishing a Kalman filtering model as follows:

wherein a (t) is an acceleration value with respect to time t, α is a preset constant,is the mean of the current acceleration, w (t) is a noise function of time t, in filteringUsing current predicted value of accelerationInstead, k is the current state and k +1 is the next state, then the equation of state is obtained:

wherein x is a state prediction value;

discretizing to obtain a discrete state equation as follows:

wherein X (k +1) is a next state prediction value, X (k) is a current state prediction value, phi (k +1, k) is a state transition matrix, U (k) is an input matrix, and W (k) is a noise matrix;

handleBy usingInstead of deriving

X(k+1)＝Φ₁(k+1,k)X(k)+W(k)

Wherein T is an output value;

when α tends to 0, the covariance matrix q (k) of the noise matrix w (k) is reduced to:

whereinWherein a is_maxThe acceleration is the maximum acceleration, and the acceleration is the maximum acceleration,is an acceleration estimate.

The invention also provides a memory, in which a computer program is stored, characterized in that the computer program performs the steps of:

the time frequency source inputs time to be calibrated through the phase trimmer, the phase trimmer processes the time to form a 1PPS signal, and the 1PPS signal is input to the local GNSS time frequency transfer device; the local GNSS time frequency transfer device compares the satellite signal received by the first antenna with the 1PPS signal to generate single station time difference data, and inputs the single station time difference data to the taming control system;

the UTC device provides reference time to the reference GNSS time frequency device; the reference GNSS time frequency transfer device compares the satellite signals received by the second antenna with reference time to generate time difference reference data, and uploads the time difference reference data to the FTP server for storage;

the taming control system downloads time difference reference data stored on the FTP server through a network, processes the time difference reference data with single station time difference data generated by a local GNSS time frequency transfer device, acquires an adjustment amount, adjusts the phase and frequency of a phase trimmer through a serial port, enables the time difference measurement value between the time to be calibrated of a time frequency source and the reference time provided by the UTC device to reach a set value, and completes time correction;

the taming control system comprises a time interval measuring module, an FPGA, a digital-to-analog conversion module and a single chip microcomputer; the time interval module receives the time difference reference data and the single-station time difference data, compares the time difference reference data with the single-station time difference data, sends the time difference data to the FPGA, receives and processes the data in the FPGA, obtains the adjustment quantity from the FPGA by the singlechip, and sends the adjustment quantity to the phase trimmer after passing through the digital-to-analog conversion module.

Compared with the prior art, the time source tracing method has the advantages of improving the reliability and the precision of time source tracing of the time correction system and providing a precondition guarantee for the accurate measurement of the time frequency parameters of the GNSS time system terminal.

Drawings

FIG. 1 is a block diagram of remote time-frequency transfer tracing according to the present invention;

FIG. 2 is a block diagram of the taming control system of the present invention;

FIG. 3 is a power supply module circuit of the taming control system of the present invention;

FIG. 4 is a power-on sequence circuit of the FPGA power supply of the present invention;

FIG. 5 is a block diagram of a visualization system of the present invention;

FIG. 6 is a flowchart illustrating the control of the taming control system according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be further described with reference to the accompanying drawings and specific examples.

The first embodiment is as follows:

the invention provides a time correction system, which mainly realizes the functions of long-distance time frequency comparison and transmission, atomic clock calibration and the like as shown in figure 1. The time correction system mainly comprises a reference end, a Web service end and a client. The system utilizes the double-frequency multi-channel receiver to carry out common-view comparison, completes the transmission of time frequency by combining the Internet, completes the tracing process from the client to the reference end and achieves the aim of calibrating the time frequency standard source. The GNSS time-frequency transmission device provides time and frequency signals as a time-frequency reference terminal through an external UTC (BIRM, beijing radio metrology testing institute). The time frequency transmission device uploads the generated single station time difference data (i.e. time difference reference data) to an FTP server for storage. The GNSS time frequency transfer device at a client PMTI (Shanghai precision metrology testing institute) is externally connected with time and frequency signals output by a time frequency reference source (to be calibrated). The taming control system downloads the time difference reference data stored on the FTP server through the network, correspondingly processes the time difference reference data and the single-station time difference data generated by the GNSS time frequency transmission device of the PMTI according to a calibration algorithm, acquires an adjustment amount, and adjusts the phase and the frequency of the phase trimmer through a serial port, so that the time of a time frequency source and the UTC (BIRM) time difference of a reference end are shortened to be within an acceptable range, and the taming is finished. And new time difference data are continuously generated at certain time intervals, including the time difference data of the reference station and the client, so that the processes are continuously performed at certain periods, the stability of time and frequency output of the client is ensured by controlling the client for a long time, and finally the PMTI acquires a BIRM single-station time difference file by using the network.

The taming control system is shown in fig. 2 and comprises a time interval measuring module, an FPGA, a digital-to-analog conversion module and a singlechip; the time interval module receives the time difference reference data and the single-station time difference data, compares the time difference reference data with the single-station time difference data, sends the time difference data to the FPGA, receives and processes the data in the FPGA, obtains the adjustment quantity from the FPGA by the singlechip, and sends the adjustment quantity to the phase trimmer after passing through the digital-to-analog conversion module.

The hardware design of the taming control system needs to consider whether the modification of the test scheme is convenient, so that the mode of FPGA + single chip microcomputer is adopted. The single chip microcomputer mainly realizes algorithm processing and flow control of data and meets the requirement of hardware expansion in the future. The characteristics of high density, high speed and field programmable of the FPGA are utilized to facilitate debugging. The whole system comprises a power supply module, a data processing part, a frequency control part and an interface part, mainly adopts devices comprising a single chip microcomputer, an FPGA, a D/A (digital-to-analog conversion module) and a voltage-controlled crystal oscillator, and the digital-to-analog conversion module adopts a 16-digit analog-to-digital converter AD 5063.

The power supply module of the taming control system is shown in fig. 3 and is used for supplying power to the FPGA and the singlechip, wherein the FPGA adopts a Xinlinx 7 series FPGA, and the singlechip adopts an AT89S51 singlechip; the power supply module adopts a TPS54310 chip, the TPS54310 is a switch power supply adjusting chip produced by Texas instruments, and can realize low-voltage input and high-current output (the input voltage range is 3V-6V, the output voltage can be adjusted between 0.9V-3.3V according to requirements, and the output current is 3A). The voltage error amplifier is arranged inside the circuit, so that the working performance under the transient response condition can be improved. The slow start mode may be provided from the inside or the outside, respectively. Its good voltage output characteristics can be used for processor/logic reset, fault signal detection and continuous power supply.

In a power supply module of the taming control system, one ends of capacitors C1 and C3 are grounded in parallel, and the other ends of the capacitors are connected with a VIN port of a TPS54310 chip; one end of the resistor R1 is connected with the RT port of the TPS54310 chip, and the other end is grounded and used for setting the switching frequency of the module; one end of an inductor L1 is connected with a PH port of the TPS54310 chip, and the other end of the inductor L1 is connected with a capacitor C2 and then grounded and used for filtering output voltage; one end of the capacitor C4 is connected with a VBIAS port of the TPS54310 chip, and the other end of the capacitor C4 is grounded; one end of the capacitor C6 is connected with an SS/ENA port of the TPS54310 chip, and the other end is grounded; the capacitor C5 is connected between the PH port and the BOOT port of the TPS54310 chip; resistors R2, R3, R5, capacitors C7, C8 and C9 form a loop compensation circuit, wherein a capacitor C8 is connected in parallel with the resistor R5 and the capacitor C9 and is connected between a VSENSE port and a COMP port of a TPS54310 chip, and a resistor R2 is connected in parallel with the capacitor C7 and the resistor R3 and is connected between the VSENSE port and a PH port of the TPS54310 chip; the resistor R4 and the resistor R2 are used as voltage dividing resistors to control the output voltage of the power supply module, and the voltage dividing resistors are specifically as follows:

wherein V_outIs the output voltage.

Typical values of the input voltage are 5V, 3.7K Ω for R4 and 3.7K Ω for R5, which is calculated to be 3.3V for the I/O power supply of the FPGA. The I/O power supply of the singlechip can also be calculated in the mode.

The TPS54310 chip switching frequency can be set to a fixed 350KHz or 550KHz internal oscillator frequency, or can be set to an adjustable 280KHz-700 KHz. The setting of the oscillator is determined by SYNC (synchronous input) and RT (frequency setting register input) pins, and when the SYNC pin and the RT pin are suspended, the switching frequency is 350 KHz. When the SYNC pin is suspended and a resistor R1 from 68K to 180K is connected between the RT pin and the ground, the conversion frequency is changed to be adjustable 280KHz-700 KHz. The calculation formula of the switching frequency is:

in the formula: f. of_SWTo switch the frequency, R1 is a resistance value connected between the RT pin and ground. Setting the resistance value of R1 to 71.5K ohms can calculate the power switch switching frequency to be 700 KHz.

The FPGA requires two power supplies, one being the core power supply (1.4V) and the other being the I/O power supply (3.3V). Because the FPGA is used in an embedded system, the power circuit design needs to consider not only the problems of voltage precision, stability, complexity of peripheral circuits, and the like, but also the problem of low power consumption. In addition, according to design requirements, in order to ensure normal operation of the chip, certain requirements are imposed on the power-on sequence of the two power supplies during power-on operation of the system, and if the requirements are violated, the performance of the device may be reduced or the device may be permanently damaged. The core power supply is powered on earlier than the I/O power supply, and at least cannot be powered on later than the I/O power supply. The problem of the power-up sequence of the system is solved by using a method of connecting diodes in series between two power sources in a circuit design as shown in fig. 4.

The diode will have a tube voltage drop in forward conduction, and in the present system, the schottky MURS120T3 diode is selected, and its tube voltage drop is 0.4V. Therefore, if the I/O power supply (VCC3.3) is powered on first, the voltage of the I/O power supply is reduced by five diodes to obtain a voltage of 1.3V, so that an output pin of the core power supply can also reach 1.3V, and the core power supply and the I/O power supply can be powered on at least at the same time.

Preferably, the phase trimmer is connected with a visualization system, as shown in fig. 5, the time correction result is displayed through the visualization system, the visualization system includes a data source adaptation system, a database, a real-time calculation frame and a configuration information template, and third-party data imports data into the database in the system through the data source adaptation system, and generates a corresponding data model at the same time; after data are imported into a database and a data model is generated, the real-time computing frame automatically outputs corresponding chart information according to the generated data model and in combination with a configuration information template; the database is a MongoDB database.

Example two:

the invention also provides a time correction method, which comprises the following steps:

the time frequency source inputs time to be calibrated through the phase trimmer, the phase trimmer processes the time to form a 1PPS signal, and the 1PPS signal is input to the local GNSS time frequency transfer device; the local GNSS time frequency transfer device compares the satellite signal received by the first antenna with the 1PPS signal to generate single station time difference data, and inputs the single station time difference data to the taming control system;

the UTC device provides reference time to the reference GNSS time frequency device; the reference GNSS time frequency transfer device compares the satellite signals received by the second antenna with reference time to generate time difference reference data, and uploads the time difference reference data to the FTP server for storage;

the taming control system downloads time difference reference data stored on the FTP server through a network, processes the time difference reference data with single station time difference data generated by a local GNSS time frequency transfer device, acquires an adjustment amount, adjusts the phase and frequency of a phase trimmer through a serial port, enables the time difference measurement value between the time to be calibrated of a time frequency source and the reference time provided by the UTC device to reach a set value, and completes time correction;

the taming control system comprises a time interval measuring module, an FPGA, a digital-to-analog conversion module and a single chip microcomputer; the time interval module receives the time difference reference data and the single-station time difference data, compares the time difference reference data with the single-station time difference data, sends the time difference data to the FPGA, receives and processes the data in the FPGA, obtains the adjustment quantity from the FPGA by the singlechip, and sends the adjustment quantity to the phase trimmer after passing through the digital-to-analog conversion module.

The time taming of the taming control system comprises 4 steps of initialization, initial adjustment, fine adjustment and locking, and the flow is shown in FIG. 6.

The flow control is mainly completed by using a program in the single chip microcomputer, the calculation and conversion of a voltage control value are carried out, and the aim of strict alignment of the pulse per second rising edge is realized. When the singlechip reads the time difference data from the FPGA, the 2 pulse intervals are controlled within hundreds of nanoseconds. By using the difference data, the voltage control value of the crystal oscillator can be adjusted so that the 2 rising edges of 1PPS are closer. The following describes several main steps of the control flow.

Firstly, the initialization process is carried out, namely, the voltage control value and each parameter variable are initially assigned, so that the crystal oscillator frequency can be adjusted to the central frequency, namely 10MHz, as soon as possible.

After initialization, the initial tuning process is entered. Setting 1 initial adjustment judgment threshold in the FPGA, receiving time difference data by the FPGA, and when the time difference is greater than the initial adjustment judgment threshold, carrying out integer period adjustment on an internal counter by the FPGA so that the second pulse output by the crystal oscillator is rapidly close to the clock source second pulse, thereby realizing the rapid adjustment of the time difference data. Since the jitter amount of the optical fiber time transfer channel is generally only a few nanoseconds, which is much smaller than the time width of 1 clock cycle, unlike the space-based channel, the setting of the initial tuning threshold needs to be considered from the aspects of system performance and stability. Generally, the smaller the initial tuning threshold is set, the shorter the time required for zero point search is, but too small a threshold is likely to trigger the threshold due to the respective outlier in the locked state to cause initial tuning, so it is usually set to be 4 clock cycles, i.e. 400 ns. And after the initial adjustment is finished, entering a zero point searching process, rapidly changing the voltage control value to find a point with zero time difference data through zero point searching, and entering an initial frequency locking state. The main purpose of setting this process is to further narrow the variation range of the differential pressure data, generally locking within 1 clock cycle width, and preventing the time difference from being greater than the initial tuning threshold and entering the initial tuning again.

The primary frequency locking process mainly changes the voltage control value according to the time difference data and the corresponding relation between the time difference data and the voltage control value, and achieves the purpose of primarily locking the frequency to 10 MHz. According to a control model obtained by testing the voltage-controlled crystal oscillator in the early stage, the voltage-controlled value is obtained by calculating according to the variation of the time difference data, and the output frequency of the crystal oscillator is adjusted every second, so that the time difference data is jittered in a smaller range. Due to the influence of system noise and the like, a TIC (time interval measurement) chip has points with discrete discontinuity and large relative error in the process of reporting time difference data, and a wild value needs to be removed at the moment.

And finally entering an algorithm frequency locking process. And processing the time difference data by using algorithms such as multiple averaging, Kalman filtering and the like, removing errors caused by optical fiber channel transmission and internal noise of a machine, and obtaining the time difference data which is more approximate to a true value as a data source. When the time difference data is processed, the advantage that Kalman filtering can realize real-time signal estimation is mainly utilized, the medium-and-long-term trend of time difference change is obtained from the measurement data containing measurement noise and the noise of the crystal oscillator, and the voltage-controlled crystal oscillator is controlled by utilizing the filtered time difference value. In the process, different filtering effects can be obtained by setting the storage length of the historical data in the averaging algorithm, the proportional coefficient of the time difference and the pressure control value and the parameters of the observation noise covariance R and the excitation noise covariance Q in the Kalman algorithm, so that the precise frequency regulation and control are realized. In the locked mode, the tame clock module will be in an out-of-lock state if the external second pulse is lost. At this time, the locking flag is set to be low, and the voltage-controlled value of the crystal oscillator continues to control the voltage-controlled crystal oscillator according to the originally set aging characteristic. When the external reference second pulse is recovered, the clock discipline process will quickly return to the zero point search process and enter the locking process again.

Example three:

the invention also provides a GNSS common-view comparison data processing and analyzing method, which comprises the following steps:

1) linear interpolation method

Calculating the time difference measurement value delta T of all tracking sections observed every day, calculating the fitting value of 00:00:00 of UTC time of the day by using least square normal fitting to obtain the time difference fitting value of the ith day zero hour, and using delta T_iAnd (4) showing. If n time difference values are obtained by measuring n days, the n time difference sequences delta T are processed_iFitting according to least square normative to obtain a fitting slope a₁(unit: ns/d). The calculation formula is as follows:

wherein, t_iThe time of the ith day is the time of day,n balance mean time;

is the average value of the time difference of n days;

from a to a₁The relative deviation of the two-place atomic clock is obtained as follows:

wherein, Delta T_iThe fitting value of the time difference at zero time of the ith day is in ns;

is the average value of the time difference of n days;

Δ f is the frequency offset, f is the frequency nominal value, τ is the sampling time interval, τ is 86400 seconds.

And according to the time difference value of n days, the parameters of the measured atomic frequency standard, such as relative long-term stability, drift rate and the like, can be further obtained.

2) Two day smoothing

And calculating the fitting value of the UTC zero time on the 2 nd day by using least square normal fitting to obtain the fitting value of the time difference on the 2 nd day, wherein the time difference measuring value delta T of the tracking section every two days is obtained. And calculating the relative frequency accuracy according to a formula. The method can smooth gross errors caused by observation of different satellites and improve the precision of the final observation result. However, because the data smoothing applies partial same region data, the final result has a certain correlation.

3) Kalman filtering

The output signal of a general oscillator can be described by the following model:

where a is the initial phase, b is the frequency offset, c is the frequency aging coefficient, and v (t) is the noise of the atomic clock. In the GPS time difference comparison data, the influence of atmospheric noise and other measurement noise of the GPS signal in the transmission process is contained, and a Kalman filtering (Kalman Filter) technology is adopted, so that partial noise can be filtered, and the short-term stability of the GPS signal is obviously improved. The Kalman filtering method is a linear unbiased minimum variance estimation method, is the most common and effective method for solving the dynamic tracking problem, adopts a state space model of a linear random system consisting of a state equation and an observation equation to describe a filter, recurs to carry out the optimal estimation on the state variable of the filter, and has higher robustness and filtering precision.

The modeling is carried out by adopting a Kalman filtering method, a constant-speed motion model can be established by only considering two state quantities of a and b, a constant-acceleration motion model can also be established by considering three state quantities of a, b and c, or a Singer (Singer) motion model is established by assuming that the probability density of the maneuvering acceleration approximately obeys uniform distribution and is expressed by a first-order time correlation model which is input as white noise. Aiming at the motion characteristic of atomic clock error, a non-zero mean value of maneuvering acceleration and a time-dependent model for correcting Rayleigh distribution, namely a maneuvering target 'current' statistical model, are adopted to replace a conventional filtering model, and the conventional filtering model is designed

Wherein a (t) is an acceleration value with respect to time t, α is a preset constant,is the mean of the current acceleration, w (t) is a noise function of time t, in filteringUsing current predicted value of accelerationInstead, k is the current state and k +1 is the next state, then the equation of state is obtained:

wherein x is a state prediction value;

discretizing to obtain a discrete state equation as follows:

wherein X (k +1) is a next state prediction value, X (k) is a current state prediction value, phi (k +1, k) is a state transition matrix, U (k) is an input matrix, and W (k) is a noise matrix;

handleBy usingInstead of deriving

X(k+1)＝Φ₁(k+1,k)X(k)+W(k)

Wherein T is an output value;

when the correlation constant α takes a small value, the covariance matrix q (k) of the system process noise w (k) is reduced to:

whereinWherein a is_maxThe acceleration is the maximum acceleration, and the acceleration is the maximum acceleration,is an acceleration estimate.

The filter established by the 'current' statistical model is a real-time identification adaptive filtering algorithm, the statistical characteristic of the maneuvering acceleration is described by adopting the corrected Rayleigh distribution, and the state noise covariance matrix Q (k) changes along with the degree of the deviation of the current acceleration from the maximum acceleration (drift rate in the case of the maximum acceleration), so that the adaptive filtering capability is greatly improved. The filter obtains an observation matrix h (k) ═ 1,0,0 by using all the time difference sequences as observed quantities, sets observation noise based on empirical values, and performs filtering smoothing on all the tracking data by using results of clock difference, clock speed, and clock speed obtained by a linear interpolation method as initial values of state quantities. And then obtaining the UTC zero-time fitting time difference of each day by adopting a linear interpolation method, and further obtaining each parameter.

Example four:

the invention also provides a memory storing a computer program executed by a processor to perform the steps of:

the time frequency source inputs time to be calibrated through the phase trimmer, the phase trimmer processes the time to form a 1PPS signal, and the 1PPS signal is input to the local GNSS time frequency transfer device; the local GNSS time frequency transfer device compares the satellite signal received by the first antenna with the 1PPS signal to generate single station time difference data, and inputs the single station time difference data to the taming control system;

the UTC device provides reference time to the reference GNSS time frequency device; the reference GNSS time frequency transfer device compares the satellite signals received by the second antenna with reference time to generate time difference reference data, and uploads the time difference reference data to the FTP server for storage;

the taming control system downloads time difference reference data stored on the FTP server through a network, processes the time difference reference data with single station time difference data generated by a local GNSS time frequency transfer device, acquires an adjustment amount, adjusts the phase and frequency of a phase trimmer through a serial port, enables the time difference measurement value between the time to be calibrated of a time frequency source and the reference time provided by the UTC device to reach a set value, and completes time correction;

the taming control system comprises a time interval measuring module, an FPGA, a digital-to-analog conversion module and a single chip microcomputer; the time interval module receives the time difference reference data and the single-station time difference data, compares the time difference reference data with the single-station time difference data, sends the time difference data to the FPGA, receives and processes the data in the FPGA, obtains the adjustment quantity from the FPGA by the singlechip, and sends the adjustment quantity to the phase trimmer after passing through the digital-to-analog conversion module.

It should be noted that the foregoing is only illustrative and illustrative of the present invention, and that any modifications and alterations to the present invention are within the scope of the present invention as those skilled in the art will recognize.