阅读说明：本技术 一种七阵元抗干扰北斗卫星导航系统 (Seven-array-element anti-interference Beidou satellite navigation system ) 是由 曾平华 于 2019-05-07 设计创作，主要内容包括：本发明公开了一种七阵元抗干扰北斗卫星导航系统,包括天线阵列和卫星信号接收机；卫星信号接收机包括接收机壳体,于接收机壳体的上端和下端分别卡紧有接收机上盖板和接收机下盖板；于接收机壳体内卡紧有抗干扰单元、接收机单元和电源单元；于接收机壳体侧壁内用螺纹旋接有射频接头,于射频接头的一端固定有射频连接线；于接收机壳体内固定有导航解算模块和时钟管理模块；天线阵列包括安装架,于安装架下部中间位置固定有本振模块和电源模块；安装架的下部固定有射频通道电路；于安装架的上部固定有天线；于安装架的顶部固定有天线罩；于安装架的下部外壁上固定有SMP连接器,射频通道电路包括GNSS射频模块和7个BD2射频模块。(The invention discloses a seven-array-element anti-interference Beidou satellite navigation system which comprises an antenna array and a satellite signal receiver; the satellite signal receiver comprises a receiver shell, wherein an upper cover plate and a lower cover plate of the receiver are respectively clamped at the upper end and the lower end of the receiver shell; an anti-interference unit, a receiver unit and a power supply unit are clamped in the receiver shell; a radio frequency connector is screwed in the side wall of the receiver shell through threads, and a radio frequency connecting wire is fixed at one end of the radio frequency connector; a navigation resolving module and a clock management module are fixed in the receiver shell; the antenna array comprises a mounting rack, and a local oscillator module and a power supply module are fixed in the middle of the lower part of the mounting rack; a radio frequency channel circuit is fixed at the lower part of the mounting rack; an antenna is fixed on the upper part of the mounting rack; an antenna housing is fixed at the top of the mounting frame; an SMP connector is fixed on the outer wall of the lower part of the mounting frame, and the radio frequency channel circuit comprises a GNSS radio frequency module and 7 BD2 radio frequency modules.)

1. A seven-array-element anti-interference Beidou satellite navigation system is characterized by comprising an antenna array and a satellite signal receiver;

the satellite signal receiver comprises a receiver shell (6), wherein an upper cover plate (8) and a lower cover plate (5) of the receiver are respectively clamped at the upper end and the lower end of the receiver shell (6); an anti-interference unit (7), a receiver unit (4) and a power supply unit (3) are clamped in the receiver shell (6); a radio frequency connector (1) is screwed in the side wall of the receiver shell (6) by using threads, and a radio frequency connecting wire (2) is fixed at one end of the radio frequency connector (1) extending into the receiver shell (6); a navigation resolving module and a clock management module are fixed in the receiver shell (6);

the antenna array comprises a mounting rack, and a local oscillator module and a power supply module are fixed in the middle of the lower part of the mounting rack; a radio frequency channel circuit is fixed at the lower part of the mounting rack; an antenna is fixed on the upper part of the mounting rack; an antenna housing is fixed at the top of the mounting frame; an SMP connector is fixed on the outer wall of the lower part of the mounting frame, and the radio frequency channel circuit comprises a GNSS radio frequency module and 7 BD2 radio frequency modules.

2. The seven-array-element anti-interference Beidou satellite navigation system according to claim 1, wherein the navigation resolving module is used for processing the received baseband signals, the GPS and GLONASS radio frequency signals and outputting navigation information according to the processing result;

the navigation resolving module comprises an FPGA chip XC6SLX150-2-FGG484I, and a double-channel ADC, an SDRAM, an ARM, an LPDDR, an interface chip and a single-channel ADC are electrically connected to the FPGA chip XC6SLX150-2-FGG 484I; and is electrically connected with a shunt through the two-way ADC.

3. The seven-array-element anti-interference Beidou satellite navigation system according to claim 2, wherein the power supply module adopts an isolation power supply module and adopts a V24C12C100BL to convert an input 28V power supply into a 12V output to supply power to each unit; V24C12C100BL isolates the external power supply from the internal cells.

4. The seven-array-element anti-jamming Beidou satellite navigation system according to claim 3, wherein the BD2 anti-jamming module comprises a 15dB adjustable attenuator, a chip AD9269 and an FPGA chip XC5VSX 95T; the output ends of the two 15dB adjustable attenuators are electrically connected to the input end of a chip AD 9269; the output terminal of the chip AD9269 is electrically connected to the input terminal of the chip XC5VSX 95T;

the model of the ARM chip is an LPC3250 fixed-point digital signal processor; the chip XC5VSX95T and the chip XC6SLX150-2-FGG484I are separately and independently configured; the chip XC5VSX95T is configured by two PROMs of 32 Mbits; the chip XC6SLX150-2-FGG484I is configured in an SPI mode through a FLASH chip W25Q64BV, and the storage space is 64 Mbits; the interface chip is a standard RS422 serial port with isolation function, and the model of the interface chip is IL 422-3V.

5. The seven-array-element anti-interference Beidou satellite navigation system according to claim 4, wherein the clock management module comprises a first splitter, and the crystal oscillator signal is input into the first splitter and then respectively outputs a first crystal oscillator signal and a second crystal oscillator signal; the first crystal oscillator signal is sequentially input to a second splitter through a first LC filter circuit, a coaxial cable and a second LC filter circuit, and a third crystal oscillator signal and a fourth crystal oscillator signal are respectively output through the second splitter; the third oscillating signal is transmitted to a BD2 anti-interference module through an attenuator; the fourth crystal oscillator is transmitted to the comparator;

the clock management module adopts a CFPT-9000 series 20MHz crystal oscillator, and the frequency stability is 10-8; after the 20MHz crystal oscillator is split by the splitter, one path of crystal oscillator signal is sent to the local oscillator chip, and the other path of crystal oscillator signal is sent to the anti-interference unit (7) after LC filtering, amplifying and splitting.

6. The seven-array-element anti-interference Beidou satellite navigation system according to claim 5, characterized in that a channel circuit adopts a digital front-end signal distortion-free design and a high isolation degree design among radio frequency channels, so that the radio frequency channels have high linearity to meet the requirement of an adaptive zeroing algorithm; the cavities are sealed separately for each rf channel to ensure high isolation between the channels.

7. The seven-array-element anti-interference Beidou satellite navigation system according to claim 6, wherein the antennas comprise 7 BD2 antennas and 1 GG antenna, and a double-feed-point feeding mode is adopted; one of the BD2 antennas is fixed at the center position of the antenna body with coordinates of (0, 0); the 6 BD2 antennas are distributed on the peripheral side of the middle BD2 antenna.

8. The seven-array-element anti-interference Beidou satellite navigation system according to claim 7, wherein the local oscillator module comprises a local oscillator chip ADF4360-6, and the local oscillator chip ADF4360-6 is configured by adopting a single chip microcomputer NC100 to output a local oscillator signal with the frequency of 1198 MHz; amplifying the local oscillation signal, carrying out two-stage shunt, and outputting the signal with the intensity of 1.5dBm to each BD radio frequency unit; also included is chip LT1963, which converts 5V to 3.3V/1.5A for ADF4360 and NC 100.

9. The seven-array-element anti-interference Beidou satellite navigation system according to claim 8, wherein the power supply module comprises an LTM4602 power supply chip, and the LTM4602 power supply chip supplies 12V to 5V/5A input to the radio frequency channel circuit and the local oscillator module.

10. The seven-array-element anti-interference Beidou satellite navigation system according to claim 9, wherein the GNSS radio frequency module receives 1 path of GNSS signals sent by the antenna, and performs filtering and amplification to ensure that the gain of the GNSS radio frequency module meets system receiving requirements; and the BD2 radio frequency module is used for receiving a BD2 signal sent by the antenna, amplifying, filtering and performing down-conversion processing on 7 paths of BD2 signals, and outputting an intermediate frequency signal.

Technical Field

The invention relates to the technical field of navigation, in particular to a seven-array-element anti-interference Beidou satellite navigation system.

Background

Common anti-interference technologies based on antenna arrays include adaptive nulling technologies based on spatial filtering, space-time joint adaptive filtering technologies, digital multi-beam technologies, and the like.

The adaptive nulling technique generally employs a power inversion algorithm, and suppresses the influence of interference on the satellite receiver by forming a spatial null in the interference direction. The technical algorithm is simple. The technology is mature and is firstly applied in engineering. The technology has the defects that the space null influences the normal receiving of the satellite signals in the null direction while inhibiting interference, the number of anti-interference signals is limited by the number of array elements, and the maximum number of anti-interference signals is reduced by 1 for the number of the array elements. The space-time joint adaptive filtering is a research hotspot in China. The digital multi-beam technology is an important branch of the field of the phased array radar, is relatively mature, and needs to be adaptively improved in combination with the application condition of a satellite receiver. The technology is rapidly developed in two years, the technical core is broken through, and the performance advantage is gradually reflected.

Since the satellite signal is often buried deeply in the noise signal and the interference signal, it is not easy to obtain the optimal weighting of the array element received signal. The strongest signals can be selected from the multiple beams by adopting the beam space processing mode so as to meet the quality requirement. On the premise of meeting the array receiving effect, the method can reduce the operation amount and the system complexity. The interference resistance of the digital wave beam technology is related to the number of antenna array elements, the more the number of the antenna array elements is, the stronger the interference resistance is, but the practical engineering realization is limited by the requirement of the antenna structure size, and the number of the antenna array elements is limited. The anti-interference capability of the digital beam technology is also influenced by signal amplitude and phase consistency, signal sampling precision, channel processing error and the like, and the factors need to be strictly controlled during engineering design. The digital beam technology has complex algorithm and large computation amount, and needs to optimize the algorithm and take special measures when the engineering is realized. For each beam channel, spatial filtering techniques are now widely used. However, the technology has a series of defects, such as weak interference suppression capability near a signal source, weak coherent interference resistance and multipath interference resistance, and the like.

Disclosure of Invention

The invention aims to provide a seven-array-element anti-interference Beidou satellite navigation system which is used for solving the problem that the existing navigation system is weak in anti-interference capability.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a seven-array element anti-interference Beidou satellite navigation system comprises an antenna array and a satellite signal receiver; the satellite signal receiver comprises a receiver shell, wherein an upper cover plate and a lower cover plate of the receiver are respectively clamped at the upper end and the lower end of the receiver shell; an anti-interference unit, a receiver unit and a power supply unit are clamped in the receiver shell; a radio frequency connector is screwed in the side wall of the receiver shell through threads, and a radio frequency connecting wire is fixed at one end of the radio frequency connector, which extends into the receiver shell; a navigation resolving module and a clock management module are fixed in the receiver shell;

the antenna array comprises a mounting rack, and a local oscillator module and a power supply module are fixed in the middle of the lower part of the mounting rack; a radio frequency channel circuit is fixed at the lower part of the mounting rack; an antenna is fixed on the upper part of the mounting rack; an antenna housing is fixed at the top of the mounting frame; an SMP connector is fixed on the outer wall of the lower part of the mounting frame, and the radio frequency channel circuit comprises a GNSS radio frequency module and 7 BD2 radio frequency modules.

Preferably, the navigation resolving module is used for processing the received baseband signals, the GPS and GLONASS radio frequency signals and outputting navigation information according to the processing result;

the navigation resolving module comprises an FPGA chip XC6SLX150-2-FGG484I, and a double-channel ADC, an SDRAM, an ARM, an LPDDR, an interface chip and a single-channel ADC are electrically connected to the FPGA chip XC6SLX150-2-FGG 484I; and is electrically connected with a shunt through the two-way ADC.

Preferably, the power supply module adopts an isolation power supply module and adopts a V24C12C100BL to convert an input 28V power supply into a 12V output to supply power to each unit; V24C12C100BL isolates the external power supply from the internal cells.

Preferably, the BD2 anti-interference module comprises a 15dB adjustable attenuator, a chip AD9269 and an FPGA chip XC5VSX 95T; the output ends of the two 15dB adjustable attenuators are electrically connected to the input end of a chip AD 9269; the output terminal of the chip AD9269 is electrically connected to the input terminal of the chip XC5VSX 95T;

the model of the ARM chip is an LPC3250 fixed-point digital signal processor; the chip XC5VSX95T and the chip XC6SLX150-2-FGG484I are separately and independently configured; the chip XC5VSX95T is configured by two PROMs of 32 Mbits; the chip XC6SLX150-2-FGG484I is configured in an SPI mode through a FLASH chip W25Q64BV, and the storage space is 64 Mbits; the interface chip is a standard RS422 serial port with isolation function, and the model of the interface chip is IL 422-3V.

Preferably, the clock management module comprises a first splitter, and the crystal oscillator signal is input into the first splitter and then respectively outputs a first crystal oscillator signal and a second crystal oscillator signal; the first crystal oscillator signal is sequentially input to a second splitter through a first LC filter circuit, a coaxial cable and a second LC filter circuit, and a third crystal oscillator signal and a fourth crystal oscillator signal are respectively output through the second splitter; the third oscillating signal is transmitted to a BD2 anti-interference module through an attenuator; the fourth crystal oscillator is transmitted to the comparator;

the clock management module adopts a CFPT-9000 series 20MHz crystal oscillator, and the frequency stability is 10-8; after the 20MHz crystal oscillator is shunted by the shunt, one path of crystal oscillator signal is sent to the local oscillator chip, and the other path of crystal oscillator signal is sent to the local oscillator chip of the anti-interference unit after LC filtering, amplifying and shunting.

Preferably, the channel circuit adopts a digital front-end signal distortion-free design and a high isolation design between radio frequency channels, so that the radio frequency channels have high linearity to meet the requirement of an adaptive zeroing algorithm; the cavities are sealed separately for each rf channel to ensure high isolation between the channels.

Preferably, the antennas include 7 BD2 antennas and 1 GG antenna, and both adopt a double-feed-point feeding mode; one of the BD2 antennas is fixed at the center position of the antenna body with coordinates of (0, 0); the 6 BD2 antennas are distributed on the peripheral side of the middle BD2 antenna, and the corresponding coordinates are (-74, 40), (-74, -40), (0, -74), (74, -40), (74, 40), (0, 74), respectively; the GG antenna is fixed at the upper left corner of the antenna body, and the coordinates are (-80 );

the BD2 antenna in the middle is line 1; the BD2 antenna at the upper left corner is line 2, and the remaining BD2 antennas are line 3 to line 7 in order clockwise; the distance between the No. 1 central antenna and the left and right BD2 antennas is 74mm, and the distance between the No. 1 central antenna and the other 4 BD2 antennas is 84 mm; the distances between two adjacent B3 antennas from No. 2 to No. 7 are as follows: 80mm, 81.4mm, 80mm, 81.4mm and 81.4 mm;

the thicknesses of the 7 BD2 antennas and the 1 GG antenna are both 5 mm; the dielectric constant of the BD2 antenna is 10.2; the dielectric constant of the GG antenna is 12.5; the BD2 antenna size was 43mm by 43 mm; the size of the GG antenna is 32mm multiplied by 32 mm;

the antenna housing is made of glass fiber reinforced plastic with the dielectric constant of 4.6; the length and width of the antenna housing are 260mm multiplied by 260 mm; the thickness of the radome within a range of 194mm x 194mm directly above the antenna is 3mm, and the thickness of the radome outside the inner cavity is 6 mm.

Preferably, the local oscillation module comprises a local oscillation chip ADF4360-6, and the local oscillation chip ADF4360-6 is configured by adopting a singlechip NC100 to output a local oscillation signal with the frequency of 1198 MHz; amplifying the local oscillation signal, carrying out two-stage shunt, and outputting the signal with the intensity of 1.5dBm to each BD radio frequency unit; also included is chip LT1963, which converts 5V to 3.3V/1.5A for ADF4360 and NC 100.

Preferably, the power module includes an LTM4602 power chip, and the LTM4602 power chip supplies the input 12V to 5V/5A to the rf channel circuit and the local oscillation module.

Preferably, the GNSS radio frequency module receives the 1-channel GNSS signal sent by the antenna, and performs filtering and amplification to ensure that the gain of the GNSS radio frequency module meets the system receiving requirement; and the BD2 radio frequency module is used for receiving a BD2 signal sent by the antenna, amplifying, filtering and performing down-conversion processing on 7 paths of BD2 signals, and outputting an intermediate frequency signal.

The invention has the following advantages:

(1) the invention constructs a seven-array-element anti-interference Beidou satellite navigation system by comprehensively adopting digital beam forming and inertia-assisted deep combination technologies based on adaptive space-time combined filtering, and has the capability of resisting multi-target compression-type interference;

(2) the antenna array design of the invention adopts a digital front-end signal distortion-free design, ensures the distortion-free transmission of signals in a specified dynamic range in a single radio frequency channel, avoids the saturation and channel blockage of devices in the radio frequency channel caused by in-band strong interference signals, and meets the requirement of an adaptive zeroing algorithm on high linearity of the radio frequency channel;

(3) the receiver design of the invention adopts the high isolation design between the radio frequency channels, avoids the over-close distance between the devices between two adjacent channels when the PCB is arranged and wired, and structurally adopts a mode of independently sealing a cavity for each channel to ensure the high isolation between the channels, thereby improving the anti-jamming capability of the self-adaptive zero-adaptive receiver.

(4) The navigation system has the capability of resisting the multi-target pressure system interference, can resist a plurality of interference sources in different directions at the same time, and can be adaptive to the capability of resisting continuous wave, frequency sweep, broadband noise, pulse pressure system interference and the like; the navigation resolving processing is carried out under the interference condition, and the navigation positioning precision under the interference condition is ensured;

(5) in the design of a radio frequency circuit, radio frequency signals from an antenna are subjected to down-conversion treatment for one time, and digital-to-analog conversion is directly performed after frequency conversion and filtering; the conversion times of radio frequency signals are reduced, the design of a radio frequency front end is simplified, and the volume and the cost of the radio frequency front end are reduced while the function is ensured; in addition, the frequency components in the radio frequency channel can be effectively reduced by adopting a one-time down-conversion design, the external interference is reduced, and the electromagnetic compatibility is ensured.

(6) The invention solves the interference problem of the Beidou navigation receiver, adopts 16-bit ADC for a 7-array BD2 receiving antenna under the condition of undistorted transmission of a digital front-end signal, and distributes the anti-interference performance indexes of various anti-interference technologies as follows: the digital multi-beam technology provides 5dB anti-interference capability; the digital null technology provides 50dB broadband interference resistance; the spreading gain of the receiver provides 35dB interference rejection. In conclusion, the anti-broadband interference capability of the anti-interference Beidou navigation system is greater than 85 dB. The method has the advantages of low power consumption and high performance, can be widely applied to various navigation equipment and military professional navigation equipment, and has strong overall market competitive advantage.

Drawings

Fig. 1 is a functional block diagram of an inventive antenna array.

Fig. 2 is a structural view of the interior of the antenna array in the invention.

Fig. 3 is a functional block diagram of a satellite receiver in the invention.

Fig. 4 is a diagram of the internal structure of the receiver in the invention.

Fig. 5 is a schematic diagram of an array antenna of the present invention.

Fig. 6 is a mounting diagram of the array antenna carrier in the invention.

Fig. 7 is a schematic view of the inventive antenna cover.

FIG. 8 is a functional block diagram of a GNSS radio unit of the present invention.

Fig. 9 is a functional block diagram of a BD2 radio frequency module in the invention.

Fig. 10 is a block diagram of a local oscillation module in the present invention.

Fig. 11 is a block diagram of a power supply module of the invention.

Fig. 12 is a functional block diagram of a receiver in the invention.

Fig. 13 is a schematic diagram of the power distribution of the system of the invention.

Fig. 14 is a schematic diagram of an anti-interference module in the invention.

FIG. 15 is a schematic diagram of a navigation solution module of the invention.

FIG. 16 is a schematic diagram of the inventive clock circuit.

Fig. 17 is a schematic diagram of the anti-interference software of the invention.

Fig. 18 is a power supply circuit diagram in the invention.

Fig. 19 is a diagram of the rf power supply of the invention.

Fig. 20 is a circuit diagram of a channel in the invention.

FIG. 21 is a circuit diagram of a first peripheral of the channel of the invention.

Fig. 22 is a second peripheral circuit diagram of the channel of the invention.

FIG. 23 is a third peripheral circuit diagram of the channel of the invention.

FIG. 24 is a circuit diagram of an inventive FPGA.

FIG. 25 is a diagram of the first peripheral circuit of the FPGA of the invention.

FIG. 26 is a diagram of a second peripheral circuit of the FPGA of the present invention.

FIG. 27 is a circuit diagram of the DSP according to the present invention.

FIG. 28 is the first peripheral circuit diagram of the DSP in the invention.

FIG. 29 is a diagram of a second peripheral circuit of the DSP in the invention.

FIG. 30 is a diagram of the third peripheral circuit of the DSP according to the present invention.

FIG. 31 is a diagram of a fourth peripheral circuit of the DSP according to the present invention.

FIG. 32 is a diagram of the fifth peripheral circuit of the DSP according to the present invention.

FIG. 33 is a diagram of the sixth peripheral circuit of the DSP according to the present invention.

FIG. 34 is the seventh peripheral circuit diagram of the DSP in the invention.

In the figure: 1-radio frequency connector; 2-radio frequency connection line; 3-a power supply unit; 4-a receiver unit; 5-a receiver lower cover plate; 6-receiver housing; 7-an anti-interference unit; 8-receiver upper cover plate.

Detailed Description

The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.