阅读说明：本技术 一种led芯片及其制作方法 (LED chip and manufacturing method thereof ) 是由 李威平 周弘毅 刘英策 张书山 于 2019-09-26 设计创作，主要内容包括：本申请实施例公开了一种LED芯片及其制作方法,该方法包括：在衬底的第一侧表面形成第一半导体层；在第一半导体层背离衬底的一侧形成发光层；在发光层背离第一半导体层的一侧形成第二半导体层,第二半导体层与第一半导体层的掺杂类型不同；对第二半导体层和发光层对应第一预设区域的部分进行刻蚀,曝露部分第一半导体层；利用预设溶液对第一半导体层的侧壁进行腐蚀,使得第一半导体层的侧壁具有预设表面,预设表面与衬底交界位置所在的平面与衬底所在平面之间的夹角为锐角,预设溶液中包括四甲基氢氧化铵。该方法制作的LED芯片具有较高的取光效率和较强的抗ESD能力。(The embodiment of the application discloses an LED chip and a manufacturing method thereof, wherein the method comprises the following steps: forming a first semiconductor layer on a first side surface of a substrate; forming a light-emitting layer on one side of the first semiconductor layer, which is far away from the substrate; forming a second semiconductor layer on one side of the light-emitting layer, which is far away from the first semiconductor layer, wherein the doping type of the second semiconductor layer is different from that of the first semiconductor layer; etching the second semiconductor layer and the part of the light-emitting layer corresponding to the first preset area, and exposing part of the first semiconductor layer; and corroding the side wall of the first semiconductor layer by using a preset solution, so that the side wall of the first semiconductor layer has a preset surface, an included angle between a plane where the preset surface and the substrate junction position are located and a plane where the substrate is located is an acute angle, and the preset solution comprises tetramethyl ammonium hydroxide. The LED chip manufactured by the method has high light extraction efficiency and strong ESD resistance.)

1. A manufacturing method of an LED chip is characterized by comprising the following steps:

forming a first semiconductor layer on a first side surface of a substrate;

forming a light-emitting layer on one side of the first semiconductor layer, which is far away from the substrate;

forming a second semiconductor layer on one side of the light-emitting layer, which is far away from the first semiconductor layer, wherein the doping type of the second semiconductor layer is different from that of the first semiconductor layer;

etching the second semiconductor layer and the part of the light-emitting layer corresponding to the first preset area, and exposing a part of the first semiconductor layer;

corroding the side wall of the first semiconductor layer by using a preset solution, so that the side wall of the first semiconductor layer is provided with a preset surface, wherein an included angle between a plane where the joint position of the preset surface and the substrate is located and a plane where the substrate is located is an acute angle, and the preset solution comprises tetramethyl ammonium hydroxide.

2. The method according to claim 1, wherein an angle between a plane where the predetermined surface and the substrate interface are located and a plane where the substrate is located ranges from 60 ° to 90 °, inclusive of 60 °, but exclusive of 90 °.

3. The method of claim 1, wherein the predetermined surface is a concave arc surface or a flat surface.

4. The method of claim 1, wherein etching the sidewall of the first semiconductor layer with a predetermined solution so that the sidewall of the first semiconductor layer has a predetermined surface comprises:

forming a protective layer covering the surface and the side wall of the second semiconductor layer, the side wall of the light emitting layer and the surface of the first semiconductor layer;

and corroding the side wall of the first semiconductor layer by using a preset solution by taking the protective layer as a mask, so that the side wall of the first semiconductor layer has a preset surface.

5. The method of claim 4, wherein the protective layer is a silicon dioxide layer, a silicon nitride layer, or a hafnium oxide layer.

6. The method of claim 1, wherein the concentration of tetramethylammonium hydroxide in the predetermined solution is in the range of 5% to 25%, inclusive.

7. The method according to claim 1, wherein the etching of the sidewall of the first semiconductor layer with the predetermined solution is performed at a temperature ranging from 50 ℃ to 120 ℃ inclusive; the time for etching the side wall of the first semiconductor layer by using the preset solution ranges from 20 minutes to 120 minutes inclusive.

8. The method of claim 1, wherein before etching the sidewalls of the first semiconductor layer with a predetermined solution, the method further comprises:

and etching the second preset area of the first semiconductor layer, and exposing a part of the substrate, wherein the exposed part of the substrate surrounds the first semiconductor layer.

9. An LED chip manufactured by the manufacturing method of any one of claims 1 to 8, the LED chip comprising:

a substrate;

a first semiconductor layer on the first side surface of the substrate;

the light-emitting layer is positioned on one side, away from the substrate, of the first semiconductor layer;

the second semiconductor layer is positioned on one side, away from the first semiconductor layer, of the light-emitting layer;

the side wall of the first semiconductor layer is provided with a preset surface, and an included angle between a plane where the preset surface and the substrate junction position are located and a plane where the substrate is located is an acute angle.

10. The LED chip of claim 9, wherein an angle between a plane of the interface between the predetermined surface and the substrate and a plane of the substrate ranges from 60 ° to 90 °, inclusive of 60 °, but exclusive of 90 °; and/or the presence of a gas in the gas,

the preset surface is an inwards concave arc surface or a plane.

Technical Field

The application relates to the technical field of manufacturing, in particular to an LED chip and a manufacturing method thereof.

Background

Because Light Emitting Diodes (LEDs) have the advantages of high brightness, long life, small volume, low energy consumption, etc., they are considered as a new generation of illumination tools and widely applied in various fields such as indication, display, decoration, backlight, general illumination, and urban night scenes. However, the light extraction efficiency of the conventional LED chip is low.

Disclosure of Invention

In order to solve the technical problem, an embodiment of the present application provides an LED chip and a manufacturing method thereof, so as to improve light extraction efficiency of the LED chip.

In order to solve the above problem, the embodiment of the present application provides the following technical solutions:

a method for manufacturing an LED chip comprises the following steps:

forming a first semiconductor layer on a first side surface of a substrate;

forming a light-emitting layer on one side of the first semiconductor layer, which is far away from the substrate;

forming a second semiconductor layer on one side of the light-emitting layer, which is far away from the first semiconductor layer, wherein the doping type of the second semiconductor layer is different from that of the first semiconductor layer;

etching the second semiconductor layer and the part of the light-emitting layer corresponding to the first preset area, and exposing a part of the first semiconductor layer;

corroding the side wall of the first semiconductor layer by using a preset solution, so that the side wall of the first semiconductor layer is provided with a preset surface, wherein an included angle between a plane where the joint position of the preset surface and the substrate is located and a plane where the substrate is located is an acute angle, and the preset solution comprises tetramethyl ammonium hydroxide.

Optionally, an included angle between a plane where the preset surface and the boundary position of the substrate are located and a plane where the substrate is located ranges from 60 ° to 90 °, including 60 °, but not including 90 °.

Optionally, the preset surface is an inwardly concave arc surface or a plane.

Optionally, etching the sidewall of the first semiconductor layer with a predetermined solution, so that the sidewall of the first semiconductor layer having a predetermined surface includes:

forming a protective layer covering the surface and the side wall of the second semiconductor layer, the side wall of the light emitting layer and the surface of the first semiconductor layer;

and corroding the side wall of the first semiconductor layer by using a preset solution by taking the protective layer as a mask, so that the side wall of the first semiconductor layer has a preset surface.

Optionally, the protective layer is a silicon dioxide layer, a silicon nitride layer, or a hafnium oxide layer.

Optionally, the concentration of tetramethylammonium hydroxide in the preset solution ranges from 5% to 25%, inclusive.

Optionally, the temperature for etching the sidewall of the first semiconductor layer by using the preset solution ranges from 50 ℃ to 120 ℃, inclusive; the time for etching the side wall of the first semiconductor layer by using the preset solution ranges from 20 minutes to 120 minutes inclusive.

Optionally, before etching the sidewall of the first semiconductor layer with a predetermined solution, the method further includes:

and etching the second preset area of the first semiconductor layer, and exposing a part of the substrate, wherein the exposed part of the substrate surrounds the first semiconductor layer.

An LED chip manufactured by any one of the above methods, the LED chip comprising:

a substrate;

a first semiconductor layer on the first side surface of the substrate;

the light-emitting layer is positioned on one side, away from the substrate, of the first semiconductor layer;

the second semiconductor layer is positioned on one side, away from the first semiconductor layer, of the light-emitting layer;

the side wall of the first semiconductor layer is provided with a preset surface, and an included angle between a plane where the preset surface and the substrate junction position are located and a plane where the substrate is located is an acute angle.

Optionally, an included angle between a plane where the boundary position between the preset surface and the substrate is located and a plane where the substrate is located ranges from 60 ° to 90 °, including 60 °, but not including 90 °; and/or the preset surface is an inwards concave arc surface or a plane.

Compared with the prior art, the technical scheme has the following advantages:

according to the technical scheme, the side wall of the first semiconductor layer is corroded by using the preset solution containing tetramethylammonium hydroxide, so that the side wall of the first semiconductor layer is provided with the preset surface, and an included angle between the plane where the preset surface and the substrate boundary position are located and the plane where the substrate is located is an acute angle, so that the incident angle of the light emitting layer, which irradiates the side wall of the first semiconductor layer, on the side wall of the first semiconductor layer is changed, the light extraction efficiency of the side wall of the first semiconductor layer is increased, and the light extraction efficiency of the LED chip is improved.

Moreover, according to the technical scheme provided by the embodiment of the application, the side wall of the first semiconductor layer is corroded by the aid of the preset solution containing tetramethylammonium hydroxide, the preset surface is smooth, so that the LED chip is high in ESD breakdown resistance, the risk of ESD breakdown of the LED chip is reduced, the probability of metal ions or insoluble floccules remaining on the LED chip is reduced, the LED chip is even free of metal ions or insoluble floccules or other products, and the performance of the LED chip is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart of a method for manufacturing an LED chip according to an embodiment of the present application;

fig. 2-15 are cross-sectional views of structures formed at various steps in a method for manufacturing an LED chip according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

As described in the background section, the light extraction efficiency of the conventional LED chip is low.

During specific operation, most of light emitted by the LED active region is emitted from the top of the P-type region into the air, but the refractive index difference between the LED active region and the P-type region is large, for example, when the P-type region is a gallium nitride layer, the refractive index of gallium nitride (GaN) material is 2.5, the refractive index of air is 1, light is transmitted from the P-type region into the air, and light with an incident angle of greater than 23 ° from the gallium nitride layer to the air is totally reflected at the interface between the gallium nitride layer and the air, so that the light is transmitted back and forth inside the chip, and finally, the light absorption and the total reflection of the semiconductor material are continuously lost, which finally results in that the light extraction efficiency of the whole chip is low.

The inventor researches and discovers that the surface of the P-type region can be roughened to improve the light extraction efficiency of the LED chip, for example, potassium hydroxide or phosphoric acid is used to form a periodic or random structure on the surface or the sidewall of the P-type region to change the incident angle of part of light incident on the interface between the P-type region and the air, so that the light can be emitted from the chip to the air, and the light extraction efficiency is improved. However, the LED chip prepared by this method has a rough sidewall, which not only causes the LED to have a risk of ESD (Electro-static discharge) breakdown, but also causes metal ions or insoluble flocs to easily remain on the LED chip, which affects the performance of the chip.

In view of this, an embodiment of the present application provides a method for manufacturing an LED chip, as shown in fig. 1, the method includes:

s1: a first semiconductor layer is formed on a first side surface of a substrate.

Specifically, in an embodiment of the present application, the forming the first semiconductor layer on the first side surface of the substrate includes:

as shown in fig. 2, a growth substrate 101 is provided, optionally, in an embodiment of the present application, the substrate 101 is a sapphire substrate, in another embodiment of the present application, the substrate 101 is a silicon substrate, and in other embodiments of the present application, the substrate 101 may also be a silicon carbide substrate or a substrate of another material, which is not limited in this application, as the case may be;

as shown in fig. 3, a first semiconductor layer 102 is formed on the first side surface of the substrate 101, and optionally, the first semiconductor layer 102 is an N-type semiconductor layer, specifically, in an embodiment of the present application, the first semiconductor layer 102 is an N-type gallium nitride layer, but this is not limited thereto in the present application, as the case may be.

S2: as shown in fig. 4, a light emitting layer 103 is formed on a side of the first semiconductor layer 102 facing away from the substrate 101, and optionally, the light emitting layer 103 is a quantum well light emitting layer.

S3: as shown in fig. 5, a second semiconductor layer 104 is formed on a side of the light emitting layer 103 facing away from the first semiconductor layer 102, and the second semiconductor layer 104 has a doping type different from that of the first semiconductor layer 102.

Optionally, in an embodiment of the present application, the second semiconductor layer 104 is a P-type semiconductor layer, specifically, in an embodiment of the present application, the second semiconductor layer 104 is a P-type gallium nitride layer, but the present application does not limit this to this, which is determined as the case may be.

In the embodiment of the present application, the first semiconductor layer 102, the light emitting layer 103, and the second semiconductor layer 104 form an epitaxial structure.

S4: etching the second semiconductor layer 104 and the part of the light emitting layer 103 corresponding to the first preset area, and exposing a part of the first semiconductor layer 102.

Optionally, in an embodiment of the present application, the first preset region is a region where an N-type electrode is formed subsequently, in the embodiment of the present application, etching portions of the second semiconductor layer 104 and the light emitting layer 103 corresponding to the first preset region, and exposing a portion of the first semiconductor layer 102 includes:

as shown in fig. 6, etching the portions of the second semiconductor layer 104 and the light emitting layer 103 corresponding to the N-type electrode to be formed, exposing a portion of the surface of the first semiconductor layer 102, where the exposed surface of the first semiconductor layer 102 is located on one side of the second semiconductor layer 104 and the light emitting layer 103.

In an embodiment of the present application, the first predetermined region includes not only a region where an N-type electrode is subsequently formed, but also an edge region of the second semiconductor layer 104 and the edge region of the light emitting layer 103, and in the embodiment of the present application, etching a portion of the second semiconductor layer 104 and a portion of the light emitting layer 103 corresponding to the first predetermined region, and exposing a portion of the first semiconductor layer 102 includes:

as shown in fig. 7, etching is performed on the second semiconductor layer 104 and the light emitting layer 103 corresponding to the predetermined region, so as to expose a portion of the surface of the first semiconductor layer 102, and the exposed surface of the first semiconductor layer 102 surrounds the second semiconductor layer 104 and the light emitting layer 103, so as to reduce the process difficulty when etching is performed on the second semiconductor layer 104 and the light emitting layer 103 corresponding to the predetermined region.

On the basis of any of the above embodiments, in an embodiment of the present application, etching the portions of the second semiconductor layer 104 and the light emitting layer 103 corresponding to the N-type electrode to be formed includes: etching the second semiconductor layer 104 and the part of the light-emitting layer 103 corresponding to the to-be-formed N-type electrode by using a dry etching process; optionally, in an embodiment of the present application, etching portions of the second semiconductor layer 104 and the light emitting layer 103, which correspond to portions where N-type electrodes are to be formed, includes: the second semiconductor layer 104 and the light emitting layer 103 corresponding to the portion to be formed with the N-type electrode are etched by using a plasma etching process, in other embodiments of the present application, other processes may also be used to etch the second semiconductor layer 104 and the light emitting layer 103 corresponding to the portion to be formed with the N-type electrode.

It should be noted that, in the above embodiment, etching is performed on the portions of the second semiconductor layer 104 and the light emitting layer 103 corresponding to the first predetermined region, and only the portions of the second semiconductor layer 104 and the light emitting layer 103 corresponding to the first predetermined region may be etched when exposing a portion of the first semiconductor layer 102, or not only the portions of the second semiconductor layer 104 and the light emitting layer 103 corresponding to the first predetermined region may be etched, but also the portions may extend into the first semiconductor layer 102, and the portions of the first semiconductor layer 102 may be etched, as long as a portion of the first semiconductor layer 102 is exposed.

On the basis of any of the above embodiments, in an embodiment of the present application, after etching portions of the second semiconductor layer 104 and the light emitting layer 103 corresponding to a first predetermined region and exposing a portion of the first semiconductor layer 102, before etching sidewalls of the first semiconductor layer 102 with a predetermined solution, the method further includes:

as shown in fig. 8, the second predetermined region of the first semiconductor layer 102 is etched to expose a portion of the substrate 101, and the exposed portion of the substrate 101 surrounds the first semiconductor layer 102, so as to reduce the process difficulty when a predetermined solution is subsequently used to etch the sidewall of the first semiconductor layer 102, so that the sidewall of the first semiconductor layer 102 has a predetermined surface.

Optionally, on the basis of the foregoing embodiment, in an embodiment of the present application, etching a second preset region of the first semiconductor layer 102 to expose a portion of the substrate 101, where the exposing portion of the substrate 101 surrounding the first semiconductor layer 102 includes: and etching a second preset area of the first semiconductor layer 102 by using a dry etching process, exposing a part of the substrate 101, wherein the exposed part of the surface of the substrate 101 surrounds the first semiconductor layer 102. Specifically, in an embodiment of the present application, etching the second predetermined region of the first semiconductor layer 102 to expose a portion of the substrate 101, where the exposing of the substrate 101 to surround the first semiconductor layer 102 includes: and etching a second preset area of the first semiconductor layer 102 by using a plasma etching process, exposing a part of the substrate 101, wherein the exposed part of the surface of the substrate 101 surrounds the first semiconductor layer 102. In other embodiments of the present application, other processes may also be adopted to etch the second preset region of the first semiconductor layer 102, and expose a part of the substrate 101, so that the exposed part of the surface of the substrate 101 surrounds the first semiconductor layer 102.

S5: as shown in fig. 9, a preset solution is used to corrode the sidewall of the first semiconductor layer 102, so that the sidewall of the first semiconductor layer 102 has a preset surface, an included angle a between a plane where the boundary position between the preset surface and the substrate 101 is located and a plane where the substrate 101 is located is an acute angle, and the preset solution includes tetramethylammonium hydroxide.

Optionally, on the basis of the foregoing embodiment, in an embodiment of the present application, an included angle a between a plane where the preset surface and the substrate 101 are located and a plane where the substrate 101 is located ranges from 60 ° to 90 °, including 60 °, excluding 90 °. It should be noted that the smaller the included angle a between the plane where the boundary position between the preset surface and the substrate 101 is located and the plane where the substrate 101 is located, the better the light extraction efficiency of the LED chip is, and the greater the process difficulty of the LED chip is.

On the basis of any of the above embodiments of the present application, in one embodiment of the present application, the predetermined solution is an aqueous solution of tetramethylammonium hydroxide, and in another embodiment of the present application, the predetermined solution is a tetramethylammonium hydroxide solution added with a buffer, that is, a mixed solution of an additive and an aqueous solution of tetramethylammonium hydroxide, which is not limited in this application, and is determined as the case may be.

Optionally, in an embodiment of the present application, etching the sidewall of the first semiconductor layer 102 with a predetermined solution so that the sidewall of the first semiconductor layer 102 has a predetermined surface includes:

as shown in fig. 10, a protective layer 105 is formed to cover the surface and the sidewall of the second semiconductor layer 104, the sidewall of the light-emitting layer 103, and the surface of the first semiconductor layer 102;

as shown in fig. 11, the protective layer 105 is used as a mask, and a predetermined solution is used to etch the sidewall of the first semiconductor layer 102, so that the sidewall of the first semiconductor layer 102 has a predetermined surface, and an included angle a between a plane where the boundary position between the predetermined surface and the substrate 101 is located and a plane where the substrate 101 is located is an acute angle.

Optionally, on the basis of the above embodiment, in an embodiment of the present application, the protection layer 105 is a silicon dioxide layer, and in another embodiment of the present application, the protection layer 105 is a silicon nitride layer. In other embodiments of the present application, the protection layer 105 may also be another material layer such as hafnium oxide, which is not limited in the present application, as the case may be.

On the basis of any one of the above embodiments, in an embodiment of the present application, the concentration of tetramethylammonium hydroxide in the preset solution ranges from 5% to 25%, inclusive; the temperature for etching the side wall of the first semiconductor layer 102 by using the preset solution ranges from 50 ℃ to 120 ℃ inclusive; the time for etching the sidewall of the first semiconductor layer 102 with the predetermined solution ranges from 20 minutes to 120 minutes, inclusive.

On the basis of any of the above embodiments, in an embodiment of the present application, the predetermined surface is an arc surface that is concave, and in another embodiment of the present application, the predetermined surface is a plane, that is, the sidewall of the first semiconductor layer 102 is an inclined surface, which is not limited by the present application as long as the light extraction efficiency of the sidewall of the first semiconductor layer 102 can be increased, and the predetermined surface is formed as a smooth surface, as the case may be.

It should be noted that the shape of the predetermined surface and the included angle between the predetermined surface and the plane of the substrate 101 are related to the arrangement mode of the LED chip when etching the sidewall of the first semiconductor layer 102, the etching time of the sidewall of the first semiconductor layer 102, the ambient temperature during etching, and the like.

Specifically, because tetramethylammonium hydroxide (TMAH) has anisotropic etching on each lattice direction of gallium nitride, the arrangement manner of the LED chips on the wafer affects the shape of the sidewall, such as horizontal arrangement, vertical arrangement, or oblique arrangement, so in the manufacturing process of the LED chip, the shape of the sidewall of the first semiconductor layer 102 and the included angle between the plane of the sidewall of the first semiconductor layer 102 and the plane of the substrate 101 can be changed by different arrangement manners.

On the basis of any of the above embodiments, in an embodiment of the present application, before forming the protective layer 105 covering the surface and the sidewall of the second semiconductor layer 104, the sidewall of the light emitting layer 103, and the surface of the first semiconductor layer 102, the method further includes:

as shown in fig. 12, a current spreading layer 106 is formed on the surface of the second semiconductor layer 104, and the protective layer 105 is formed after the current spreading layer 106 is formed, as shown in fig. 13, the protective layer 105 covers the surface and the sidewall of the current spreading layer 106, the sidewall of the second semiconductor layer 104, the sidewall of the light emitting layer 103, and the surface of the first semiconductor layer 102.

Optionally, on the basis of the above embodiment, in an embodiment of the present application, the current spreading layer 106 is a transparent conductive layer, but the present application does not limit this, which is determined as the case may be.

On the basis of any one of the above embodiments, in an embodiment of the present application, the method further includes:

as shown in fig. 14, etching portions of the protection layer 105 corresponding to a third preset region and a fourth preset region to expose a portion of the surface of the first semiconductor layer 102 and a portion of the surface of the second semiconductor layer 104 (or the current spreading layer 106), so as to form a first electrode electrically connected to the first semiconductor layer 102 in the third preset region and a second electrode electrically connected to the second semiconductor layer 104 in the fourth preset region in the following step;

as shown in fig. 15, a first electrode 107 electrically connected to the first semiconductor layer 102 is formed in the third predetermined region, and a second electrode 108 electrically connected to the second semiconductor layer 104 is formed in the fourth predetermined region. Optionally, the first electrode 107 is an N-type electrode, and the second electrode 108 is a P-type electrode.

Optionally, on the basis of the foregoing embodiment, in an embodiment of the present application, etching the portion of the protection layer 105 corresponding to the third preset region and the fourth preset region includes: and etching the parts of the protective layer 105 corresponding to the third preset area and the fourth preset area by using a dry etching process. Specifically, in an embodiment of the present application, etching the portion of the protection layer 105 corresponding to the third preset region and the fourth preset region includes: and etching the parts of the protective layer 105 corresponding to the third preset area and the fourth preset area by using a plasma etching process. However, the present application is not limited thereto, and in other embodiments of the present application, the protective layer 105 may be etched by other processes, as the case may be.

In addition to any of the above embodiments, in an embodiment of the present application, the forming of the first electrode 107 electrically connected to the first semiconductor layer 102 in the third predetermined region and the forming of the second electrode 108 electrically connected to the second semiconductor layer 104 in the fourth predetermined region include: a first electrode 107 electrically connected to the first semiconductor layer 102 and a second electrode 108 electrically connected to the second semiconductor layer 104 in the fourth predetermined region are formed in the third predetermined region by using an evaporation process, but the present application is not limited thereto, and in other embodiments of the present application, another process may be used to form the first electrode 107 electrically connected to the first semiconductor layer 102 and the second electrode 108 electrically connected to the second semiconductor layer 104 in the third predetermined region, as the case may be.

Optionally, the first electrode 107 and the second electrode 108 are formed in the same step, and more optionally, the first electrode 107 and the second electrode 108 are metal electrodes to reduce the resistivity of the first electrode 107 and the second electrode 108, but this is not limited in this application, and is determined as the case may be.

As can be seen from the above, in the manufacturing method of the LED chip provided in the embodiment of the present application, the sidewall of the first semiconductor layer 102 is etched by using the preset solution containing tetramethylammonium hydroxide, so that the sidewall of the first semiconductor layer 102 has the preset surface, and an included angle between a plane where the intersection of the preset surface and the substrate 101 is located and a plane where the substrate 101 is located is an acute angle, so as to change an incident angle of the light, which is emitted from the light emitting layer 103 to the sidewall of the first semiconductor layer 102, on the sidewall of the first semiconductor layer 102, increase the light extraction efficiency of the sidewall of the first semiconductor layer 102, and further improve the light extraction efficiency of the LED chip.

It should be noted that, in a package test, compared with a structure in which the sidewall of the first semiconductor layer 102 in the LED chip is perpendicular to the plane of the substrate 101, the luminance of the LED chip manufactured by the method for manufacturing an LED chip provided in the embodiment of the present application can be increased by about 0.5% to 1.5%, and no attenuation of other photoelectric characteristics is caused.

Moreover, according to the manufacturing method of the LED chip provided in the embodiment of the present application, the preset surface formed by etching the sidewall of the first semiconductor layer 102 with the preset solution including tetramethylammonium hydroxide is relatively smooth, so that not only is the ESD breakdown resistance of the LED chip strong, but also the risk of ESD breakdown of the LED chip is reduced, and the probability of metal ions or insoluble flocs remaining on the LED chip is reduced, even the LED chip is free of metal ions or insoluble flocs or other products, thereby improving the performance of the LED chip.

Correspondingly, the embodiment of the application also provides an LED chip provided by any one of the embodiments. Specifically, as shown in fig. 15, the LED chip includes:

a substrate 101, wherein optionally, the substrate 101 is a sapphire substrate, a silicon carbide substrate, or the like;

a first semiconductor layer 102 on a first side surface of the substrate 101;

the light emitting layer 103 is located on a side of the first semiconductor layer 102 away from the substrate 101, and optionally, the light emitting layer 103 is a quantum well light emitting layer;

a second semiconductor layer 104 located on a side of the light emitting layer 103 away from the first semiconductor layer 102, where the doping type of the second semiconductor layer 104 is different from that of the first semiconductor layer 102, optionally, the first semiconductor layer 102 is an N-type semiconductor layer, such as an N-type gallium nitride layer, and the second semiconductor layer 104 is a P-type semiconductor layer, such as a P-type gallium nitride layer;

the sidewall of the first semiconductor layer 102 has a preset surface, and an included angle between a plane where the preset surface and the substrate 101 are located and a plane where the substrate 101 is located is an acute angle.

Optionally, on the basis of the foregoing embodiment, in an embodiment of the present application, an included angle a between a plane where the preset surface and the substrate 101 are located and a plane where the substrate 101 is located ranges from 60 ° to 90 °, including 60 °, but not including 90 °. It should be noted that the smaller the included angle a between the plane where the boundary position between the preset surface and the substrate 101 is located and the plane where the substrate 101 is located, the better the light extraction efficiency of the LED chip is, and the greater the process difficulty of the LED chip is.

On the basis of the above embodiment, in an embodiment of the present application, the predetermined surface is an arc surface that is concave, and in another embodiment of the present application, the predetermined surface is a plane, that is, the sidewall of the first semiconductor layer 102 is an inclined surface, which is not limited in the present application as long as the light extraction efficiency of the sidewall of the first semiconductor layer 102 can be increased, and the predetermined surface is formed as a smooth surface, as the case may be.

On the basis of any one of the above embodiments, in an embodiment of the present application, the LED chip further includes:

a protective layer 105 covering the surface and the sidewall of the second semiconductor layer 104, the sidewall of the light emitting layer 103, and the surface of the first semiconductor layer 102, wherein the protective layer 105 is optionally a silicon dioxide layer, a silicon nitride layer, or another material layer such as hafnium oxide, which is not limited in this application, and is determined as the case may be.

It should be noted that, in the embodiment of the present application, the protection layer 105 has a third through hole corresponding to a third predetermined region and a fourth through hole corresponding to a fourth predetermined region, where the third through hole is used for subsequently forming the first electrode 107 electrically connected to the first semiconductor layer 102, and the fourth through hole is used for subsequently forming the second electrode 108 electrically connected to the second semiconductor layer 104.

On the basis of any one of the above embodiments, in an embodiment of the present application, the LED chip further includes:

and a current spreading layer 106 located between the second semiconductor layer 104 and the protective layer 105, wherein the protective layer 105 covers the surface and the sidewall of the current spreading layer 106, covers the sidewall of the second semiconductor layer 104, and covers the sidewall of the light emitting layer 103 and the surface of the first semiconductor layer 102.

Optionally, the current spreading layer 106 is a transparent conductive layer, but this is not limited in this application, as the case may be.

On the basis of any one of the above embodiments, in an embodiment of the present application, the LED chip further includes: a first electrode 107 electrically connected to the first semiconductor layer 102 through the third via hole, and a second electrode 108 electrically connected to the second semiconductor layer 104 through the fourth via hole.

Optionally, the first electrode 107 and the second electrode 108 are metal electrodes to reduce the resistivity of the first electrode 107 and the second electrode 108, but this is not limited in this application, and is determined as the case may be.

To sum up, in the LED chip provided in the embodiment of the present application, the sidewall of the first semiconductor layer 102 has a preset surface, and an included angle between a plane where the preset surface is located and a plane where the substrate 101 is located is an acute angle, so that an incident angle of light emitted from the light emitting layer 103 to the sidewall of the first semiconductor layer 102 at the sidewall of the first semiconductor layer is changed, light extraction efficiency of the sidewall of the first semiconductor layer 102 is increased, and light extraction efficiency of the LED chip is further improved.

Moreover, according to the LED chip provided in the embodiment of the present application, the sidewall of the first semiconductor layer is formed by etching a preset solution containing tetramethylammonium hydroxide, and the surface is smooth, so that the ESD breakdown resistance of the LED chip is high, the risk of ESD breakdown of the LED chip is reduced, the probability of metal ions or insoluble flocs remaining on the LED chip is reduced, and even the LED chip is free of metal ions or insoluble flocs or other products remaining thereon, thereby improving the performance of the LED chip.

In the description, each part is described in a progressive manner, each part is emphasized to be different from other parts, and the same and similar parts among the parts are referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.