阅读说明：本技术 形成多个光电器件的公共电极的方法 (Method of forming a common electrode for a plurality of optoelectronic devices ) 是由 马里恩·沃尔博特 于 2020-11-19 设计创作，主要内容包括：本发明涉及一种形成多个光电器件的公共电极(190)的方法,该方法包括以下步骤：a)提供支撑基底(111),在该支撑基底上放置由沟槽(170)隔开的光电器件；b)在正面、侧面和沟槽的底部上形成介电层(130),在正面和侧面上形成的介电层的厚度分别为厚度E1和小于厚度E1的厚度E2；c)将介电层(130)蚀刻厚度E3,以露出沟槽的第一部分(170a)处的侧面；d)形成填充沟槽以及覆盖正面的金属层；e)对金属层进行机械化学抛光,抛光停止在介电层(130)的一部分上,保留在沟槽(170)中的金属形成公共电极(190)。(The present invention relates to a method of forming a common electrode (190) for a plurality of opto-electronic devices, the method comprising the steps of: a) providing a support substrate (111) on which the photovoltaic devices separated by the trenches (170) are placed; b) forming a dielectric layer (130) on the front side, the side surfaces and the bottom of the trench, the dielectric layer formed on the front side and the side surfaces having a thickness of E1 and a thickness of E2 less than the thickness of E1, respectively; c) etching the dielectric layer (130) to a thickness E3 to expose sides at the first portion (170a) of the trench; d) forming a metal layer for filling the groove and covering the front surface; e) the metal layer is subjected to mechanochemical polishing, the polishing stopping on a portion of the dielectric layer (130), the metal remaining in the trench (170) forming a common electrode (190).)

1. A method of forming a common electrode (190) of a plurality of optoelectronic devices, each optoelectronic device of the plurality of optoelectronic devices comprising a front side (151a) and a back side (151b) connected by a side (151c), the method comprising the steps of:

a) -providing a support substrate (111) on whose surface, called main surface (111a), said plurality of photovoltaic devices separated by grooves (170), is placed by their rear faces (151b), said grooves (170) being defined by the sides (151c) of the photovoltaic devices and by the bottom at the main surface (111 a);

b) forming a dielectric layer (130) by covering the front side, the side face (151c) and a bottom of the trench (170), the thickness of the dielectric layer (130) at the front side and the side face (151c) being a thickness E1 and a thickness E2 smaller than a thickness E1, respectively;

c) wet etching the dielectric layer (130) to a thickness E3 that is less than the thickness E1 to expose the side surfaces (151c) at the first portion (171a) of the trench (170) and at least partially leave the dielectric layer (130) on the front surface;

d) forming a metal layer (185) by covering the trench (170) and covering the front surface;

e) -mechanochemical polishing of the metal layer (185), said polishing stopping on the part of the dielectric layer (130) covering the front side remaining at the end of step c), the metal remaining in the trenches (170) forming the common electrode (190);

each trench comprising, from the bottom, a second portion (171b) adjacent to the first portion, the first portion (171a) and the second portion extending according to a first height and a second height, respectively, the first portion (171a) opening into a plane formed by the front face of the optoelectronic device,

step b) is preceded by step b 0): step c) also enables removal of the passivation layer at the first portion (171a) by forming the passivation layer (120) by covering the front surface, the side surfaces (151c) and the bottom of the trench (170) according to a compliant deposition technique.

2. The method of claim 1, wherein the thickness E1 is at least 2 times greater than the thickness E2.

3. The method of claim 1, wherein step b0) is performed by atomic layer deposition.

4. The method according to claim 1, wherein the passivation layer (120) comprises at least a material selected from the group consisting of: SiO 2₂，Al₂O₃。

5. The method according to claim 1, wherein the thickness of the passivation layer (120) is between 5nm and 30 nm.

6. The method of claim 1, wherein the dielectric layer (130) is formed by a plasma activated chemical vapor deposition technique.

7. The method according to any one of claims 1 to 6, wherein the dielectric layer (130) comprises at least one material selected from the group consisting of: SiO 2₂，Si₃N₄。

8. The method according to claim 1, wherein step a) comprises transferring the stack of layers formed on the seed substrate onto a main surface (111a) of the support substrate (111).

9. The method according to claim 8, wherein after switching the stack of layers, the trench (170) is formed extending over the entire thickness of the stack.

10. The method of claim 9, wherein the forming of the trench (170) uses a hard mask that is removed prior to performing step b).

11. The method according to claim 1, wherein the optoelectronic device is a light emitting diode (172) comprising, from a front side (151a) to a back side (151 b): the light emitting diode comprises a first N-doped semiconductor layer (153), a light emitting layer assembly (155) and a second P-doped semiconductor layer (157), wherein the first height is smaller than or equal to the thickness of the first N-doped semiconductor layer.

12. A method according to claim 11, wherein said support substrate (111) comprises, on its main surface (111a), an integrated circuit intended to individually address each optoelectronic device of said plurality.

Technical Field

The present invention relates to the fields of microelectronics and optoelectronics. In particular, the invention relates to a method of forming electrical contacts at the sides of a device (more particularly a light emitting diode) placed on a main surface of a supporting substrate.

In particular, the invention is implemented in order to simplify manufacturing and to increase control of electrodes on the side faces of LEDs with very high aspect ratios, among other things.

Background

Light emitting display devices known in the art typically comprise Light Emitting Diode (LED) assemblies, in particular gallium nitride based Light Emitting Diode (LED) assemblies.

The LED comprises from the front to the back: an N-doped semiconductor layer, a light-emitting layer assembly and a P-doped semiconductor layer, and placing the LEDs, through their back side, on a support substrate provided with control circuitry intended to individually address each LED at its P-doped semiconductor layer.

The light emitting display device further includes a common electrode in electrical contact with the N-doped semiconductor layer of each of the LEDs. This electrical contact typically occurs at the side of the semiconductor layer.

Accordingly, a method of forming a light emitting display device known in the prior art is illustrated in fig. 1A to 1G.

The method specifically includes a step of providing a support substrate 111 having an integrated control circuit 110 formed on a main surface thereof as shown in fig. 1A. The integrated circuit comprises in particular metal connection posts 113 separated from each other by dielectric regions 114, the metal connection posts 113 being intended to connect a plurality of LEDs by their back surfaces.

Fig. 1B is a schematic view of a stack 150 of layers formed on a major surface of a support substrate 151. Specifically, from the main surface, the stack of layers includes an N-doped semiconductor layer 153, a light emitting layer assembly 155, and a P-doped semiconductor layer 157. Each of the layers may include gallium nitride.

The stack of layers 150 is then transferred onto a major surface of the support substrate 111 (fig. 1C) according to methods known in the art. The switching may comprise the steps of: the stack 150 is bonded on the integrated circuit 110, and then the support substrate 151 is removed.

Further, one or two intermediate metal layers 116 and 159 may be formed on the integrated circuit 110 and the stack 150, respectively, prior to the bonding step.

Then, the following steps are performed after the transferring step: trenches 170 are formed in the stack 150 from the face of the stack exposed to the external environment, and the trenches 170 extend through the thickness of the stack to define a plurality of LEDs 172 (fig. 1D).

The formation of the trench typically involves the following successive steps:

a hard mask layer such as a dielectric material layer is formed by covering the exposed surface of the stack 150,

a lithography step intended to define a pattern 120 at the hard mask layer by means of a photoresist layer,

the hard mask layer is etched to form a hard mask pattern 120,

the photolithographic resin applied in the photolithographic step is removed,

the stack 150 is etched through the hard mask to delineate the LEDs.

The etching step may be continued to subsequently remove portions of layer 116 and layer 159 from the bottom of trench 170.

Thus, at the end of the step, the support substrate 111 comprises a plurality of LEDs separated from each other by the trenches 170.

Specifically, the LEDs are placed on the main surface of the support substrate 111 through the back surfaces thereof, while the front surface of each LED, which is opposite to the back surface and is connected to the back surface through the side surface, is covered with the hard mask pattern 120. Thus, the trench 170 is defined by the bottom at the major surface of the support substrate and the sides of the LED.

Then, after the LED is formed, a step of passivating the LED is performed (fig. 1E). The passivation specifically includes forming a passivation film 190 by covering the hard mask pattern 120, the side 180 of the LED 172, and the bottom of the trench 170.

A step of partially removing the passivation layer is then performed. This step in particular comprises removing a portion of the passivation layer covering the pattern 120 and a first portion of the lateral surface extending from the front surface of the LED to a depth less than the thickness of the N-doped semiconductor layer (fig. 1F).

In other words, at the end of this step, the passivation layer 190 remains on the second portion extending from the bottom of the trench by a height corresponding to at least the combined thickness of the intermediate metal layer 116 and the intermediate metal layer 159, the P-doped semiconductor layer 157, and the light emitting layer assembly 155.

The removal is carried out in particular by a photolithographic step comprising filling the second part of the trench with a photolithographic resin and then etching the pattern 120 and the passivation layer at the first part.

Finally, the common electrode is formed by filling the trench 170 with a metal material.

In particular, the formation of the common electrode involves the growth of a metal layer, for example by electrodeposition covering the pattern 120 and filling the trenches.

A mechanochemical polishing step, stopping on the hard mask pattern 120, is next performed to leave metal only in the trenches.

However, the above method is not satisfactory.

In fact, at the end of the step of forming the trench, the thickness of the hard mask pattern 120 is not well controlled and is particularly non-uniform from one pattern to another.

The consequence of this non-uniformity is that there is a significant variation between the first part of one trench and the first part of the other trench, and therefore it is difficult to accurately control the extent of the contact area between the common electrode and the N-doped semiconductor layer of each LED.

It is therefore an object of the present invention to propose a method of forming a common electrode which is easy to implement.

It is a further object of the invention to propose a method of forming a common electrode which is more reliable and has less variability than methods known in the prior art.

Disclosure of Invention

The objects of the invention are at least partially achieved by a method of forming a common electrode for a plurality of optoelectronic devices, wherein each optoelectronic device comprises a front side and a back side connected by a side surface, the method comprising the steps of:

a) providing a support substrate, a plurality of optoelectronic devices separated by trenches being placed by their rear face on a face of the support substrate called main face, said trenches being defined by the lateral faces of said optoelectronic devices and by the bottom at the main face;

b) forming a dielectric layer by covering the front surface, the side surface and the bottom of the trench, the thicknesses of the dielectric layer of the front surface and the side surface being a thickness E1 and a thickness E2 smaller than the thickness E1, respectively;

c) wet etching the dielectric layer to a thickness E3 that is less than the thickness E1 to expose the sides at the first portion of the trench and at least partially leave the dielectric layer on the front side;

d) forming a metal layer for filling the groove and covering the front surface;

e) subjecting the metal layer to mechanochemical polishing, said polishing stopping on the part of the dielectric layer remaining at the end of step c), the metal remaining in the trench forming the common electrode.

According to one embodiment, each trench comprises, starting from the bottom, a second portion and a first portion adjacent to each other, the second portion and the first portion extending according to a second height and a first height, respectively, the first portion opening into a plane formed by the front face of the optoelectronic device.

According to one embodiment, thickness E1 is at least 2 times greater than thickness E2.

According to one embodiment, step b0) is included before step b): step c) also enables removal of the passivation layer at the first portion by forming the passivation layer according to a compliant deposition technique by covering the front side, the side surfaces and the bottom of the trench.

According to one embodiment, step b0) is performed by atomic layer deposition.

According to one embodiment, the passivation layer comprises at least a material selected from the group consisting of: SiO 2₂、Al₂O₃。

According to one embodiment, the thickness of the passivation layer is between 5nm and 30 nm.

According to one embodiment, the dielectric layer is formed by a plasma activated chemical vapor deposition technique.

According to one embodiment, the dielectric layer comprises at least one material selected from the group consisting of: SiO 2₂、Si₃N₄。

Silicon nitride Si considered in the present invention₃N₄Not necessarily stoichiometric.

According to one embodiment, step a) comprises transferring the stack of layers formed on the seed substrate onto a main surface of a support substrate.

According to one embodiment, after switching the stack of layers, a trench is formed that extends over the entire thickness of the stack.

According to one embodiment, the formation of the trench uses a hard mask that is removed before performing step b).

According to one embodiment, the optoelectronic device is a light emitting diode comprising, from its front side to its back side, a first N-doped semiconductor layer, a light emitting layer assembly and a second P-doped semiconductor layer, the first height being less than or equal to the thickness of the N-doped semiconductor layer.

According to one embodiment, the support substrate comprises, on a main surface thereof, an integrated circuit intended to address each optoelectronic device individually.

Drawings

Further characteristics and advantages of the invention will become apparent in the method of forming electrical contacts of a plurality of optoelectronic devices according to the invention, described by way of non-limiting example with reference to the following drawings, in which:

fig. 1A, 1B, 1C, 1D, 1E, 1F and 1G are schematic diagrams of the various steps carried out to manufacture a light-emitting display device according to a method known in the prior art, the figures relating to which are specifically illustrated according to a section perpendicular to a main surface of a supporting substrate;

fig. 2A, 2B, 2C, 2D and 2E are schematic diagrams of respective steps carried out in manufacturing a light emitting display device according to the present invention, and particularly show views related to the drawings in terms of a cross section perpendicular to a main surface of a support substrate;

fig. 3A, 3B, 3C, 3D, 3E and 3F are schematic views of the various steps that may be carried out to carry out step a) of the method of the invention, the views relating to the figures being shown in detail according to a section perpendicular to the main surface of the support substrate.

Detailed Description

Like reference symbols in the various drawings indicate like elements, and the various drawings are not necessarily to scale. For clarity, only elements useful for understanding the described embodiments are shown and described in detail.

In particular, embodiments of integrated control circuits known per se to the person skilled in the art have not been described in detail.

The present invention relates to a method of manufacturing a common electrode of an optoelectronic device which is placed on a main surface of a support substrate through its back surface.

The remainder of the description will be limited to optoelectronic devices formed from light emitting diodes (hereinafter "LEDs"). However, the person skilled in the art can apply the invention to any other type of device, such as a photodiode.

A schematic representation of the various steps of a method of manufacturing a common electrode for a plurality of light emitting diodes 172, each comprising a front side 151a and a back side 151b connected by a side 151c, is shown in fig. 2A to 2E.

In particular, the method comprises a step a): a support substrate 111 is provided, on the face of which the rear face 151b is intended to rest, with a plurality of light-emitting diodes 172 separated by trenches 170 (fig. 2A), the face being referred to as main face 111 a.

Specifically, the trench 170 is bounded by the side 151c of the light emitting diode 172 and the bottom 170a at the major surface 111 a.

The support substrate 111 may comprise, on its main surface 111a, an integrated circuit intended to address each light emitting diode 172 individually.

In particular, the integrated circuit may include metal connection posts 113 separated from each other by dielectric regions 114.

In particular, the metal connection posts 113 are intended to be connected to each of the rear faces 151b of the light emitting diodes 172, so as to be able to control the latter.

The integrated circuit may further comprise a base unit associated with each light emitting diode 172, the base unit being provided with one or more transistors for controlling the current circulating in the diode.

As shown in fig. 3A to 3F, the performing of step a) may specifically include the following steps.

a0) A support substrate 111 (fig. 3A, showing only the metal posts 113 and the dielectric regions 114) provided with an integrated circuit on its main surface 111a is provided.

a1) A stack 150 of layers is formed, for example by epitaxy, on a first face of a seed substrate 151 (fig. 3B).

a2) The stack of layers 150 is transferred onto the main surface 111a (fig. 3C).

a3) Trenches 170 are formed (fig. 3D and 3E).

Specifically, step a3) of forming the trench 170 is performed by forming a hard mask (fig. 3D) and then etching through the mask (fig. 3E) to define the light emitting diode 172.

In this regard, the hard mask includes a post 120, the post 120 being made of, for example, a dielectric material and defining an impression of the light emitting diode 172 to be formed. In particular, the thickness of the pillars 120 may be between 500nm and 1.5 μm, for example 1 μm.

Finally, after step a3), the hard mask-forming pillars 120 are removed (fig. 3F). This last step makes it possible to advantageously reduce the aspect ratio of the structures placed on the main surface 111a of the support substrate 111.

The stack formed in step a1) may include the first N-doped semiconductor layer 153, the light emitting layer assembly 155, and the second P-doped semiconductor layer 157 from the first side of the seed substrate 151. In other words, the light emitting diode includes the first N-doped semiconductor layer 153, the light emitting layer assembly 155, and the second P-doped semiconductor layer 157 from the front surface 151a to the back surface 151b thereof. According to another variant, the order of the stacked layers may be reversed.

Step a2) may include bonding a seed substrate (having a stack formed thereon) on the major surface 111a of the support substrate 111, and then removing the seed substrate and reducing the thickness of the layer 153.

The first N-doped semiconductor layer 153 may include N-doped GaN having a thickness between 0.5 μm and 0.2 μm.

The second P-doped semiconductor layer 157 may include P-doped GaN having a thickness between 0.1 μm and 0.5 μm.

More specifically, the total thickness of the stack 150 may be between 700nm and 3 μm.

Each light emitting layer in light emitting layer assembly 155 may include quantum wells based on, for example, GaN, InN, InGaN, AlGaN, AlN, AlInGaN, GaP, AlGaP, AlInGaP, or a combination based on one or more of the foregoing materials.

Alternatively, the light-emitting layer of the assembly 155 may be, for example, a residual donor concentration of 10¹⁵And 10¹⁸Atom/cm³Between (e.g., about 10)¹⁷Atom/cm³) I.e. not intentionally doped.

Prior to the switching step a2), one or two metal layers 116 and 159 may be formed by covering the main surface 111a and the free surface of the stack 150, respectively.

In particular, the two metal layers 116 and 159 are configured to contact each other during the step of switching a2) (fig. 3C).

Metal layer 116 may comprise titanium and aluminum.

The metal layer 159 may comprise a stack of aluminum and titanium layers, the titanium layer being intended to be in contact with the metal layer 116.

The thickness of the metal layer 116 may be between 300nm and 1 μm, for example 600 nm.

The thickness of the metal layer 159 may be between 50nm and 300nm, for example 100 nm.

Once the two metal layers 116 and 159 are considered, it is conceivable that the trench 170 formed in step a3) also extends over the entire combined thickness of the two layers (fig. 3E).

The method according to the invention further comprises a step b) performed after step a).

Specifically, step B) includes forming dielectric layer 130 by covering front surface 151a, side surfaces 151c, and bottom 170a of trench 170 (fig. 2B).

Specifically, the thicknesses of the dielectric layer 130 of the front surface 151a and the side surface 151c are a thickness E1 and a thickness E2 smaller than the thickness E1, respectively.

For example, thickness E1 is at least 2 times greater than thickness E2.

As another example, the thickness E1 may be between 100nm and 500nm, for example equal to 200 nm.

The dielectric layer 130 may be formed by a plasma activated chemical vapor deposition technique. This technique is particularly advantageous for embodiments of the present invention insofar as it enables the deposition of a non-compliant layer (i.e., a greater deposition rate on front surface 151a relative to side surface 151 c). However, the invention is not limited to this deposition technique and any other technique that would deposit a layer in a non-compliant manner may be used by those skilled in the art.

The dielectric layer 130 may include at least one material selected from the group consisting of: SiO 2₂、Si₃N₄。

Advantageously, according to a variant, step b) may be preceded by a step b 0): the passivation layer 120 is formed by covering the front surface 151a, the side surfaces 151c, and the bottom 170a of the trench 170 according to a compliant deposition technique.

"compliant deposition technique" refers to a technique in which the deposition rates on the side and front surfaces are substantially equal (advantageously equal). By "substantially equal" is meant that the relative deviation is less than 10%, advantageously less than 5%.

The passivation layer 120 may have a thickness between 5nm and 30nm and comprise at least a material selected from the group consisting of: SiO 2₂、Al₂O₃。

The passivation layer 120 may be formed by atomic layer deposition.

Step b) is followed by step c): dielectric layer 130 is wet etched to a thickness E3 that is less than thickness E1 to expose the sides at first portion 171a of the trench that extends a first height from front side 151a of light emitting diode 172 (fig. 2C).

Furthermore, step c) is performed to at least partially preserve the dielectric layer 130 on the front side 151 a.

Step c) is also performed to leave the dielectric layer 130 at a second portion 171b of the trench 170 adjacent to the first portion 171a, the second portion extending from the first portion to the bottom 170a of the trench 170.

The part of the dielectric layer remaining at the end of step c) will advantageously be used as a layer to stop the mechanochemical polishing step described in the remainder of the description.

If the passivation layer 120 is considered, the passivation layer at the first portion 171a is also etched.

Advantageously, step c) fills the second portion 171b of the trench 170 with a photolithographic resin before the wet etching.

Advantageously, the first height is less than or equal to the thickness of the N-doped semiconductor layer.

Step c) is followed by forming a common electrode 190. In particular, the method may comprise a step d): forming a metal layer 185 (fig. 2D) by covering the front surface 151a and the trench 170, in particular by electrodeposition or by CVD; and step e): a mechanochemical polish is performed to leave metal only in the trenches 170.

"covering the trench" means covering the sides and bottom.

According to the invention, the covering of the trench does not exclude the filling of the trench.

Still according to the invention, the step of filling the void in the trench with a metallic material may be performed without step d) causing filling of the trench.

Particularly advantageously, step d) can be carried out according to a damascene method.

In this regard, the portion of the dielectric layer 130 remaining on the front surface 151a at the end of step c) serves as a polishing stop layer.

The metal remaining in the trench 170 at the end of step e) forms a common electrode which is in electrical contact with the N-doped semiconductor layer of each light-emitting diode at the side face of the light-emitting diode.

The presence of the dielectric layer 130 and optionally a passivation layer at the second portion 170b enables the common electrode to be electrically isolated from the second P-doped semiconductor layer 157 and the light emitting layer assembly 155.

The invention is advantageously implemented when the aspect ratio of the light-emitting diode is large, in particular greater than 2. In fact, once the dielectric layer 130 and the passivation layer are considered, the removal of the hard mask according to the invention enables easier coverage of the topology by the dielectric layer 130 and the passivation layer.

Furthermore, during the mechanochemical polishing step, the front side of the light emitting diode (and thus the first N-doped semiconductor layer 153) is protected by the dielectric layer 130.