阅读说明：本技术 一种同轴光电器件及其底座 (Coaxial photoelectric device and base thereof ) 是由 汪振中 庄睿 于 2020-04-09 设计创作，主要内容包括：本申请公开了一种同轴光电器件及其底座,该底座具有相对的顶面和底面,以及贯穿所述顶面和底面的通孔；所述通孔内设有信号管脚,所述信号管脚与所述通孔的孔壁之间填充绝缘介质以固定所述信号管脚；所述信号管脚具有高出所述底座顶面的延长段,所述延长段上设有引线键合平面；所述底座的顶面在所述信号管脚的附近设有容性补偿结构,以降低所述信号管脚的阻抗。通过优化补偿设计,在TO底座与高速信号管脚上设计容性补偿结构,以降低信号管脚的阻抗,改善TO CAN封装的频响,使得组装时仍可采用传统的引线键合工艺实现高速信号与内部图形电路的连接,实现低成本、高频响的封装,可用于更高速率的应用场景。(The application discloses a coaxial photoelectric device and a base thereof, wherein the base is provided with a top surface, a bottom surface and a through hole penetrating through the top surface and the bottom surface; a signal pin is arranged in the through hole, and an insulating medium is filled between the signal pin and the hole wall of the through hole to fix the signal pin; the signal pin is provided with an extension section higher than the top surface of the base, and a lead bonding plane is arranged on the extension section; the top surface of the base is provided with a capacitive compensation structure near the signal pin to reduce the impedance of the signal pin. Through optimization compensation design, a capacitive compensation structure is designed on the TO base and the high-speed signal pin TO reduce the impedance of the signal pin and improve the frequency response of TO CAN packaging, so that the traditional lead bonding process CAN be still adopted during assembly TO realize the connection of a high-speed signal and an internal graphic circuit, the packaging with low cost and high frequency response is realized, and the TO CAN packaging structure CAN be used in application scenes with higher speed.)

1. A coaxial optoelectronic device mount having opposing top and bottom surfaces, and a through-hole extending through the top and bottom surfaces; a signal pin is arranged in the through hole, and an insulating medium is filled between the signal pin and the hole wall of the through hole to fix the signal pin; the method is characterized in that: the signal pin is provided with an extension section higher than the top surface of the base, and a lead bonding plane is arranged on the extension section; the top surface of the base is provided with a capacitive compensation structure near the signal pin to reduce the impedance of the signal pin.

2. The mount of coaxial optoelectronic device of claim 1, wherein: the top surface of the base is provided with a boss surrounding the signal pin, and the boss and the corresponding signal pin form the capacitive compensation structure.

3. The coaxial optoelectronic device mount of claim 2, wherein: the bosses are annular posts that surround the respective signal pins.

4. The coaxial optoelectronic device mount of claim 2, wherein: and an avoiding space is arranged on one side of the boss opposite to the lead bonding plane of the signal pin and used for avoiding a lead needle tool.

5. The mount of coaxial optoelectronic device of claim 1, wherein: the top surface of the base is provided with a bulge, the bulge is provided with a side surface facing the signal pin, and an insulating cushion block is arranged between the side surface and the signal pin; the bulges, the insulating cushion blocks and the corresponding signal pins form the capacitive compensation structure.

6. The mount of coaxial optoelectronic device of claim 5, wherein: and a conductive block is arranged between the insulating cushion block and the signal pin, the conductive block is in conductive connection with the signal pin, and the protrusion, the insulating cushion block and the conductive block form the capacitive compensation structure.

7. The mount of coaxial optoelectronic device of claim 6, wherein: the conductive bumps comprise solder bumps.

8. The mount of coaxial optoelectronic device of claim 5, wherein: the wire bonding plane is positioned on the side surface of the signal pin extension, and the height of the capacitive compensation structure on the other side surface of the extension, which is positioned outside the wire bonding plane, is equal to or less than the height of the extension.

9. The mount of coaxial optoelectronic device of any one of claims 1-8, wherein: the top surface of the base is also provided with a heat sink, the heat sink is provided with an installation plane parallel to the lead bonding plane, and the lead bonding plane and the installation plane of the heat sink face to the same direction.

10. A coaxial optoelectronic device, characterized by: comprising an optoelectronic chip, a substrate and the coaxial optoelectronic device mount of any one of claims 1-9; the substrate is arranged on the coaxial photoelectric device base, and the photoelectric chip is arranged on the substrate and is electrically connected with the substrate; the substrate is electrically connected with the signal pins through bonding wires.

Technical Field

The application relates to the technical field of optical communication, in particular to a coaxial photoelectric device and a base thereof.

Background

At present, the transmission speed of a high-speed link in optical communication is from 1.25Gbps to 10Gbps and then to 25Gbps of a single channel. The increase of transmission rate requires the bandwidth of transmission link to be increased continuously, 10Gbps signal requires 7GHz bandwidth, and 25Gbps signal requires 21GHz bandwidth.

Optical modules there are a variety of carriers in high-speed links, typically including:

1. the hard circuit board (PCB) is used as a carrier of SMD (Surface Mounted Devices) and is butted with a system, so that the cost is low;

2. a flexible circuit board (FPC), similar to a PCB, mainly used for interconnection between two hard carriers, which can absorb spatial tolerance;

3. the hermetic shell package (Ceramic Box/TO CAN) is used for packaging devices with high airtightness requirements, such as lasers, TEC, PD and the like;

4. the ceramic substrate (COP) is used for bearing the photoelectric device, and has good heat dissipation and high processing precision.

With the formal commercial use of 5G at home and abroad, the market puts forward the requirements of higher speed and lower cost for the encapsulation of the airtight tube shell. In the TO CAN packaging module commonly used at present, high-speed signals are directly led out from a driving chip in an SMD form and transmitted TO a laser chip through a PCB, an FPC and a TO base. The high-speed signal in the packaging form passes through a plurality of impedance abrupt points, and the transmission mode is complex to change. The larger the impedance mismatch on the transmission link, the more signal reflections and noise, resulting in higher distortion. Moreover, as the signal rate increases, from 10Gbps to 25Gbps applications, the jitter and noise requirements for the transmitted signal become more stringent. Where the TO submount acts as the primary hermetic package for the active laser, its package structure has a large impact on the link impedance.

As shown in fig. 1, in the structure of the conventional 2.5G TO base 10 ', a high-speed signal is connected TO an internal graphic circuit through a signal pin 20 ' and then by gold wire/soldering, etc., and the impedance of the signal pin 20 ' is divided into a soldering section 21 ', a connecting section connected TO the base, and an extension section 22 ' according TO the change of the impedance. The connection section connected to the base can control the impedance through the control glass column 30 'and the characteristic dimension of the coaxial structure, so that the impedance sudden change is small, while the extension section 22' has a higher impedance due to lack of reference, as shown in the simulation result shown in fig. 2, it can be seen that the impedance of the extension section of the signal pin suddenly changes from the standard 50Ohm to about 100 Ohm. Impedance mismatch will cause greater signal reflection and noise, resulting in higher signal distortion.

Disclosure of Invention

The coaxial photoelectric device and the base thereof are low in cost, simple in process, good in high-frequency performance and capable of being used in application scenes with higher speed.

In order to achieve one of the above objects, the present application provides a coaxial optoelectronic device mount having opposing top and bottom surfaces, and a through-hole extending through the top and bottom surfaces; a signal pin is arranged in the through hole, and an insulating medium is filled between the signal pin and the hole wall of the through hole to fix the signal pin; the signal pin is provided with an extension section higher than the top surface of the base, and a lead bonding plane is arranged on the extension section; the top surface of the base is provided with a capacitive compensation structure near the signal pin to reduce the impedance of the signal pin.

As a further improvement of the embodiment, the top surface of the base is provided with a boss surrounding the signal pin, and the boss and the corresponding signal pin form the capacitive compensation structure.

As a further refinement of the embodiment, the bosses are annular posts surrounding the respective signal pins.

As a further improvement of the embodiment, an avoiding space is arranged on one side of the boss opposite to the wire bonding plane of the signal pin for avoiding the wire needle tool.

As a further improvement of the embodiment, a protrusion is arranged on the top surface of the base, the protrusion has a side surface facing the signal pin, and an insulating cushion block is arranged between the side surface and the signal pin; the bulges, the insulating cushion blocks and the corresponding signal pins form the capacitive compensation structure.

As a further improvement of the embodiment, a conductive block is arranged between the insulating cushion block and the signal pin, the conductive block is in conductive connection with the signal pin, and the protrusion, the insulating cushion block and the conductive block form the capacitive compensation structure.

As a further refinement of the embodiment, the conductive bumps comprise solder bumps.

As a further improvement of the embodiment, the wire bonding plane is located at a side of the signal pin extension, and the height of the capacitive compensation structure located at the other side of the extension outside the wire bonding plane is equal to or less than the height of the extension.

As a further improvement of the embodiment, the top surface of the base is further provided with a heat sink, the heat sink has a mounting plane parallel to the wire bonding plane, and the wire bonding plane and the mounting plane of the heat sink face the same direction.

The application also provides a coaxial photoelectric device, which comprises a photoelectric chip, a substrate and the coaxial photoelectric device base in any embodiment; the substrate is arranged on the coaxial photoelectric device base, and the photoelectric chip is arranged on the substrate and is electrically connected with the substrate; the substrate is electrically connected with the signal pins through bonding wires.

The beneficial effect of this application: through optimization compensation design, a capacitive compensation structure is designed on a TO base and a high-speed signal pin TO reduce the impedance of the signal pin and improve the frequency response of TO CAN packaging, so that the connection between a high-speed signal and an internal graphic circuit CAN be realized by adopting a traditional Wire Bonding process during assembly, the packaging with low cost and high frequency response is realized, and the TO CAN packaging structure CAN be used in application scenes with higher speed.

Drawings

FIG. 1 is a schematic diagram of a current low rate (2.5G) TO base structure;

FIG. 2 is a schematic diagram of impedance simulation of a high-speed signal pin of the TO base of FIG. 1;

fig. 3 is a schematic structural view of a TO base according TO embodiment 1 of the present application;

FIG. 4 is a schematic diagram of impedance simulations of high-speed signal pins of the TO header after and before modification;

FIG. 5 is a schematic diagram of a return loss simulation of high-speed signal pins of the TO header after and before modification;

fig. 6 is a schematic structural view of a TO base according TO embodiment 2 of the present application;

fig. 7 is a schematic structural view of a TO base according TO embodiment 3 of the present application;

fig. 8 is a schematic view of the internal structure of a coaxial optoelectronic device according to embodiment 4 of the present application.

Detailed Description

The present application will now be described in detail with reference to specific embodiments thereof as illustrated in the accompanying drawings. These embodiments are not intended to limit the present application, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present application.

In the various illustrations of the present application, certain dimensions of structures or portions may be exaggerated relative to other structures or portions for ease of illustration and, thus, are provided to illustrate only the basic structure of the subject matter of the present application.

Also, terms used herein such as "upper," "above," "lower," "below," and the like, denote relative spatial positions of one element or feature with respect to another element or feature as illustrated in the figures for ease of description. The spatially relative positional terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. When an element or layer is referred to as being "on," or "connected" to another element or layer, it can be directly on, connected to, or intervening elements or layers may be present.

The coaxial packaged photoelectric device (TO CAN) structure comprises a base, a photoelectric chip and a pipe cap, wherein the base is provided with a plurality of signal pins and grounding pins, the pipe cap is provided with a lens, the photoelectric chip is installed on the base, and the pipe cap and the base form airtight packaging. The photoelectric chip is electrically connected with the signal pins and supplies power through the signal pins. The coaxial packaged photoelectric device has the advantages of small volume, low cost, easy coupling and the like, and has wide application in optical communication systems. However, since the high-speed link is complicated, the impedance is suddenly increased, and the high-frequency performance is poor, it is often used in a low-rate module of 10G or less. The structure of TO base is improved TO this application TO improve coaxial packaging device's high frequency performance, make it can use in the module of higher speed, with the cost that reduces high-speed optical module.

Example 1

As shown in fig. 3, the coaxial optoelectronic device mount 10 of this embodiment has opposite top and bottom surfaces 11 and 12, and a through hole penetrating through the top and bottom surfaces 11 and 12, a signal pin 20 is disposed in the through hole, and an insulating medium 30 is filled between the signal pin 20 and a wall of the through hole to fix the signal pin 20. Wherein, the signal pin 20 has an extension 21 higher than the top surface 11 of the base 10, the extension 21 is provided with a wire bonding plane 22 for bonding a wire to electrically connect with the optoelectronic chip, where the wire bonding plane 22 is provided at the end side of the extension 21 of the signal pin 20, and the extension 21 includes the wire bonding plane 22. In this embodiment, a heat sink 40 is also disposed on the base 10, the heat sink having a mounting plane 41 parallel to the wire bonding plane 22 for placing the optoelectronic chip, the wire bonding plane 22 facing the same direction as the mounting plane 41 of the heat sink 40. The heat sink 40 is formed integrally with the base 10, but in other embodiments, the heat sink and the base may be assembled together. The top surface 11 of the base 10 is provided with a capacitive compensation structure near the signal pin 20 TO reduce the impedance of the signal pin and improve the frequency response of the TO CAN package, so that the connection between a high-speed signal and an internal graphic circuit CAN be realized by adopting the traditional wire bonding process during assembly, the low-cost and high-frequency response package CAN be realized, and the capacitive compensation structure CAN be used in a higher-speed application scene.

The capacitive compensation structure in this embodiment is implemented by disposing a boss 13 surrounding the signal pin 20 on the top surface 11 of the base 10, filling an insulating medium 30, such as a glass medium, between the boss 13 and the signal pin 20, and forming the capacitive compensation structure by the boss 13 and the corresponding signal pin 20. In this embodiment, two high-speed signal pins 20 are provided on the base 10, the above-mentioned bosses 13 are ring-shaped columns surrounding the corresponding signal pins 20, and the bosses 13 on the periphery of each signal pin 20 may be connected with each other or may be independent of each other. In other embodiments, the number of the signal pins may also be 1 or more, ring-shaped columns surrounding the corresponding pins are respectively arranged around each signal pin, and the ring-shaped columns may be connected with each other or may be independent of each other.

As shown in fig. 4 and 5, the signal pin can be divided into a soldering section, a connecting section connected to the base, and an extension section according to the change of impedance, and from the structural point of view, as shown in fig. 3, the soldering section (not shown) is a portion of the signal pin 20 located below the bottom surface 12 of the base 10, the connecting section is a portion penetrating the base 10, and the extension section 21 is a portion higher than the top surface 11 of the base 10. The connection section connected with the base 10 can control the impedance through controlling the glass medium and the characteristic size of the coaxial structure, so that the impedance mutation is small and is close to the standard 50 ohms. The extension 21 has a higher impedance due to the lack of reference, and the impedance of the improved signal pin extension is reduced from 100 ohms to 90 ohms as shown by the dashed line in fig. 4. The lug boss and the corresponding signal pin form a capacitive compensation structure, so that the sensitivity of the extension section of the signal pin is reduced, the impedance of the lead bonding plane of the signal pin is reduced, and the bandwidth and the frequency response of the device are optimized. On the other hand, the arrangement of the boss 13 on the base 10 also means that the connection length between the signal pin 20 and the base 10 is increased, that is, the length with controllable impedance is increased, and the length of the extension section 21 of the signal pin 20 is shortened, that is, the distance between the wire bonding plane 22 and the base 10 is shortened, so that the impedance of more signal pins is controllable, the length of the impedance discontinuity is shortened, and the overall high-frequency performance of the base is optimized. The height of the projection 13 in this embodiment is preferably as high as possible, and is limited to a wire bonding tool which is lower than the height of the lower end of the wire bonding plane 22 and does not interfere with wire bonding. Here, the lower end of the wire bonding plane 22 refers to an end of the wire bonding plane 22 relatively close to the top surface 11 of the submount 10.

Example 2

As shown in fig. 6, unlike embodiment 1, the boss 13 in this embodiment is a truncated cone having a smaller outer diameter than the base 10 and concentric with the base 10, and has a height lower than the lower end of the wire bonding plane 22 of each signal pin 20, and a space 14 for avoiding a wire bonding tool at the time of wire bonding is provided on the side of the truncated cone opposite to the wire bonding plane 22 of the signal pin 20. In this embodiment, the avoiding space 14 is a chamfered notch on the circular truncated cone, and in other embodiments, the avoiding space may have other shapes as long as the avoiding space does not interfere with the lead needle tool when bonding the lead. Of course, in other embodiments, the boss may not be a concentric circular truncated cone of the base, but may be a boss of other shapes, and the height is lower than the height of the lower end of each signal pin wire bonding plane, and at the same time, does not interfere with the wire needle tool when bonding the wires.

Like embodiment 1, the boss 13 and the corresponding signal pin 20 in this embodiment form a capacitive compensation structure, which reduces the inductance of the extension 21 of the signal pin 20, thereby reducing the impedance at the wire bonding plane 22 of the signal pin 20, and optimizing the bandwidth and frequency response of the device. On the other hand, the arrangement of the boss 13 on the base 10 also means that the connection length between the signal pin 20 and the base 10 is increased, that is, the length with controllable impedance is increased, and the length of the extension section 21 of the signal pin 20 is shortened, that is, the distance between the wire bonding plane 22 and the base 10 is shortened, so that the impedance of more signal pins is controllable, the length of the impedance discontinuity is shortened, and the overall high-frequency performance of the base is optimized. The height of the projection 13 in this embodiment is preferably as high as possible, and is limited to a wire bonding tool which is lower than the height of the lower end of the wire bonding plane 22 and does not interfere with wire bonding.

Example 3

As shown in fig. 7, unlike embodiments 1 and 2, the capacitive compensation structure in this embodiment is implemented by providing a protrusion 14 on the top surface 11 of the base 10, the protrusion 14 having a side surface facing the signal pin 20, and an insulating pad 50 between the side surface and the signal pin 20. The bump 14, the insulating pad 50 and the corresponding signal pin 20 form a capacitive compensation structure, that is, capacitive induction is formed between the signal pin 20 and the bump 14, so that the inductance of the extension 21 of the signal pin 20 is reduced, the impedance at the wire bonding plane 22 is reduced, and the bandwidth and the frequency response of the device are optimized.

In this embodiment, a conductive block 60 is disposed between the insulating pad 50 and the signal pin 20, the conductive block 60 is electrically connected to the signal pin 20, and the protrusion 14, the insulating pad 50 and the conductive block 60 form a capacitive compensation structure. The conductive bumps 60 have larger sides and can form a larger capacitive inductance with the bumps 14, which can lower the impedance at the wire bonding plane 22 of the signal pins 20 more, further improving the bandwidth and frequency response of the device. In this embodiment, the conductive bumps 60 are solder bumps, and have good conductivity with the signal pins 20, and the process is simple. In other embodiments, the conductive block may be made of other conductive materials.

The top surface 11 of the base 10 shown in fig. 7 is further provided with a heat sink 40, the protrusion 14 is connected with the heat sink 40 and is located at one side of the two signal pins 20, and the base 10, the protrusion 14 and the heat sink 40 are of an integrated structure. In other embodiments, the protrusion may be located in the middle of the two signal pins, and have two side surfaces facing the two signal pins respectively. Alternatively, separate bumps and insulating pads may be provided on the side edges of the signal pins, respectively, as long as the lead pins do not interfere with the bonding of the leads. Of course, in other embodiments, the number of signal pins may be 1 or more. The wire bonding plane 22 is located at the side of the extension 21 of the signal pin 20, and when the above capacitive compensation structure is located at the other side of the extension 21 outside the wire bonding plane 22, the height of the capacitive compensation structure may be equal to or less than the height of the extension 21, so that a greater capacitive induction is formed between the signal pin 20 and the bump 14, thereby greatly reducing the inductance of the extension 21 of the signal pin 20, reducing the impedance at the wire bonding plane 22, and greatly optimizing the bandwidth and frequency response of the device.

Example 4

As shown in fig. 8, this embodiment provides a coaxial optoelectronic device comprising an optoelectronic chip 70, a substrate 80, and the coaxial optoelectronic device mount of any of the above embodiments. The top surface 11 of the base 10 is provided with a heat sink 40, the substrate 80 is disposed on the heat sink 40 of the base 10, the optoelectronic chip 70 is disposed on the substrate 80 and electrically connected to the substrate 80, and the substrate 80 is electrically connected to the signal pins 20 through bonding wires 90. Specifically, the optoelectronic chip 70 is electrically connected to the pattern circuit on the substrate 80 through a bonding wire, and the bonding wire is bonded to the pattern circuit on the substrate 80 from the wire bonding plane 22 of the extension 21 of the signal pin 20, so as to realize the signal transmission from the signal pin 20 to the substrate 80. Here, the bonding wire 90 is a gold wire having excellent conductivity, and in other embodiments, other conductive metal wires such as a copper wire or an aluminum wire may be used. Compared with the traditional 25G TO with high bandwidth, the coaxial photoelectric device can realize the connection of high-speed signals and an internal graphic circuit by adopting the traditional lead bonding process, does not need a complex welding process and realizes low-cost interconnection; meanwhile, compared with a traditional 2.5G TO device, the high-frequency performance is improved, and an application scene with higher speed can be realized.

The above list of details is only for the concrete description of the feasible embodiments of the present application, they are not intended to limit the scope of the present application, and all equivalent embodiments or modifications that do not depart from the technical spirit of the present application are intended to be included within the scope of the present application.