Simplified process flow method for manufacturing vertical cavity surface emitting laser
阅读说明：本技术 一种制造垂直腔面发射激光器的精简工艺流程方法 (Simplified process flow method for manufacturing vertical cavity surface emitting laser ) 是由 翁玮呈 丁维遵 刘嵩 梁栋 于 2019-12-26 设计创作，主要内容包括：本发明提供了一种制造垂直腔面发射激光器的精简工艺流程方法,相对于传统的VCSEL制造方法,本制造方法将P型欧姆接触金属与阳极焊盘金属结合为一次光刻工艺,可以实现完整包覆发光平台侧壁或者完整填埋为氧化刻蚀而制作的沟道,形成有效连接P电极金属层;同时,由于金属是连续的,器件的散热不受影响。这个制作工艺将原本需要多次光刻的工艺凝缩成一张光罩实现,在VCSEL量产制造中形成成本优势。最后,P和N电极金属层可以共享一次退火工艺同时实现良好的欧姆连接。(The invention provides a simplified process flow method for manufacturing a vertical cavity surface emitting laser, compared with the traditional VCSEL manufacturing method, the manufacturing method combines P-type ohmic contact metal and anode bonding pad metal into a one-time photoetching process, can realize complete cladding of the side wall of a light-emitting platform or complete burying of a channel manufactured for oxidation etching to form an effective connection P electrode metal layer, and meanwhile, because the metal is continuous, the heat dissipation of a device is not influenced. The manufacturing process condenses the process which originally needs multiple times of photoetching into a photomask to realize, and forms cost advantage in VCSEL mass production. Finally, the P and N electrode metal layers may share an annealing process while achieving good ohmic connections.)
1. A simplified process flow method for manufacturing a vertical cavity surface emitting laser is characterized in that: the method specifically comprises the following steps:
1) preparing a semiconductor epitaxial layer structure of a VCSEL device, and performing first chemical deposition to form a first passivation layer;
2) etching the epitaxial layer structure to form a channel or a light-emitting mesa structure;
3) exposing the oxide layer by using the channel to define a corresponding light-emitting region;
4) performing second chemical deposition to form a second passivation layer, etching the passivation layer between the inner part of the edge of the table top in the horizontal direction and the outer part of the light-emitting region to form a P-type ohmic contact region, and etching the first passivation layer and the second passivation layer of the cutting channel to form a unit chip region;
5) defining a P-type ohmic contact metal on the second passivation layer by photoetching, and plating a plurality of layers of P-type ohmic metal to form a P-electrode metal layer;
6) plating an N electrode metal layer under the N type substrate;
the P-type ohmic contact metal is used as the anode pad metal by adjusting the thickness of the P-type ohmic contact metal.
2. A simplified process flow method for fabricating a vertical cavity surface emitting laser as claimed in claim 1 wherein: the semiconductor epitaxial layer structure comprises a P-type distributed Bragg reflector, a quantum well layer, an N-type distributed Bragg reflector, an N-type substrate layer, a P electrode metal layer and an N electrode metal layer.
3. A simplified process flow method for fabricating a vertical cavity surface emitting laser as claimed in claim 2 wherein: the material of the P-type distributed Bragg reflector and the N-type distributed Bragg reflector is selected from one or more of Al, Ga, As, In and P element compounds, or one or more of Si, N, O and Al element forming dielectrics, the material of the quantum well layer is selected from one or more of Ga, Al, In, As, P and N element compounds, and the material of the P electrode metal layer and the N electrode metal layer is selected from one or more of Ti, Pt, Au, Pd, Ge and Ni metals.
4. A simplified process flow method for fabricating a vertical cavity surface emitting laser as claimed in claim 1 wherein: the formation of the oxide layer utilizes a wet oxidation process.
5. A simplified process flow method for fabricating a vertical cavity surface emitting laser as claimed in claim 1 wherein: the oxide layer is formed and then passivated and electrically isolated by means of ion implantation.
6. A simplified process flow method for fabricating a vertical cavity surface emitting laser as claimed in claim 1 wherein: the first passivation layer material and the second passivation layer material are selected from one or more of Si, N, O and Al elements which form a dielectric medium.
7. A simplified process flow method for fabricating a vertical cavity surface emitting laser as claimed in claim 1 wherein: the P-type ohmic metal is formed by evaporation, sputtering, electroplating or electroless plating techniques.
8. A simplified process flow method for fabricating a vertical cavity surface emitting laser as claimed in claim 1 wherein: and adjusting the thickness of the N-type ohmic contact metal, and using the N-type ohmic contact metal as cathode pad metal.
Technical Field
The invention relates to the technical field of Vertical Cavity Surface Emitting Lasers (VCSELs), in particular to a simplified process flow method for manufacturing a VCSEL.
Background
Vertical cavity surface emitting lasers are of interest for their excellent performance and wide application. High production efficiency is required to achieve low manufacturing costs, and thus the method for manufacturing is strictly controllable. After a P electrode metal layer is manufactured by a conventional process through a photomask, two to three layers of photomasks are required to be added, then a thicker Au layer is plated, and a bonding pad is manufactured and connected with the P electrode metal layer. The long process time, the need of multiple photomasks and the large amount of metal material are the problems faced at present. Etching the passivation layer and GaAs requires a photomask to define the area of the light-emitting platform, and thus it takes a long time to etch the passivation layer and GaAs wafer using two different parameters, even two different machines. A light shield is needed to remove the film on the cutting channel, so that the component itself is not damaged by the film during the cutting process. The substrate is thinned and another substrate must be used for wafer lamination to protect the front side and facilitate wafer transfer or backside processing, but the thinning process involves a high risk of chipping, so any handling of the thin wafer requires great care. After the N electrode metal layer is plated on the back surface of the wafer, a thicker Au stack needs to be plated, and the GaAs substrate is prevented from being damaged in the use process of the assembly. The P electrode metal layer and the N electrode metal layer are respectively manufactured through annealing, and a good ohmic connection effect can be obtained. Statistics shows that the main process type is larger than 11 procedures, the number of photomasks is larger than 7, the plating times is larger than 5 times, a substrate needs to be thinned, the average total process working hour is larger than 3 weeks, the basic condition of the mainstream process is achieved, and the technical problem that the time and the cost are further required to be reduced in the field is also solved urgently.
Disclosure of Invention
In view of the above technical problems in the prior art, the present invention provides a simplified process flow method for manufacturing a vertical cavity surface emitting laser, which can be implemented by a single metal layer (P or N electrode metal layer) on the front or back surface through a photomask, thereby further reducing the production cost. The method comprises the following steps:
1) preparing a semiconductor epitaxial layer structure of a VCSEL device, and performing first chemical deposition to form a first passivation layer;
2) etching the epitaxial layer structure to form a channel or a light-emitting mesa structure;
3) exposing the oxide layer by using the channel to define a corresponding light-emitting region;
4) performing second chemical deposition to form a second passivation layer, etching the passivation layer between the inner part of the edge of the table top in the horizontal direction and the outer part of the light-emitting region to form a P-type ohmic contact region, and etching the first passivation layer and the second passivation layer of the cutting channel to form a unit chip region;
5) defining a P-type ohmic contact metal on the second passivation layer by photoetching, and plating a plurality of layers of P-type ohmic metal to form a P-electrode metal layer;
6) plating an N electrode metal layer under the N type substrate;
the P-type ohmic contact metal is used as the anode pad metal by adjusting the thickness of the P-type ohmic contact metal.
In the case of a back-emitting device, the N-type ohmic contact region needs to be patterned to emit light from the N-type region, and the above method is also applicable.
For the cutting path, whether the process is executed or not can be selected according to the product requirements, and if the epitaxial characteristics are verified, the process can be skipped, so that the effects of saving the cost and shortening the period can be directly achieved.
The epitaxial layer structure is etched to form channels, namely, a single continuous channel or a plurality of discontinuous channels can be arranged around each light-emitting point, or a light-emitting mesa structure and the like are formed.
A certain margin can be left on two sides of the table top in the horizontal direction to contain the precision of the process, and the whole or part of the margin is etched to form a P electrode metal layer contact surface area.
In the execution process of the method, a photomask is used, the metal cladding performance of the side wall of the platform is improved by adjusting the thickness of the P-type ohmic contact metal or the angle of plating metal, and the P-type ohmic contact metal is used as anode bonding pad metal, so that the related anode bonding pad metal process is omitted; and selectively defining the P electrode metal layer by using evaporation, sputtering, electroplating or chemical plating technologies and the like according to the product design and the appearance processing requirements of different patterns, for example, selecting the last metal layer of the P electrode metal layer as an Au metal layer according to products with different powers, and adjusting the thickness of the last Au metal layer, wherein the Au metal layer needs to be thicker if the products are high-power products, and can be thinner if the products are low-power and short-pulse products. The method does not need a plurality of light masks, and further adjusts the metal consumptive materials and the process period.
The thickness of the P-type ohmic contact metal is adjusted, the P-type ohmic contact metal is used as the anode bonding pad metal, namely the P-type ohmic contact metal and the anode bonding pad metal are combined into one-time process treatment, and the cladding performance of the process treatment is the same as that of the original standard process. The method not only reduces the number of light masks and the process procedures, but also shortens the process time and adjusts the metal usage amount.
Preferably, the semiconductor epitaxial layer structure comprises a P-type distributed bragg reflector, a quantum well layer, an N-type distributed bragg reflector, an N-type substrate layer, a P-electrode metal layer and an N-electrode metal layer.
Preferably, the materials of the P-type distributed Bragg reflector and the N-type distributed Bragg reflector are selected from one or more of Al, Ga, As, In and P element compounds, or Si, N, O and Al elements form one or more of dielectrics, the materials of the quantum well layer are selected from one or more of Ga, Al, In, As, P and N element compounds, and the materials of the P electrode metal layer and the N electrode metal layer are selected from one or more of Ti, Pt, Au, Pd, Ge and Ni metals.
The specific material of the P-type distributed Bragg reflector and the N-type distributed Bragg reflector can be AlGaAs/GaAs, and the material of the quantum well layer can be GaAs/InGaAs/InGaP/AlGaInP/AlGaInAsP/InGaAlAs, etc.
Preferably, the oxide layer is formed by a wet oxidation process, and the corresponding light emitting region may also be defined by an ion implantation process instead of the wet oxidation process.
Preferably, the oxide layer is formed and then passivated and electrically isolated by ion implantation.
Preferably, the first passivation layer material and the second passivation layer material are selected from one or more of Si, N, O and Al elements forming a dielectric.
The specific material of the first passivation layer and the second passivation layer may be SiN, SiO, SiON, or the like.
Preferably, the P-type ohmic metal is formed using evaporation, sputtering, electroplating or electroless plating techniques.
Preferably, the thickness of the N-type ohmic contact metal is adjusted, and the N-type ohmic contact metal is used as the cathode pad metal.
For a substrate removal process similar to scribe lines, products that are validated at low power, low conversion efficiency and epitaxial wafers may not require a substrate removal process, and high power may choose whether to omit this process as desired. As a result of practical verification, it was found that there was no difference in the characteristics at normal temperature.
Under certain conditions, the thickness of the N-type ohmic contact metal is adjusted, the N-type ohmic contact metal is used as cathode pad metal, namely the protection effect same as that of a standard process can be achieved by plating Au on the last layer, usually, the last metal layer of the N electrode metal layer is selected as an Au metal layer, and the thickness of the Au metal layer can be adjusted according to products with different powers. If the back needs to define the luminous zone, only one photomask is needed to be manufactured and the one-time metal plating process is needed to be carried out, and the effects of saving the cost and shortening the period can be achieved by integrating various requirements.
In the execution process of the method, a substrate removing process can be omitted, so that the wafer transmission and the process thereof can be executed more easily, the wafer is not easy to break, and the wafer has the characteristics similar to those of a thinned thin wafer, so that the time and the cost are saved.
The thickness of the N-type ohmic contact metal is adjusted, the N-type ohmic contact metal is used as cathode pad metal, namely the N-electrode metal layer and the cathode pad metal are combined into a one-time process, the last metal layer of the N-electrode metal layer is usually selected as an Au metal layer, the thickness of the last Au layer can be adjusted to meet the requirements of testing and packaging, the assembly cannot be damaged, and time can be saved. Under the conditions of high-quality epitaxial wafer or low performance, low requirement on appearance processing and the like, the first passivation layer is not needed, the wet/dry etching method is directly used for etching and defining the light emitting platform area, and the time for etching the passivation layer is saved.
How to save the cost is the problem that all products will meet and is the ultimate goal in the industry, and the method provided by the invention is no matter in the laser components of sensing, medical treatment, industrial use, communication, quantum computer, distance measurement, security protection and the like; the single laser, the array laser, the speckle laser and the like in the design of the component can be selected and applied according to requirements.
The beneficial effects of the invention at least comprise:
1. the method not only reduces the number of photomasks and process procedures, but also shortens the process time by a large margin and adjusts the metal usage amount.
2. For the condition of rapid verification or low requirement on the appearance processing, the substrate removing process can be omitted, thereby saving the number of photomasks and the process time.
3. The N-type ohmic contact metal and the cathode bonding pad metal are combined into a one-step process, an electroplating process is omitted, and the thickness of the last layer of the N electrode metal layer is directly adjusted according to product requirements.
4. Proper temperature and time matching for different electrodes is often critical and specific requirements are imposed for good ohmic connections. In the implementation process of the method, the P electrode metal layer and the N electrode metal layer can achieve good ohmic connection by using similar annealing temperature and only needing to implement an annealing process once, so that the process is simplified, and the manufacturing time is reduced.
Drawings
FIG. 1 is a schematic illustration of dielectric film deposition.
Fig. 2 is a schematic diagram of mesa dry/wet etch and oxidation.
FIG. 3 is a schematic diagram of SiN deposition and etch streets.
Figure 4 is a schematic view of metallization.
Figure 5 is a schematic top view of a single VCSEL device.
Fig. 6-7 are schematic top views of various arrangements of multiple VCSEL devices.
(1) The light emitting diode comprises a first passivation layer, (2) a P-DBR layer, (3) a quantum well layer, (4) an N-DBR layer, (5) an N-type substrate layer, (6) an oxide layer, (7) a channel, (8) a second passivation layer, (9) a P-type ohmic contact region, (10) a P electrode metal layer, (11) a light emitting region, (12) an N electrode metal layer, (13) a mesa and light emitting region, and (14) a cutting path.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of the present invention.
The invention provides a simplified process flow method for manufacturing a vertical cavity surface emitting laser, which comprises the following steps:
as shown in fig. 1, a semiconductor epitaxial layer structure of a VCSEL device is prepared, which includes a P-
As shown in fig. 2, the mesa structure of the VCSEL unit and the
As shown in fig. 3, a second chemical deposition is performed to form a
As shown in fig. 4, the P-
The N electrode metal layer and the cathode bonding pad metal are combined into a one-time process, the last metal layer of the N electrode metal layer is selected as an Au metal layer, the requirements of testing and packaging can be met by adjusting the thickness of the last Au metal layer, the assembly cannot be damaged, and time saving and metal consumable adjustment can also be achieved.
Thus, a complete VCSEL device is formed.
Process flow
Power (W)
Voltage (V)
Energy conversion efficiency (%)
Threshold current (A)
Simplified process
1.25
2.66
33.48
0.21
Simplified process
1.22
2.61
33.22
0.22
Conventional flow scheme
1.23
2.57
33.78
0.21
As can be seen from the comparison table of various performances of the experiment, the VCSEL device prepared by the process has little difference in various performances with the VCSEL device prepared by the traditional process.
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