阅读说明：本技术 一种垂直腔面发射激光器及其密集型阵列结构 (Vertical cavity surface emitting laser and intensive array structure thereof ) 是由 李明欣 杨旭 张岩松 于 2019-07-05 设计创作，主要内容包括：一种垂直腔面发射激光器及其密集型阵列结构,包括隔离层：其包括圆形部分和从圆形部分的圆周向外延伸的一个或多个延伸部分；P-型金属层：其包括一个或多个分离的不规则形状部分,不规则形状部分由近似矩形的外侧部分和近似梯形的内侧部分组成,隔离层的延伸部分完全或部分覆盖P-型金属层；一个或多个电介质通孔开口：其分别位于P-型金属层的一个或多个不规则形状部分之上；多个氧化槽：多个氧化槽沿隔离层的圆形部分的圆周外间隔排布且于隔离层的延伸部分两侧,相邻两延伸部分之间分布有至少一个氧化槽。本发明在缩小VCSEL芯片尺寸的同时不影响VCSEL芯片性能,并提升现有垂直腔面发射激光器(VCSEL)阵列的密集程度。(A vertical cavity surface emitting laser and a dense array structure thereof, comprising an isolation layer: comprising a circular portion and one or more extensions extending outwardly from the circumference of the circular portion; p-type metal layer: the isolation layer comprises one or more separated irregular-shaped parts, wherein each irregular-shaped part consists of an approximately rectangular outer part and an approximately trapezoidal inner part, and the extending part of the isolation layer completely or partially covers the P-type metal layer; one or more dielectric via openings: respectively located over one or more irregularly shaped portions of the P-type metal layer; a plurality of oxidation tanks: the oxidation tanks are arranged at intervals along the circumference of the circular part of the isolation layer and are arranged on two sides of the extension part of the isolation layer, and at least one oxidation tank is distributed between two adjacent extension parts. The invention reduces the size of the VCSEL chip without influencing the performance of the VCSEL chip and improves the density of the existing Vertical Cavity Surface Emitting Laser (VCSEL) array.)

1. A vertical cavity surface emitting laser, comprising:

isolation layer: comprising a circular portion and one or more extensions extending outwardly from the circumference of the circular portion;

p-type metal layer: comprising one or more discrete irregularly shaped portions, the extended portion of the spacer layer completely or partially covering the irregularly shaped portion of the P-type metal layer;

one or more dielectric via openings: one or more of the dielectric via openings are respectively located over one or more of the irregularly shaped portions of the P-type metal layer;

a plurality of oxidation tanks: the oxidation grooves are arranged at intervals along the circumference of the circular part of the isolation layer and are arranged on two sides of the extension part of the isolation layer, and at least one oxidation groove is distributed between every two adjacent extension parts.

2. A vertical cavity surface emitting laser according to claim 1, wherein said width of said vertical cavity surface emitting laser is between 15 microns and 28 microns.

3. A vertical cavity surface emitting laser according to claim 1, wherein an inner portion of said irregular shape portion of said P-type metal layer extends to both sides to form a shape of a partial circular ring.

4. A vertical cavity surface emitting laser according to claim 1, wherein each of said oxidation grooves is irregular in shape, and two adjacent oxidation grooves having no said extension portion in between are connected together.

5. A vertical cavity surface emitting laser according to claim 1, wherein said isolation layer completely covers said dielectric via opening.

6. A vertical cavity surface emitting laser according to claim 1, wherein the number of irregularities of said metal layer is equal to the number of said dielectric via openings and extensions of said isolation layer.

7. A vertical cavity surface emitting laser according to claim 1, wherein the number of said oxidation grooves is not equal to the number of irregularities of said metal layer.

8. A vertical cavity surface emitting laser according to claim 1, wherein the number of said irregularities of said metal layer is one, two, three or four.

9. A vertical Cavity surface emitting laser according to claim 1 wherein the metal layer, the dielectric via openings and the extensions of the spacer layer are all equally or unequally spaced around the circumference of the circular portion.

10. A dense array structure of lasers, comprising:

a plurality of vertical cavity surface emitting lasers as claimed in any of claims 1-9, said plurality of vertical cavity surface emitting lasers being arranged in an array.

Technical Field

The invention relates to the field of vertical cavity surface emitting lasers, in particular to a vertical cavity surface emitting laser and a dense array structure thereof.

Background

A Vertical-Cavity Surface-Emitting Laser (hereinafter referred to as VCSEL) is a semiconductor Laser with a Laser beam Emitting direction perpendicular to a substrate Surface, and its main structure includes a bottom reflector, an active region, and a top reflector. To achieve photoelectric conversion, P-type and N-type metal layers need to be deposited on the top and bottom of the VCSEL, respectively, to facilitate current injection. In addition, the vertical light Emitting direction of the VCSEL is one of the main features distinguished from an Edge-Emitting Laser (Edge-Emitting Laser). The VCSEL invention was in 1977 and has long been the subject of academic research and has not been widely used in industrial manufacturing. In 1994, professor Dennis decappe from the united states and its group creatively applied oxidation technology to VCSELs, i.e., formed oxide apertures in VCSELs to limit optical field and current, thereby greatly improving various aspects of performance and reliability of VCSELs, making mass production of VCSELs possible. The oxidized VCSEL is the most important type of commercially available VCSEL, and is widely applied to industrial and consumer fields such as optical communication, 3D sensing, infrared illumination, and the like. The primary advantages of VCSELs are low power consumption, high photoelectric conversion efficiency, and in addition, their ease of optical field coupling, ease of array integration, and ease of on-wafer testing make them amenable to low cost fabrication. The manufacturing process of the VCSEL is roughly a structure design, epitaxial growth, process processing, wafer test, and the like. In order to achieve uniform oxide aperture, a plurality of critical steps such as structure design, epitaxial growth, and process processing need to be designed specifically. In terms of process, the typical implementation is to form a pillar step by dry etching and then form an oxide aperture by an oxidation process of lateral oxidation. This embodiment does not facilitate further increasing the density of the VCSEL array, thereby reducing the VCSEL chip size.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides a vertical cavity surface emitting laser and an intensive array structure thereof, which aims to improve the density of the existing Vertical Cavity Surface Emitting Laser (VCSEL) array, and not affect the VCSEL chip performance while reducing the VCSEL chip size. The technical scheme of the invention is as follows:

as a first aspect of the present invention, there is provided a vertical cavity surface emitting laser including:

isolation layer: comprising a circular portion and one or more extensions extending outwardly from the circumference of the circular portion;

p-type metal layer: comprising one or more discrete irregularly shaped portions, the extended portion of the spacer layer completely or partially covering the irregularly shaped portion of the P-type metal layer;

one or more dielectric via openings: one or more of the dielectric via openings are respectively located over one or more of the irregularly shaped portions of the P-type metal layer;

a plurality of oxidation tanks: the oxidation grooves are arranged at intervals along the circumference of the circular part of the isolation layer and are arranged on two sides of the extension part of the isolation layer, and at least one oxidation groove is distributed between every two adjacent extension parts.

Further, the width of the VCSEL is between 15 and 28 microns.

Further, the inner portions of the irregularly shaped portions of the P-type metal layer extend to both sides to form the shape of a partial circular ring.

Further, a plurality of the oxidation grooves are irregularly shaped, and two adjacent oxidation grooves having no extension portion in the middle are connected together.

Further, the isolation layer completely covers the dielectric via opening.

Further, the number of irregularities of the metal layer is equal to the number of the dielectric via openings and the extension portions.

Further, the number of the oxidation grooves is not equal to the number of the irregular portions of the metal layer.

Further, the number of the irregular parts of the metal layer is one, two, three or four.

Further, the metal layer, the dielectric via openings and the extended portions of the isolation layer are distributed at equal or unequal intervals around the circumference of the circular portion.

As a second aspect of the present invention, there is provided a dense array structure of lasers, comprising:

a plurality of vertical cavity surface emitting lasers as described in any of the above, said plurality of vertical cavity surface emitting lasers being arranged in an array.

The invention has the beneficial effects that:

the invention improves the existing Vertical Cavity Surface Emitting Laser (VCSEL), does not affect the performance of a VCSEL chip while reducing the size of the VCSEL chip, and improves the density of the existing Vertical Cavity Surface Emitting Laser (VCSEL) array.

Drawings

FIG. 1 is a top plan view of a first VCSEL provided in an embodiment of the invention;

FIG. 2 is a top plan view of a second VCSEL provided in an embodiment of the invention;

FIG. 3 is a top plan view of a third VCSEL provided in an embodiment of the invention;

FIG. 4 is a top plan view and a side cross-sectional view of a first VCSEL provided in accordance with an embodiment of the present invention;

FIG. 5 is a top plan view and another side cross-sectional view of a first VCSEL provided in accordance with an embodiment of the present invention;

FIG. 6 is a top plan view of a fourth type of VCSEL provided in accordance with an embodiment of the present invention;

FIG. 7 is a top plan view of a fifth type of VCSEL provided in an embodiment of the invention;

FIG. 8 is a top plan view of a sixth VCSEL provided in accordance with an embodiment of the invention;

FIG. 9 is a top plan view of a dense array of lasers according to an embodiment of the present invention;

fig. 10 is a top plan view of another dense array structure of lasers according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The present invention is directed to a compact VCSEL and also to a compact VCSEL array. Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may refer to the same or similar features, elements or components throughout the different views. The embodiments described below are only examples, and not all embodiments. Fig. 1-10 are not drawn to scale and are merely intended to illustrate the principles and concepts of the invention so as to enable one of ordinary skill in the art to practice the embodiments.

With the widespread use of VCSEL array chips in consumer electronics, one major requirement for VCSEL chips is to reduce chip size. One important indicator that affects the size of a VCSEL chip is the density of the VCSELs within the array, and the main factors that affect the density of VCSELs include the size of the annular dielectric opening in the isolation layer, the size of the annular P-type metal layer, the size of the isolation layer, the size of the annular oxidation trench that forms the oxide aperture, and the relative positions of these major elements. For a common columnar step-type VCSEL, a cylinder is etched by a dry method or a wet method and then oxidized by an oxidation process to realize an oxidized aperture, and a dielectric opening, a P-type metal layer and an isolation layer of the columnar step-type VCSEL are all positioned in a circular truncated cone at the top of the pillar. Due to the limitations of the fabrication process, the column size of the columnar stepped VCSEL needs to be large enough to sequentially deploy the lower dielectric opening, the P-type metal layer, and the isolation layer, which limits the minimum spacing between adjacent VCSELs, and thus limits the density of the VCSEL array.

In the above embodiment, the width of a typical single VCSEL, i.e. the outer diameter of the ring-shaped oxidation trench, is about 30 microns to 50 microns, and further reducing the size of the cylinder of the stepped VCSEL may seriously affect the performance of the VCSEL, for example, the output power, the laser optical field distribution, the reliability, etc. are affected.

In view of the above problems, embodiments of the present invention provide a VCSEL and a dense VCSEL array design, which can overcome the size limitation of the existing VCSEL without sacrificing the performance of the VCSEL chip. The main idea of the embodiment of the invention is to convert the ring-shaped metal, the ring-shaped dielectric opening and the ring-shaped oxidation groove of the typical stepped VCSEL into separate units, and then fully utilize the gap between the adjacent VCSELs through some possible arrangement modes, so as to reduce the pitch between the adjacent VCSELs, thereby improving the density of the VCSEL array.

Fig. 1 and 2 respectively show top views of two examples of VCSEL designs for a dense VCSEL array. As shown in fig. 1, the VCSEL100 is one possible implementation for a dense VCSEL, which includes: an isolation layer 106, wherein the isolation layer 106 comprises a central approximately circular portion and one or more extending portions extending from a circumference of the approximately circular portion; a P-type metal layer 102 comprising one or more discrete irregularly shaped portions, divided into outer and inner portions, arranged along the circumference of the central approximately circular portion of isolation layer 106, in a position such that isolation layer 106 may completely or partially cover metal layer 102; a passivation layer comprising one or more dielectric via openings 104, said dielectric via openings 104 being positioned above the metal layer 102, arranged such that the dielectric via openings 104 are completely contained within the outline of the metal layer 102, and such that the isolation layer 106 completely covers the dielectric via openings 104, thereby ensuring that current can be injected into the metal layer after electrical polarization without leaking out of the isolation layer coverage area; a plurality of oxidation baths 108, which according to a possible embodiment have an irregular shape, are positioned approximately equally spaced along the circumference of the central approximately circular portion of the isolation layer 106, and may be placed completely or partially between the metal layer 102 and the extended portion of the isolation layer 106. As shown in fig. 1, the width W of the densely packed VCSELs, i.e., the distance from the outer edge of the oxidation trench 108 to the outer edge of the opposite oxidation trench 108, is between 15 microns and 28 microns.

Fig. 2 illustrates another possible embodiment of a dense VCSEL, in which one or more (which may include two, three, or four) inner portions of the metal layer 102 extend along the circumferential direction of the circular portion to two sides, and the extending portions may or may not be connected to adjacent extending portions, thereby forming a partial ring shape as a whole. Due to the presence of the circumferentially extending portion of metal layer 102, oxidation trench 108 is forced axially outward so that it does not coincide with the metal layer, resulting in a slight increase in width W 'of the VCSEL (W' > W), which is approximately between 18-32 microns in size.

Fig. 3 illustrates another possible dense VCSEL embodiment in which one or more of the oxidation trenches 108 may extend laterally to connect with adjacent oxidation trenches 108 to form an arch.

As shown in fig. 1, 2 and 3, the oxide apertures 110 are formed by an oxidation process, and have a shape determined by the inner profile of the plurality of oxidation grooves 108 and the uniformity of the oxidation process, and generally have an irregular pattern of approximately circular shape.

The process of fabricating the VCSEL may include one or more epitaxial growth processes, one or more metal deposition processes, one or more passivation layer deposition processes, one or more oxidation trench etching processes, one or more ion implantation processes, and the like. The cross-section of a completed VCSEL is shown in fig. 4 and 5, cross-section 250 is a cross-section through a pair of oxidation trenches 108 (as shown by the "X-X" lines), and cross-section 300 is a cross-section through a pair of dielectric via openings 104 (as shown by the "Y-Y" lines). A Vertical Cavity Surface Emitting Laser (VCSEL)100 includes a dielectric passivation layer 112, a P-type metal layer 102 (shown in fig. 5), an isolation layer 106, a top reflective layer 116, an oxide layer 120, an active region 114, a bottom reflective layer 124, a base layer 118, and an N-type metal layer 126. The cross-section of fig. 4 does not pass through metal layer 102 and via opening 104, and is therefore not shown in fig. 4.

As shown in fig. 4 and 5, an N-type metal layer is plated on the bottom of the base layer 118 to form a cathode. The base layer 118 may include a base underlayer material and a semiconductor material grown by epitaxy. The bottom reflective layer 124 is above the base layer 118 and may include a Distributed Bragg Reflector (DBR). Active region 114 is above bottom reflective layer 124 and may include quantum wells and spacers to confine electrons and holes to facilitate recombination and emission of photons. Above the active region 114 is a top reflective layer 116, which may include a Distributed Bragg Reflector (DBR). An oxide layer 120 is located in the top reflective layer 116 near the active region 114 to confine the optical field and current to improve VCSEL performance (e.g., photoelectric conversion efficiency, optical power). The formation mechanism of the oxide layer 120 is to convert the transparent AlAs or AlGaAs in the original epitaxial layer into the opaque Al2O3 by an oxidation process, and the conversion direction is to diffuse inward from the oxidation trench 108, so as to finally form an approximately circular irregular aperture, i.e. the oxide aperture 110. Isolation layer 106 may extend to the edge of P-type metal layer 102 (as shown in fig. 5), may be used to isolate current, and may be implemented by ion implantation. Above the top reflective layer 116 is a P-type metal layer 102 (shown in fig. 5) to form an anode from which current is injected down, through the oxide apertures, and out the cathode. Dielectric passivation layer 112 is over top reflective layer 116 and P-type metal layer 102 for protection. As shown in fig. 5, via opening 104 is above P-type metal layer 102 for accessing current. Upon application of an electrical current, the excited photons may be emitted through the light emitting aperture 122 (shown in FIG. 5) under appropriate conditions. It is noted that fig. 4-5 illustrate only an embodiment of a dense VCSEL as an example, and that one or more P-type or N-type metal layers, one or more passivation layers, one or more oxide layers may be used according to some possible embodiments.

According to some possible embodiments, the number of the plurality of irregular portions of the metal layer, the number of the via openings, and the number of the isolation layer extensions may be three, two, and one, as shown in fig. 6, 7, and 8, respectively. The number of irregularities of the P-type metal layer, the number of dielectric via openings and the number of isolation layer extensions of the VCSEL350 in the example shown in figure 6 are all three. According to some possible embodiments, the metal layer inner portion may extend to both sides in the circumferential direction to form a partial ring shape. The number of irregularities of the P-type metal layer, the number of dielectric via openings, and the number of isolation layer extensions of the exemplary VCSEL400 shown in fig. 7, in which the metal layer inside part has been extended circumferentially to both sides to form a partial ring shape, are all two. According to some possible embodiments, the metal layer may also be a plurality of discrete irregularities. The number of irregularities of the P-type metal layer, the number of dielectric via openings, and the number of isolation layer extensions of the exemplary VCSEL450 shown in fig. 8, in which the metal layer inside part has been extended circumferentially to both sides to form a partial ring shape, is one. According to some possible embodiments, the metal layer may also be a single irregular part.

According to some possible embodiments, the plurality of separated portions of the metal layer, the plurality of extended portions of the isolation layer, and the plurality of oxidation grooves in the VCSEL may be uniformly or non-uniformly distributed along a circumference of an approximately circular shape at a center of the isolation layer. VCSELs for dense designs may be arranged in a VCSEL array in some possible embodiments, which may include regular and irregular arrangements, as shown in fig. 9 and 10, respectively. By regularly arranged VCSEL arrays, all adjacent nearest VCSELs in a VCSEL array have equal center-to-center spacing, e.g. close-packed regular hexagons, trapezoids, triangles, etc. By non-regularly arranged VCSEL arrays, it is meant that not all adjacent nearest VCSELs in a VCSEL array have the same center-to-center spacing.

One possible regular VCSEL array 500 is shown in fig. 9, in which each VCSEL can be a dense VCSEL as described in the present invention, and only VCSEL100 is illustrated as an example. In order to fully utilize the space between the VCSELs to increase the density of the VCSEL array and thus reduce the size of the VCSEL chip, it is possible by some embodiments that adjacent VCSELs may fully or partially share one or more oxidation trenches, P-type metal layers, isolation layers, or via openings, as shown in fig. 9. It should be noted that the shape of the shared oxidation trench is irregular, and the shape of the shared oxidation trench may also vary according to the center-to-center spacing of adjacent VCSELs.

Fig. 10 shows a possible non-regular arrangement of VCSEL arrays 550, where each VCSEL can be a dense VCSEL as described in the present invention, and shows a mixture of VCSELs 100 and 300 as an example, but not intended to represent all possible embodiments. According to some possible embodiments, the irregular arrangement of VCSEL arrays may have a greater density of VCSELs in some regions than in other regions, and the dense VCSELs of the present invention can solve the problem of the local region density being too high, and can improve the design flexibility by selecting different combinations of dense VCSELs (e.g., VCSEL100 and VCSEL 300). As shown in fig. 10, a plurality of adjacent VCSELs may be made to share, in whole or in part, one or more oxidation trenches, P-type metal layers, isolation layers, or via openings by some embodiments. It should be noted that the shape of the shared oxidation trench is irregular, and the shape of the shared oxidation trench may also vary according to the center-to-center spacing of adjacent VCSELs.

In the example of fig. 1-10, a dense design of VCSEL and array according to the present invention is implemented by splitting and recombining the metal layer, the passivation layer via opening and the oxidation trench to form a dense VCSEL array. While the central region of each VCSEL (e.g., oxide aperture, etc.) is not affected, so that the performance of such densely packed VCSELs and arrays can be matched to the performance of typical VCSELs and arrays. Since the dense design fully utilizes the gap between adjacent VCSELs, the density of VCSEL arrays can be greatly increased, and therefore, the size of VCSEL chips can be greatly reduced under the same specification requirement, thereby reducing the cost of chip production and manufacturing.

It should be noted that the described embodiments of the present invention are only examples and do not include all possible embodiments based on the present invention. Modifications of the embodiments of the invention based on the description herein by a person skilled in the art are all within the scope of the invention. No essential or critical elements of the invention should be construed as the essential or essential elements of the invention unless explicitly described as such. Furthermore, the use of "a" and "an" in this disclosure is intended to mean one or more items, and may be used interchangeably with "one or more". The terms "having," "containing," and the like, as used herein, are open-ended terms only, unless expressly stated otherwise. The phrase "based on" in the present invention is intended to mean "based, at least in part, on" unless explicitly stated otherwise.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.