阅读说明：本技术 固体摄像装置、摄像系统及摄像方法 (Solid-state imaging device, imaging system, and imaging method ) 是由 渡边恭志 于 2020-02-05 设计创作，主要内容包括：提供一种能够实现像素阵列部的多个像素的信号的相加读出模式及单独信号从各像素循环读出的循环读出模式这两者的固体摄像装置。像素阵列部具有被定义为以包含像素的多边形的顶角相接的交点为中心而将多边形的顶角分别切掉的区域的多个交点共用区域(41)。在光电二极管部(PD(i,j)、PD(i+1,j)、PD(i,j+1)及PD(i+1,j+1))和交点共用区域41各自的边界部,相同序数的电荷检测部作为低电阻率区域(FD-(11)、FD-(12)、FD-(13)、FD-(14))被配置有4个。在电荷检测部的各自中,具备依次连接着第1主电极端子的4个切换元件(T-(11)、T-(12)、T-(13)、T-(14))和将输入端子连接在切换元件各自的第2主电极端子上的共通的信号读出电路(A1)。(Provided is a solid-state imaging device capable of realizing both an addition read mode for signals of a plurality of pixels in a pixel array unit and a cyclic read mode for cyclically reading individual signals from each pixel. The pixel array section has a plurality of intersection-shared regions (41) defined as regions in which corners of polygons including pixels are cut out with intersections at which the corners meet each other as centers. At the boundary between the photodiode section (PD (i, j), PD (i +1, j), PD (i, j +1), and PD (i +1, j +1)) and the intersection common region 41, the charge detection section of the same number is a low resistivity region (FD) 11 、FD 12 、FD 13 、FD 14 ) Is configured with 4. Each of the charge detection units includes 4 switching elements (T) connected in sequence to the 1 st main electrode terminal 11 、T 12 、T 13 、T 14 ) And a common signal readout circuit (A1) having an input terminal connected to the 2 nd main electrode terminal of each switching element.)

1. A solid-state imaging device is provided,

a plurality of polygons each having a transfer path control type pixel, which is provided with a photoelectric conversion region and a plurality of charge detection portions each storing signal charges transferred from the photoelectric conversion region, are defined as virtual pixel divisions, and the virtual pixel division tiles are filled in a pixel array portion,

the topology of the tile is subdivided into:

a plurality of intersection-shared regions defined as regions in which the corners of a mesh formed by the outer shape defined by the virtual pixels such that the corners of the polygon in which the charge detection units having the same ordinal number are located are connected, are cut out with the intersections as the center, the intersection-shared regions being periodically arranged; and

a plurality of photodiode sections which are remaining regions within the virtual pixel division and each include the photoelectric conversion region,

the solid-state imaging device is characterized in that,

assuming that N is a positive integer of 3 or more, the charge detection units of N identical numbers are arranged at the boundary between the photodiode unit and the intersection common region, and the intersection common region includes:

n switching elements, a1 st main electrode terminal being connected to each of the charge detection sections in sequence; and

and a common signal readout circuit having an input terminal connected to the 2 nd main electrode terminal of each of the switching elements.

2. The solid-state imaging device according to claim 1,

a planar pattern of a two-dimensional region arranged to include a plurality of regions shared by the intersections sequentially defined by different ordinal numbers is used as unit cells, and the unit cells are arranged in the pixel array section so as to be periodically spread.

3. The solid-state imaging device according to claim 2,

the unit cells are arranged repeatedly so as to be shifted from each other in the column direction by a length corresponding to a virtual pixel division between adjacent columns.

4. The solid-state imaging device according to claim 2,

the unit cell includes 2 × 2 groups of the intersection common region,

the intersection-shared region included in the unit cell is arranged in a parallelogram in which the virtual pixel divisions adjacent to each other on the left and right are shifted by 1/2 in the vertical direction.

5. The solid-state imaging device according to claim 1,

the pixel has a low resistivity region constituting a discharge portion for discharging charges other than the signal charges in addition to the low resistivity region constituting the charge detection portion,

a plurality of low resistivity regions are separated from each other by adding an increasing ordinal number corresponding to the number of the discharge portions in addition to the ordinal number for separating the charge detection portions,

the low resistivity region having the same increased ordinal number is disposed at the boundary between the photodiode section and the intersection common region so as to surround the periphery of the intersection common region,

the switching elements are connected to the low resistivity regions in numbers corresponding to the increasing ordinal numbers.

6. The solid-state imaging device according to claim 5,

in the two-dimensional region, the intersection-point-sharing regions sequentially defined by different increasing ordinal numbers are arranged so as to be close to each other by a number corresponding to the increasing ordinal number.

7. The solid-state imaging device according to any one of claims 1 to 4,

the pixel array unit further includes, in a periphery thereof:

a horizontal scanning circuit for driving the plurality of switching elements and the common signal reading circuit, respectively; and

and a control circuit for driving the horizontal scanning circuit by switching between a mode for sequentially and individually reading signals from the plurality of charge detection units arranged in the common region for the respective intersections and a mode for simultaneously reading signals from the plurality of charge detection units.

8. A camera system, characterized in that,

comprising:

a light source that projects irradiation light onto an object; and

a solid-state imaging device in which a plurality of polygons each having a transfer path control type pixel are defined as a virtual pixel division, the virtual pixel division tile is filled in a pixel array unit, reflected light of the irradiation light reflected by the object enters the transfer path control type pixel, and the transfer path control type pixel is provided with a photoelectric conversion region and a plurality of charge detection units each storing signal charge transferred from the photoelectric conversion region so as to sequentially give an ordinal number,

in the solid-state imaging device, the topology of the tile is subdivided into:

a plurality of intersection-shared regions defined as regions in which the corners of a mesh formed by the outer shape defined by the virtual pixels such that the corners of the polygon in which the charge detection units having the same ordinal number are located are connected, are cut out with the intersections as the center, the intersection-shared regions being periodically arranged; and

a plurality of photodiode sections which are remaining regions within the virtual pixel division and each include the photoelectric conversion region,

assuming that N is a positive integer of 3 or more, the charge detection units of N identical numbers are arranged at the boundary between the photodiode unit and the intersection common region, and the intersection common region includes:

n switching elements, a1 st main electrode terminal being connected to each of the charge detection sections in sequence; and

and a common signal readout circuit having an input terminal connected to the 2 nd main electrode terminal of each of the switching elements.

9. An imaging method using a solid-state imaging device in which a polygon having transfer path control type pixels is defined as a virtual pixel division and is further divided into a plurality of intersection point common regions defined by cutting off vertex angles of a plurality of polygons respectively with an intersection point at which the vertex angles are connected as a center, and a plurality of photodiode sections which are remaining regions cut off by the intersection point common regions, wherein the transfer path control type pixels are arranged with a plurality of charge detection sections sequentially ordinally assigned thereto,

the above-mentioned image pickup method is characterized in that,

n is a positive integer of 3 or more, and N charge detection units of the same number are arranged at the boundary between the photodiode unit and the intersection-sharing region,

in each intersection common region, the following modes are switched and operated:

a mode for sequentially reading out N individual signals from the charge detector;

and a mode in which all of the N signals are simultaneously read out from the charge detection unit.

10. The image pickup method according to claim 9,

before the mode of sequentially reading the individual signals, the following is performed:

projecting irradiation light from a light source to an object; and

and storing signal charges generated by the photodiode section by reflected light, which is obtained by reflecting the irradiation light on the object, into the charge detection section at different timings, using mutually independent transfer control means.

Technical Field

The present invention relates to a solid-state imaging device used for distance imaging, an imaging system using the solid-state imaging device, and an imaging method.

Background

As a method of obtaining depth information of an object, a time of flight (TOF) method is known in which distance measurement is performed using a time of flight of light reciprocating to a measurement target object. That is, the method is a method in which the irradiation light is reflected on the object and the distance to the object is determined from the delay of the reflected light with respect to the irradiation light.

In this case, a direct type for directly measuring the delay time of the reflected light and an indirect type for measuring the phase delay of the reflected light are known. The indirect type is also a Pulse Modulation (PM) type in which the distance to the object is determined from the phase delay of the irradiation light of the pulse light emission and a continuous wave modulation (CW) type in which the distance to the object is determined from the phase delay of the irradiation light of the sine wave light emission. The following description will be made by using the PM method, but the present invention is also applicable to the PM method and the CW method. In addition, a CMOS image sensor in which TOF type pixels can be formed by a CMOS process is advantageous for low power consumption and system integration, and TOF realized by a CMOS structure will be discussed below.

A method of configuring a pixel for detecting a phase delay of reflected light has also been proposed, and in general, a method of reading out a pixel with a phase shifted from a common light detection unit to a plurality of reading units has been proposed. In this specification, a reading unit that reads out a signal from the light detection unit is hereinafter referred to as a "tap (tap)". The number of taps may be 2 at minimum, but as shown in patent document 1, 3 or more taps capable of providing "discharge units" to remove background light are preferable, and if 4 taps are provided, a three-tap and one-discharge type is possible as shown in non-patent document 1, or a four-tap operation is possible as shown in non-patent document 2.

In a distance imaging system that performs distance measurement imaging by arranging a plurality of CMOS TOF pixels, when the resolution is increased by increasing the number of pixels, the pixel size needs to be reduced, and a decrease in distance accuracy due to a decrease in sensitivity and the number of saturated electrons cannot be avoided. As one of the countermeasures, a method of adding between adjacent pixels is known. In this specification, such a method of adding between adjacent pixels is hereinafter referred to as "binning". However, combining the four taps makes the structure very complicated, and thus the implementation is not easy.

Documents of the prior art

Patent document

Patent document 1: japanese patent No. 4235729

Non-patent document

Non-patent document 1: 5 Anfuji et al, "high-resolution optical time-of-flight image sensor with a 3tap temporal field modulator with three-tap transverse electric field charge modulator", 2017 International society for image sensor research (IISW), R24, p 254-257, Hiroshima, 2017, 5.31.D.)

Non-patent document 2: lee and other 4 people, "Back-Illuminated Time-of-Flight light Image Sensor with SOI-Based full populated Detector technology for LiDAR Application," academic digital publishing Association (MDPI) Proceedings (Proceedings), 2018, Vol 2, No. 13, item No. 798

Disclosure of Invention

Problems to be solved by the invention

In view of the above-described problems, it is an object of the present invention to provide a solid-state imaging device capable of realizing two modes, i.e., an addition readout mode of signals of a plurality of pixels arranged in a pixel array unit and a cyclic readout mode of individual signals from each pixel, and an imaging system and an imaging method using the solid-state imaging device.

Means for solving the problems

The invention according to claim 1 relates to a solid-state imaging device in which a plurality of polygons having the same shape are defined as virtual pixel divisions, and the pixel array unit is filled with the virtual pixel division tiles. The virtual pixel division of the solid-state imaging device according to claim 1 includes transfer path control type pixels each including a photoelectric conversion region and a plurality of charge detection units each storing signal charges transferred from the photoelectric conversion region arranged in the periphery of the photoelectric conversion region. In each of the transfer path control type pixels, ordinal numbers are assigned to the plurality of charge detection units so as to be distinguished from each other. The pixel array section of the solid-state imaging device according to claim 1 has a tile topology that is further divided into: (a) a plurality of intersection-shared regions defined as regions in which corners are cut out with an intersection of meshes formed by the outer shapes divided by the virtual pixels as a center, the plurality of intersection-shared regions being periodically arranged so that corners of polygons in which the charge detection sections having the same ordinal number are located are in contact with each other; and (b) a plurality of photodiode sections which are the remaining regions within the virtual pixel division cut out by the intersection common region and each of which includes a photoelectric conversion region. In the solid-state imaging device according to claim 1, N is a positive integer of 3 or more, and N charge detection units of the same number are arranged at each boundary between the photodiode unit and the intersection-sharing region. The intersection-shared region includes: n switching elements connected in sequence to the 1 st main electrode terminal in each of the charge detection sections; and a common signal readout circuit having input terminals connected to the 2 nd main electrode terminals of the switching elements, respectively.

The invention according to claim 2 is based on an imaging system including: (a) a light source that projects irradiation light onto an object; and (b) a solid-state imaging device in which a plurality of polygons each having a transfer path control type pixel, each polygon having the same shape, are defined as virtual pixel divisions, and the virtual pixel division tiles are filled in a pixel array unit, the transfer path control type pixel being configured with a photoelectric conversion region and a plurality of charge detection sections that are arranged in the periphery of the photoelectric conversion region and that respectively store signal charges transferred from the photoelectric conversion region, ordinal numbers that are different from each other are given to the plurality of charge detection sections, and reflected light of irradiation light reflected by an object enters the transfer path control type pixel, the solid-state imaging device subdividing the topology of the tiles into a plurality of intersection common regions defined as regions in which apex angles are cut out with the intersection of meshes constituted by the outer shape of the virtual pixel division as the center, and a plurality of photodiode sections, the plurality of photodiode sections are arranged periodically so that the corners of polygons in which the charge detection sections having the same ordinal number are located are in contact with each other, and the remaining regions in the virtual pixel division cut out by the intersection common region include photoelectric conversion regions. In the imaging system according to claim 2, N is a positive integer of 3 or more, and N charge detection units of the same number of orders are arranged at the boundary between the photodiode unit and the intersection common region. The intersection-shared region includes: n switching elements connected in sequence to the 1 st main electrode terminal in each of the charge detection sections; and a common signal readout circuit having input terminals connected to the 2 nd main electrode terminals of the switching elements, respectively.

The invention according to claim 3 relates to an imaging method using a solid-state imaging device in which a polygon having transfer path control type pixels in which a plurality of charge detection units are arranged and classified by ordinal numbers is defined as a virtual pixel division, and the polygon is further divided into a plurality of intersection point common regions defined as regions in which apex angles of the polygons are cut out respectively with an intersection point at the center where the apex angles are connected, and a plurality of photodiode units defined as remaining regions obtained by cutting out the intersection point common regions. In the imaging method according to claim 3, N is a positive integer of 3 or more, N charge detection units of the same number are arranged at the boundary between the photodiode unit and the intersection common region, and the following mode is switched and operated for each of the intersection common regions: a mode in which N individual signals are sequentially read from the charge detection section; a mode in which all of the N signals are simultaneously read out from the charge detection unit.

Effects of the invention

According to the present invention, it is possible to provide a solid-state imaging device capable of realizing both an addition read mode of signals of a plurality of pixels in a pixel array unit and a cyclic read mode in which individual signals are cyclically read from each pixel, and an imaging system and an imaging method using the solid-state imaging device.

Drawings

Fig. 1 is a block diagram showing a part of an example of an imaging system according to embodiment 1 of the present invention.

Fig. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to embodiment 1.

Fig. 3 is a circuit diagram showing an example of an equivalent circuit of a pixel including a signal reading circuit in the solid-state imaging device according to embodiment 1.

Fig. 4 is a schematic diagram illustrating a relationship between the arrangement of the photodiode section and the transfer control mechanism section of the solid-state imaging device according to embodiment 1 and the region shared by the intersections.

Fig. 5 is a schematic diagram showing a configuration of a1 st intersection common region of the solid-state imaging device according to embodiment 1.

Fig. 6 is a circuit diagram showing a circuit configuration of the solid-state imaging device according to embodiment 1, which is enlarged to the other intersection common region with the 4 th intersection common region as the center.

Fig. 7 is a timing chart for explaining a method of driving and reading out the solid-state imaging device according to embodiment 1.

Fig. 8 is a schematic diagram showing an example of arrangement of signal lines in the solid-state imaging device according to embodiment 1.

Fig. 9 is a timing chart illustrating a cyclic readout mode in which signals are cyclically read out from individual pixels in the solid-state imaging device according to embodiment 1.

Fig. 10 is a timing chart showing an addition read mode in which signals are addition read from pixels in the solid-state imaging device according to embodiment 1.

Fig. 11 is a circuit diagram showing an example of a pixel of the solid-state imaging device according to embodiment 2.

Fig. 12 is a schematic diagram showing the arrangement of the photodiode section and the transfer control mechanism section of the solid-state imaging device according to embodiment 2.

Fig. 13 is a schematic diagram showing a configuration of a common region at an intersection of the solid-state imaging device according to embodiment 2.

Fig. 14 is a timing chart for explaining a method of driving and reading out the solid-state imaging device according to embodiment 2.

Fig. 15 is a timing chart illustrating a cyclic readout mode in which signals are cyclically read out from individual pixels in the solid-state imaging device according to embodiment 2.

Fig. 16 is a timing chart for explaining an addition read mode in which signals are addition read from pixels in the solid-state imaging device according to embodiment 2.

Fig. 17 is a schematic diagram showing the arrangement of the photodiode section and the transfer control mechanism section of the solid-state imaging device according to embodiment 3.

Fig. 18 is a schematic diagram showing an example of arrangement of signal lines in the solid-state imaging device according to embodiment 3.

Fig. 19 is a timing chart for explaining a cycle read mode in which signals are cyclically read from individual pixels in the solid-state imaging device according to embodiment 3.

Fig. 20 is a timing chart for explaining an addition read mode in which signals are addition read from pixels in the solid-state imaging device according to embodiment 3.

Fig. 21 is a schematic diagram showing the arrangement of the photodiode section and the transfer control mechanism section of the solid-state imaging device according to embodiment 4.

Fig. 22 (a) is a diagram illustrating the technical idea of regarding the pixel division of the pixel array section constituting the solid-state imaging device according to embodiment 1 as a 1-piece square brick (tile) and tiling the brick so as not to generate a gap, and fig. 22 (b) is a diagram illustrating the technical idea of tiling the pixel array section of the solid-state imaging device according to embodiment 1 with two kinds of bricks, namely, an octagonal 1 st brick corresponding to the pattern of the photodiode section and a quadrangular 2 nd brick corresponding to the pattern of the intersection common region.

Fig. 23 is a schematic diagram illustrating a detailed planar structure of a photodiode section represented as an octagonal brick shown in fig. 22 (b).

Fig. 24 is a schematic diagram illustrating a cross section corresponding to a part of the pixel array section of the solid-state imaging device according to embodiment 1, as viewed in the directions XXIV to XXIV in fig. 23.

FIG. 25 is a diagram illustrating another topology of the two tiles shown in FIG. 22 (b).

Fig. 26 is a schematic plan view of a structure of an intersection-shared region, which is an example of a solid-state imaging device according to another embodiment, and which is described with a focus on one of intersection-shared regions constituting a pixel array unit formed of eight-tap pixels.

Fig. 27 is a schematic plan view illustrating a part of a pixel array section in a topology in which a triangular virtual pixel is divided into tiles, as another example of a solid-state imaging device according to another embodiment.

Fig. 28 is a schematic plan view illustrating a part of a pixel array section in a topology in which hexagonal dummy pixel division tiles are used as another example of a solid-state imaging device according to another embodiment, and shows a periodic arrangement of unit cells.

Fig. 29 is a schematic plan view showing a part of fig. 28 in an enlarged manner.

Fig. 30 is a schematic plan view illustrating a part of a pixel array section in a topology in which pentagonal virtual pixels are divided into tiles, as still another example of a solid-state imaging device according to another embodiment.

Fig. 31 is a schematic plan view showing a part of fig. 30 in an enlarged manner.

Detailed Description

Next, embodiments 1 to 4 of the present invention will be described with reference to the drawings. In the description of the drawings of the solid-state imaging device according to embodiments 1 to 4, the same or similar reference numerals are given to the same or similar parts. However, the drawings are schematic, and it should be noted that the relationship between the thickness and the plane size, the ratio of the thicknesses of the respective members, and the like are different from the actual ones. Therefore, specific thickness and size should be determined with reference to the following description. It is to be understood that the drawings also include portions having different dimensional relationships and ratios.

The solid-state imaging devices according to embodiments 1 to 4 are solid-state imaging devices illustrating devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is not limited to the following configurations and arrangements of circuit elements and circuit blocks, or layouts on semiconductor chips, and the like. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

In the following description of embodiments 1 to 4, the 1 st conductivity type is p-type and the 2 nd conductivity type is n-type, but it can be easily understood that if the 1 st conductivity type is n-type and the 2 nd conductivity type is p-type, the same effect can be obtained by reversing the electrical polarities. In this case, the high level and the low level of the pulse waveform are also the case where appropriate inversion is required according to the technical common knowledge of those skilled in the art.

For example, in the following fig. 2 and 4, for convenience of explanation, a topology in which a plurality of pixel divisions are arranged in a two-dimensional matrix in a pixel array unit is shown, but this is merely an example. The layout of the line sensor may be such that pixels are divided and arranged one-dimensionally in the pixel array section.

(embodiment 1)

Fig. 1 shows a part of a TOF type distance imaging-enabled configuration of an imaging system 11 according to embodiment 1 of the present invention. Here, a part of the imaging system 11 shown in fig. 1 is configured by a light source 12 that projects irradiation light 17 onto an object 16, an imaging optical system 13 that reflects the irradiation light 17 off the object 16 and makes reflected light 18 incident thereon, a TOF type solid-state imaging device 14, and an image processing circuit 15.

Fig. 2 shows a part of the structure of the solid-state imaging device 14 shown in fig. 1. As shown in fig. 2, the solid-state imaging device 14 according to embodiment 1 divides virtual pixels each including a plurality of transfer path control type pixels into X_ij(i＝1～m₁，j＝1～n₁：m₁、n₁Each is a positive integer of 2 or more. ) The pixel array unit 1 is arranged in a mesh shape, and plane filling (tiling) is performed, thereby enabling four-tap distance imaging. The "transfer path control type pixel" refers to a pixel in which transfer paths and transfer directions of signal charges can be independently distributed as is conventionally known as a TOF type.

As evidenced by bidaggeras, a regular polygon shape in which a plane can be fully laid without a gap only by parallel translation and inversion can be used, and there are only three types of regular triangles, squares, and hexagons. However, if the conditions of regular polygon are removed and rotation is allowed, the tile tiles may be tiled without any gap in any triangle or quadrangle, including non-convex patterns. The solid-state imaging device 14 according to embodiment 1 shown in fig. 2 is configured to divide a square virtual pixel into X_ijThe pixel array section 1 is arranged in a mesh shape and is tiled and filled so as not to generate a gap.

Further, in the solid-state imaging device according to embodiment 1, a vertical scanning circuit 22 and a horizontal scanning circuit 23 for driving each pixel, a signal processing circuit 24 for processing signals from the pixels, and a control circuit 25 for controlling the whole of them are arranged around the pixel array section 1.

Fig. 3 shows a circuit configuration for performing TOF distance imaging using the solid-state imaging device according to embodiment 1 of the present invention. Virtual pixel division X formed as a kind of "planar filling shape" in geometry, i.e., a quadrangle_ijThe transfer path control type pixel includes one photodiode section PD constituting a part of a transfer path control type pixel and four transfer control means connected to the photodiode section PD.

The "planar filling shape" used in the present specification refers to a shape in which a plane can be completely filled in one pattern only by parallel movement and inversion so that a gap such as a small triangle does not occur. The three regular polygons of bidagoras' regular triangle, square, regular hexagon are called "regular planar fill shapes". Similarly, the term "tile fill" or "flat surface fill" used in the present specification means that a flat surface is completely filled so that a small gap of another shape such as a triangle does not occur, and in this case, as described in "another embodiment" or the like in the latter stage of the present specification, rotation is allowed without being limited to the fill by a regular polygon.

The four transfer control means are respectively assigned the 1 st to 4 th ordinal numbers (ordinal numbers), and are divided into the 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3 and the 4 th transfer control means G4, thereby constituting a four-tap type pixel. The 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the 4 th transfer control means G4 independently control the transfer path and the transfer direction of the signal charge corresponding to the four taps, respectively.

The 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the 4 th transfer control means G4 may be insulated gate type transfer control means similar to MOS transistors as shown in fig. 24, or may be lateral electric field control type transfer control means, respectively. Fig. 24 illustrates an insulated gate type transfer control mechanism for controlling the surface potential of the semiconductor substrate 31 of the 1 st conductivity type (p-type) by the gate electrodes 36a, 36b, and 36c provided on the gate insulating film 35.

The four transfer control means G1 to G4 are each connected to a1 st charge detector FD1, a 2 nd charge detector FD2, a 3 rd charge detector FD3, and a4 th charge detector FD4, respectively, in order of ordinal number. In fig. 3, the other terminal of the 1 st detector capacitor C1, which has one terminal grounded, is connected to the 1 st charge detector FD1, so that the storage capacitance of the 1 st charge detector FD1 can be increased. Similarly, the other terminal of the 2 nd detector capacitor C2, which is grounded at one terminal, is connected to the 2 nd charge detector FD2, so that the storage capacitance of the 2 nd charge detector FD2 can be increased.

In fig. 24, a virtual pixel division X is exemplarily illustrated_i，(j+1)The photoelectric conversion region of the pixel (2) is composed of a p-type semiconductor substrate 31 and a second conductivity type (2) selectively buried in the upper part of the semiconductor substrate 31n-type) is formed by embedding the p-n junction of the region 32 a. P is arranged on the surface embedded region 32a⁺A pinned layer 33a of type. As shown in fig. 24, regions (n) to which n-type impurities are added at high concentration are separately buried in the upper portion of the semiconductor substrate 31⁺Regions) 34a, 34b, 34 c.

As shown in fig. 24, a gate insulating film 35 is provided on the upper surface of the semiconductor substrate 31. The 1 st transfer control means G1 of the insulated gate type is constituted by the gate electrode 36b provided on the gate insulating film 35, and the signal charge of the photodiode section PD (i, j +1) is transferred to the n⁺The 1 st charge detection portion FD1 formed by the region 34 b. The 4 th transfer control means G4 of the insulated gate type is constituted by the gate electrode 36a provided on the gate insulating film 35, and the signal charge of the photodiode section PD (i, j +1) is transferred to the n⁺The 4 th charge detection part FD4 formed by the region 34 a. Further, the 1 st transfer control means G1 of the insulated gate type is constituted by the gate electrode 36c provided on the gate insulating film 35 of fig. 24, and the signal charge of the photodiode section PD (i +1, j) is transferred to n⁺The 1 st charge detection section FD1 of the photodiode section PD (i +1, j) configured by the region 34 c.

Further, as shown in fig. 3, the other terminal of the 3 rd sensing part capacitor C3 having one terminal grounded is connected to the 3 rd charge sensing part FD3, and the other terminal of the 4 th sensing part capacitor C4 having one terminal grounded is connected to the 4 th charge sensing part FD4, so that the storage capacitances of the 3 rd sensing part capacitor C3 and the 4 th sensing part capacitor C4 can be increased, respectively. However, in fig. 3, the 1 st detector capacitor C1, the 2 nd detector capacitor C2, the 3 rd detector capacitor C3, and the 4 th detector capacitor C4 added to the charge detectors FD1 to FD4 may be individual capacitance elements designed intentionally or may be parasitic floating capacitors. For example, the four detector capacitances C1 to C4 may be junction capacitances of the charge detectors FD1 to FD4, respectively.

The 1 st charge detector FD1 in fig. 3 has a drain terminal connected to the source terminal of the 1 st reset transistor RT1 on the power supply line VRD. Similarly, the 2 nd charge detector FD2 has a drain terminal connected to the source terminal of the 2 nd reset transistor RT2 on the power supply line VRD. Further, the 3 rd charge detector FD3 is connected to the source terminal of the 3 rd reset transistor RT3 having its drain terminal connected to the power supply line VRD, and the 4 th charge detector FD4 is connected to the source terminal of the 4 th reset transistor RT4 having its drain terminal connected to the power supply line VRD. The potentials of the charge detectors FD1 to FD4, which are caused by the signal charges accumulated in the charge detectors FD1 to FD4, are reset (initialized) by the 1 st reset transistor RT1, the 2 nd reset transistor RT2, the 3 rd reset transistor RT3, and the 4 th reset transistor RT4, respectively.

The 1 st charge detector FD1 in fig. 3 is connected to the gate terminal of the 1 st source follower transistor SF 1. Similarly, the 2 nd charge detector FD2 is connected to the gate terminal of the 2 nd source follower transistor SF 2. Further, the 3 rd charge detector FD3 is connected to the gate terminal of the 3 rd source follower transistor SF3, and the 4 th charge detector FD4 is connected to the gate terminal of the 4 th source follower transistor SF 4. The 1 st source follower transistor SF1 has a drain terminal connected to the power supply line VDD and a source terminal connected to the source terminal of the 1 st select transistor SL 1. Similarly, the 2 nd source follower transistor SF2 has a drain terminal connected to the power supply line VDD and a source terminal connected to the source terminal of the 2 nd select transistor SL 2.

Further, the 3 rd source follower transistor SF3 has a drain terminal connected to the power supply line VDD, a source terminal connected to the source terminal of the 3 rd select transistor SL3, a4 th source follower transistor SF4 has a drain terminal connected to the power supply line VDD, and a source terminal connected to the source terminal of the 4 th select transistor SL 4.

The reset potential and the signal potential after signal transfer of the charge detectors FD1 to FD4 are amplified by the 1 st source follower transistor SF1, the 2 nd source follower transistor SF2, the 3 rd source follower transistor SF3, and the 4 th source follower transistor SF4, respectively, and then output from the drain terminals of the 1 st selection transistor SL1, the 2 nd selection transistor SL2, the 3 rd selection transistor SL3, and the 4 th selection transistor SL4 as the 1 st output signal O1, the 2 nd output signal O2, the 3 rd output signal O3, and the 4 th output signal O4, respectively. The reset potential and the signal potential read out as the output signals O1 to O4 are subjected to Correlated Double Sampling (CDS) processing for obtaining a difference between the reset potential and the signal potential by the signal processing circuit 24 shown in fig. 2, and a clean signal is obtained.

By dividing the virtual pixels shown in FIG. 3 into X_ijAs shown in fig. 2, the four-tap solid-state imaging device 14 according to embodiment 1 is configured by arranging the pixel array section 1 in a two-dimensional matrix (mesh) shape. A method of realizing a mode in which signals are cyclically read from individual pixels and a mode in which signals are additively read from pixels in a 2 × 2 intersection common region in the solid-state imaging device according to embodiment 1 will be described with reference to fig. 4. In fig. 4, a virtual pixel included in a part of the pixel array section 1 of the solid-state imaging device 14 that performs the four-tap TOF operation is divided into X_ij、X_i，(j+1)、X_(i+1)，j、X_(i+1)，_(j+1)The photodiode section PD, the 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the 4 th transfer control means G4 are shown. In the central part of fig. 4, a virtual pixel division X is shown_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}The respective photodiode sections PD (i, j), PD (i +1, j), PD (i, j +1), and PD (i +1, j + 1).

Virtual pixel division X_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}The tiles are arranged in a two-dimensional matrix (mesh) and are tiled so as not to generate gaps. Dividing X at four adjacent virtual pixels_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}Among the four transfer control means, the same type of transfer control means classified and classified by the same ordinal number is set as a virtual pixel division X so that they are close to each other_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}The respective position. By this arrangement setting, the same kind of transfer control means having the same ordinal number is formed to divide the virtual pixel into X_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}The same ordinal number surrounding region surrounded by the mode switching circuit。

The same ordinal number surrounding area of the quadrangle surrounded by the four adjacent 1 st transfer control means G1 is defined as the "1 st intersection common area 41". The 1 st intersection common region 41 is divided into four virtual pixels X shown in fig. 22 (a)_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}Cross point P of the mesh defined by the outer periphery of (2)₁As a central, common intersection point P₁Where (a) is located. The 1 st intersection common region 41 is, as shown in fig. 22 (b), a region obtained by dividing four virtual pixels into X_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}The respective 1 st transfer control mechanisms G1 are located in a quadrangular region formed by chamfering the corners thereof.

Similarly, a region enclosed by the same ordinal number of the quadrangle enclosed by the four adjacent 2 nd transfer control means G2 is defined as the "2 nd intersection common region 42". The 2 nd intersection common region 42 is divided into X by four virtual pixels shown in fig. 22 (a)_(i－1)，j、X_{(i－1)，(j+1)}、X_i，j、X_i，(j+1)Cross point P of the mesh defined by the outer periphery of (2)₂As a central, common intersection point P₂Where (a) is located. The 2 nd intersection common region 42 is at the intersection P as shown in fig. 22 (b)₂Dividing four virtual pixels into X_(i－1)，j、X_(i－1)，_(j+1)、X_i，j、X_i，(j+1)The 2 nd transfer control means G2 are located in a quadrangular region formed by chamfering the corners thereof.

Further, the same ordinal number surrounding regions of the quadrangle surrounded by the four adjacent 3 rd transfer control means G3 and the four adjacent 4 th transfer control means G4 are referred to as a "3 rd intersection common region 43" and a "4 th intersection common region 44", respectively. The 3 rd intersection common region 43 is divided into X by four virtual pixels shown in fig. 22 (a)_i，(j+1)、X_i，(j+2)、X_{(i+1)，(j+1)}、X_{(i+1)，(j+2)}Cross point P of the mesh defined by the outer periphery of (2)₃As a central, common intersection point P₃Where (a) is located. The 3 rd intersection common region 43 is at the intersection P as shown in fig. 22 (b)₃Dividing four virtual pixels into X_i，(j+1)、X_i，(j+2)、X_{(i+1)，(j+1)}、X_{(i+1)，(j+2)}The 3 rd transfer control means G3 are located in a quadrangular region formed by chamfering the corners thereof.

The 4 th intersection common region 44 is divided into four virtual pixels X shown in fig. 22 (a)_{(i－1)，(j+1)}、X_{(i－1)，(j+2)}、X_i，(j+1)、X_i，(j+2)Cross point P of the mesh defined by the outer periphery of (2)₄As a central, common intersection point P₄Where (a) is located. The 4 th intersection common region 43 is at the intersection P as shown in fig. 22 (b)₄Dividing four virtual pixels into X_{(i－1)，(j+1)}、X_{(i－1)，(j+2)}、X_i，(j+1)、X_i，(j+2)The 4 th transfer control mechanism G4 is located in a quadrangular region formed by chamfering the corners thereof. For example, if one looks at the virtual pixel division X_i，(j+1)Since the four corners at which the 1 st transfer controller G1, the 2 nd transfer controller G2, the 3 rd transfer controller G3, and the 4 th transfer controller G4 are located are chamfered and cut out, the virtual pixel division X of the quadrangle is divided into four corners_i，(j+1)The outer shape of the inequilateral octagonal photodiode section PD (i, j +1) is defined as shown in fig. 22 (b).

Other virtual pixel divisions X_ij、X_(i+1)，j、X_{(i+1)，(j+1)}Similarly, the four corners at which the 1 st transfer controller G1, the 2 nd transfer controller G2, the 3 rd transfer controller G3, and the 4 th transfer controller G4 are located are chamfered and cut off, respectively, so that the outer shapes of the photodiode section PD (i, j), PD (i +1, j +1), and the like having a scalene octagon are defined. Thus, in FIG. 2, the division of a quadrilateral virtual pixel into X is illustrated_ijThe pixel array section 1 is filled with tiles so as not to generate gaps, but as can be seen from fig. 22, actually: the tile filling of the 1 st tile in the inequilateral octagon occupied by the photodiode section PD (i, j) and the 2 nd tile in the quadrangle occupied by the 1 st intersection common region 41, the 2 nd intersection common region 42, the 3 rd intersection common region 43, and the 4 th intersection common region 44.

As shown in fig. 23 and 24, the internal structure of the photodiode section PD (i, j +1) in fig. 22 (b) is represented by a planar pattern including a non-equilateral octagonal photoelectric conversion region defined by the surface embedded region 32a occupying the inside of the photodiode section PD (i, j +1) and an element isolation region surrounding the photoelectric conversion region. I.e. virtual pixel division X_i，(j+1)The photoelectric conversion region of the pixel (b) functioning as an effective photodiode is a region of a scalene octagon having a smaller area than the 1 st tile of the scalene octagon shown in fig. 22 (b). Thus, the area relationship among the pixels is as follows:

(virtual pixel division) > (photodiode section) > (photoelectric conversion region).

As shown in fig. 24, the virtual pixel division X_i，(j+1)The photoelectric conversion region of the pixel (2) is composed of a p-type semiconductor substrate 31 and a p-n junction selectively buried in a surface buried region 32a on the semiconductor substrate 31. P is arranged on the surface embedded region 32a⁺A pinned layer 33a of type. As shown in fig. 23, four n pieces are provided around the photodiode section PD (i, j +1) corresponding to the photodiode section PD (i, j +1)⁺And a region serving as a charge detection section.

As shown in fig. 4, when a unit pattern region (place) including intersection common regions of mutually different ordinal numbers of a 2 × 2 group including a1 st intersection common region 41, a 2 nd intersection common region 42, a 3 rd intersection common region 43, and a4 th intersection common region 44 defined by the same ordinal number is set as a four-tap type "unit cell 49", the unit cell 49 is set as a unit of a periodic pattern, and each virtual pixel is divided into X groups_ijThe pixel array section 1 shown in fig. 2 is repeatedly arranged.

Division X at each virtual pixel of fig. 4_ij1 st charge transfer direction D internally indicated by the thick dotted arrow₁Respectively represent division of X from each virtual pixel_ijThe photodiode section PD (i, j) in (1) transfers and distributes the signal charges in a direction toward the first transfer control means. Similarly, the 2 nd charge transfer direction D indicated by the solid arrow₂Respectively representing division of X from each virtual pixel_ijThe photodiode section PD (i, j) in (2) is directed to transfer and distribute the signal charges to the transfer control means. In addition, each virtual pixel in fig. 4 is divided into X_ijThe 3 rd charge transfer direction D is indicated by an arrow of a one-dot chain line₃Respectively representing division of X from each virtual pixel_ijThe photodiode section PD (i, j) in (3) is directed to transfer and distribute the signal charges to the transfer control means. Further, the charge transfer direction D is larger than that of the 1 st charge transfer direction₁4 th charge transfer direction D indicated by a thin dotted arrow₄Respectively representing division of X from each virtual pixel_ijThe photodiode section PD (i, j) in (b) is directed to the 4 th transfer control means to transfer and distribute the signal charges.

Dividing X at each virtual pixel_ijIn this embodiment, four transfer control means G1 to G4 are arranged at four vertices around the photodiode section PD (i, j), but the arrangement positions in these pixels have a periodic pattern cyclically different from the coordinate positions inside the unit cell 49. The charge transfer direction D in the photodiode section PD following the cyclic position in the periodic pattern₁～D₄Also as indicated by the arrows in the figure, there is a division X with the virtual pixel in the unit cell 49_ijCompared to cyclically different orientations. However, the virtual pixel division X shown in FIG. 4_ijA charge transfer direction D symmetrical with respect to the photodiode section PD (i, j) as a center point₁～D₄Which direction becomes equivalent with respect to the charge transfer. Thus, the total virtual pixel division X shown in FIG. 4_ijMay be considered equivalent.

In fig. 4, the positions of the 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the 4 th transfer control means G4 can be replaced while maintaining the above-described periodicity. In fig. 4, a cyclic periodic pattern is formed which repeats in units of the unit cells 49 each including the 2 × 2 intersection common region at the arrangement position (ordinal number array) in the pixels of the 4 types of transfer control means G1 to G4, but since the range including the 2 × 2 intersection common region having a rectangular shape is the unit cell 49, the 2 × 2 virtual pixel division is converged to the area of one unit cell 49. In the adjacent unit cell 49 columns, the positions corresponding to the length of the virtual pixel division may be repeatedly arranged while being shifted from each other in the column direction. An example of this case is described with reference to fig. 12 of embodiment 2.

Fig. 5 shows the mode switching circuit arranged in the intersection common region in detail. Here, the photodiode section shown in fig. 4 shows the 1 st intersection common region 41 located at the center of the photodiode sections PD (i, j), PD (i +1, j), PD (i, j +1), and PD (i +1, j + 1). As shown in fig. 22 (a), the corners of four quadrangles are divided into X with virtual pixels_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}Cross point P of meshes formed by the quadrangular outer shape of (2)₁Are connected with each other. The 1 st intersection common region 41 is defined as the intersection P₁A rhombic region having a center formed by cutting out the apex angles of a quadrangle. In fig. 5, four 1 st charge detection units FD1 (see fig. 3) are shown as dots (·) around the 1 st intersection common region 41. In order to distinguish the four 1 st charge detecting units FD1 from each other, the 1 st charge detecting unit FD1 connected to the upper left photodiode unit PD (i, j) of fig. 5 is redefined as a "1 st low resistivity region FD1 by adding a new ordinal number to the 1 st charge detecting unit FD1₁₁". In the upper right of fig. 23, a region (n) obtained by adding an n-type impurity at a high concentration to the upper part of a p-type semiconductor substrate is shown⁺Region) to represent the 1 st low-resistivity region FD of fig. 5₁₁. In the 1 st low resistivity region FD, as in FIG. 3₁₁A1 st extension capacitor C connected to one terminal of the first and second capacitors₁₁To the other terminal.

In fig. 5, four capacitors are arranged around the 1 st intersection common region 41. In order to distinguish the four capacitances from each other, the 1 st detection part capacitance C1 on the upper left photodiode part PD (i, j) side in fig. 5 is newly given a ordinal number and is redefined as the "1 st extension capacitance C₁₁". Namely, the "1 st extension capacitance C" redefined in FIG. 5₁₁"and pictureThe 1 st detection part capacitance C1 shown in fig. 3 corresponds to. Further, in the 1 st low resistivity region FD₁₁To which a1 st switching element T is connected₁₁1 st main electrode terminal, 1 st switching element T₁₁Is connected to the gate terminal of the 1 st source follower transistor SF 1. If the 1 st switching element T₁₁In the case of a MOS transistor such as a MOSFET, the 1 st main electrode terminal corresponds to a source terminal and the 2 nd main electrode terminal corresponds to a drain terminal. The 1 st source follower transistor SF1 constituting the common signal readout circuit a1 shown in fig. 5 corresponds to the 1 st source follower transistor SF1 constituting the signal readout circuit a1 shown in fig. 3. The gate terminal of the 1 st source follower transistor SF1 functions as an input terminal of the signal readout circuit a 1.

Similarly, the 1 st charge detection section FD1 connected to the upper right photodiode section PD (i +1, j) of fig. 5 is defined as "the 2 nd low-resistivity region FD1₁₂". N is selectively buried in the upper part of the p-type semiconductor substrate 31 shown in FIG. 24⁺Region 34c and low-resistivity region 2 FD₁₂And (7) corresponding. In the 2 nd low resistivity region FD₁₂The other terminal of the 2 nd detection part capacitor, which is connected to the ground at one terminal, is connected. "No. 2 extended capacitance C redefined in FIG. 5₁₂"corresponds to the 1 st detection unit capacitance C1 shown in fig. 3. Further, in the 2 nd low resistivity region FD₁₂To which a 2 nd switching element T is connected₁₂1 st main electrode terminal, 2 nd switching element T₁₂The 2 nd main electrode terminal of (a) is connected to the input terminal of the common signal sensing circuit a 1.

In addition, the 1 st charge detection part FD1 connected to the photodiode part PD (i, j +1) at the lower left of fig. 5 is defined as "the 3 rd low-resistivity region FD1₁₃". N in FIG. 24⁺Region 34b is a 3 rd low resistivity region FD₁₃. In the 3 rd low resistivity region FD₁₃The other terminal of the 3 rd detection part capacitor, which connects one terminal to ground, is connected. "extension capacitance No. 3C" redefined in FIG. 5₁₃"corresponds to the 1 st detection unit capacitance C1 shown in fig. 3. Further, in the 3 rd low resistivity region FD₁₃Is connected with a 3 rd switching element T₁₃1 st main electrodeTerminal, No. 3 switching element T₁₃The 2 nd main electrode terminal of (a) is connected to the input terminal of the common signal sensing circuit a 1.

Further, the 1 st charge detection section FD1 connected to the photodiode section PD (i +1, j +1) at the lower right in fig. 5 is defined as a "4 th low-resistivity region FD1₁₄". N selectively provided on a p-type semiconductor substrate as shown in the upper right region of FIG. 23⁺Region and 4 th low resistivity region FD₁₄And (7) corresponding. In the 4 th low-resistivity region FD₁₄The other terminal of the 4 th detection part capacitor, which is grounded at one terminal, is connected thereto. "4 th detection part capacitance C redefined in FIG. 5₁₄"corresponds to the 1 st detection unit capacitance C1 shown in fig. 3. Further, in the 4 th low resistivity region FD₁₄To which a4 th switching element T is connected₁₄1 st main electrode terminal, 4 th switching element T₁₄The 2 nd main electrode terminal of (a) is connected to the input terminal of the common signal sensing circuit a 1.

That is, in fig. 5, the 1 st transfer control means G1, which is the transfer control means classified by the same ordinal number, of each of the four photodiode sections PD (i, j), PD (i +1, j), PD (i, j +1), and PD (i +1, j +1) is connected to the 1 st low-resistivity region FD that is added with the capacitance corresponding to the 1 st detection section capacitance C1 shown in fig. 3₁₁2 nd low resistivity region FD₁₂3 rd low resistivity region FD₁₃And 4 th low resistivity region FD₁₄. From four low-resistivity regions FD₁₁～FD₁₄The output signals of the charge detection parts are respectively transmitted through the 1 st switching element T₁₁2 nd switching element T₁₂3 rd switching element T₁₃And 4 th switching element T₁₄The signals are input to the common signal sensing circuit a 1.

The signal output from the 1 st source follower transistor SF1 is output to the 1 st signal line Sig1 via the 1 st selection transistor SL1 constituting the common signal readout circuit a 1. From four virtual pixel divisions X_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}In a mode in which the signals of the pixels are independently read, the element T is switched₁₁～T₁₄Sequentially turned on and divided into 4 readouts. In the case of a mode in which signals from pixels included in unit cells including a 2 × 2 intersection common region are read out by addition, the switching element T is switched₁₁～T₁₄Simultaneously switched on and read out 1 time.

As shown in FIG. 5, the 1 st cross point common region 41 including the 1 st transfer control means G1 further includes a switching element T₁₁～T₁₄A1 st source follower transistor SF1, a1 st select transistor SL1, and a1 st reset transistor RT 1. Although not shown, the circuit configuration of the intersection common region set for each of the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the 4 th transfer control means G4 is the same as that of the 1 st intersection common region 41 except that the number of ordinal numbers (ordinal numbers) given to the elements such as the transistors is different.

In fig. 5, the driving signal lines of the respective gates are partially illustrated as an example. That is, although the 1 st transfer control mechanism drive line Φ G1, the reset transistor drive line Φ RT, and the selection transistor drive line Φ SL are shown, the 2 nd transfer control mechanism drive line and the switching element T which need to be in the same row are not described₁₁～T₁₄The driving line of (a). Although these drive lines are mainly in the horizontal wiring direction, the transfer control means G1 to G4 that operate globally can also realize the vertical wiring direction. In addition, the vertical wiring requires a power supply line in addition to the 1 st signal line Sig1, but is not described.

Fig. 6 shows a circuit configuration in which the circuit configuration of fig. 5 is enlarged for a unit cell including a 2 × 2 intersection common region corresponding to fig. 3, with attention paid to four photodiode sections PD (p, q), PD (p +1, q), PD (p, q +1), and PD (p +1, q +1) (p is 1 to m)₂，q＝1～n₂：m₂、n₂Each is a positive integer of 2 or more. ). As shown in fig. 6, the same circuit configuration is repeated, but the arrangement of the transfer control means G1 to G4 corresponds to fig. 4. In the 4 th intersection common region 44 located at the center of the unit cell including the 2 × 2 intersection common region shown in fig. 6, the adjacent photodiode sections PD (p, q), PD (p +1, q), PD (p,q +1) and PD (p +1, q +1) is G4.

The 4 th charge detection part FD4 connected to the upper left photodiode part PD (p, q) of fig. 6 is defined as "the 1 st low resistivity region FD4₄₁". In the 1 st low resistivity region FD, as in FIG. 3₄₁To which 1 st extension capacitors C each having one terminal grounded are connected_41aAnd 1 st auxiliary capacitor C_41bTo the other terminal. "No. 1 extended capacitor C of FIG. 6_41a"corresponds to the 4 th detection unit capacitance C4 shown in fig. 3. 1 st auxiliary capacitor C_41bThe value of (1) may be set according to the intensity of light from the imaging object, or the 1 st storage capacitor C may be used in some cases_41bAre omitted. Further, in the 1 st low resistivity region FD₄₁Connected with a1 st switching element T₄₁1 st main electrode terminal, 1 st switching element T₄₁The 2 nd main electrode terminal of (b) is connected to the gate terminal of the 4 th source follower transistor SF4 constituting the common signal readout circuit a 4. The 4 th source follower transistor SF4 constituting the common signal readout circuit a4 of fig. 6 corresponds to the 4 th source follower transistor SF4 shown in fig. 3, and the gate terminal of the 4 th source follower transistor SF4 of fig. 6 functions as an input terminal of the signal readout circuit a 4.

Similarly, the 4 th charge detection part FD4 connected to the upper right photodiode part PD (p +1, q) of fig. 6 is defined as "the 2 nd low-resistivity region FD4₄₂". In the 2 nd low resistivity region FD₄₂A 2 nd extension capacitor C connected to one terminal of the first and second extension capacitors C_42aAnd 2 nd auxiliary capacitance C_42bTo the other terminal. "No. 2 extended capacitor C of FIG. 6_42a"corresponds to the 4 th detection unit capacitance C4 shown in fig. 3. No. 2 auxiliary capacitor C_42bThe value of (2) may be set according to the intensity of light from the imaging object, and the 2 nd storage capacitor C may be used in some cases_42bAre omitted. Further, in the 2 nd low resistivity region FD₄₂Connected with a 2 nd switching element T₄₂1 st main electrode terminal, 2 nd switching element T₄₂The 2 nd main electrode terminal of (b) is connected to the gate terminal of the 4 th source follower transistor SF4 constituting the common signal readout circuit a 4.

In addition, the 4 th charge detection part FD4 connected to the photodiode part PD (p, q +1) at the lower left of fig. 6 is defined as "the 3 rd low resistivity region FD4₄₃". In the 3 rd low resistivity region FD₄₃A 3 rd extension capacitor C connected to one terminal of the first and second extension capacitors C_43aAnd 3 rd auxiliary capacitor C_43bTo the other terminal. "No. 3 extended capacitor C of FIG. 6_43a"corresponds to the 4 th detection unit capacitance C4 shown in fig. 3. No. 3 auxiliary capacitor C_43bThe value of (3) may be set according to the intensity of light from the imaging object, and the 3 rd storage capacitor C may be used in some cases_43bAre omitted. Further, in the 3 rd low resistivity region FD₄₃Connected with a 3 rd switching element T₄₃1 st main electrode terminal, 3 rd switching element T₄₃The 2 nd main electrode terminal of (b) is connected to the gate terminal of the 4 th source follower transistor SF4 constituting the common signal readout circuit a 4.

Further, a4 th charge detection portion FD4 connected to the photodiode portion PD (p +1, q +1) at the lower right of fig. 6 is defined as a "4 th low-resistivity region FD4₄₄". In the 4 th low-resistivity region FD₄₄A4 th detection part capacitor C connected to one of the terminals_44aAnd 4 th auxiliary capacitance C_44bTo the other terminal. "4 th detection part capacitance C of FIG. 6_44a"corresponds to the 4 th detection unit capacitance C4 shown in fig. 3. 4 th auxiliary capacitor C_44bThe value of (4) may be set according to the intensity of light from the imaging object, and the 4 th auxiliary capacitor C may be used in some cases_44bAre omitted. Further, in the 4 th low resistivity region FD₄₄Connected with a4 th switching element T₄₄1 st main electrode terminal, 4 th switching element T₄₄The 2 nd main electrode terminal of (b) is connected to the gate terminal of the 4 th source follower transistor SF4 constituting the common signal readout circuit a 4.

That is, in fig. 6, in each pixel of the four photodiode sections PD (p, q), PD (p +1, q), PD (p, q +1), and PD (p +1, q +1), the 4 th transfer control means G4, which is a transfer control means classified by the same ordinal number, is connected to the sub-transfer control means G4 to which a capacitance corresponding to the 4 th detection section capacitance C4 shown in fig. 3 is addedLow resistivity region of 1 st FD of the auxiliary capacitance₄₁2 nd low resistivity region FD₄₂3 rd low resistivity region FD₄₃And 4 th low resistivity region FD₄₄。

Four low resistivity regions FD from the common region 44 defined as the 4 th intersection₄₁～FD₄₄The output signals of the charge detection parts are respectively transmitted through the 1 st switching element T₄₁2 nd switching element T₄₂3 rd switching element T₄₃And 4 th switching element T₄₄To the gate terminal of the 4 th source follower transistor SF4 constituting the input terminal of the common signal readout circuit a 4. In fig. 6, the wirings only show the reset transistor drive line Φ RT, the selection transistor drive line Φ SL, and the 1 st output signal line Sig1 in the 4 th intersection common region 44, and the 2 nd output signal line Sig2 adjacent to each other on the left and right. An example of the configuration of the entire wiring will be described later with reference to fig. 8.

Fig. 7 shows the timing of driving in the four-tap manner in the 1 st intersection common region 41 shown in fig. 5 and the configuration of the pixels in the periphery thereof. In addition, although the case of the pulse wave modulation method is described below, the present invention can be applied to the case of the sine wave modulation method. In the case of the sine wave modulation method, the 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the 4 th transfer control means G4 correspond to the phases 0 °, 90 °, 180 °, and 270 °. In the operation of the pulse wave modulation method, first, the first half of the frame period is divided into X full-dummy pixels in synchronization with the light emission pulse as shown in fig. 7 (a)_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}Each of the four taps included in the pixel of (1) simultaneously distributes and stores the electric charges in a global storage period. The four transfer control means G1 To G4 repeat the short pulses with the pulse width Tw and the repetition period To at timings that do not overlap with each other. If the storage period is over, dividing X from each virtual pixel is performed_ijThe pixel of (2) is read out in a line-sequential (rolling) manner.

First, fig. 7 (b) shows the division of all virtual pixels into X_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}The mode in which the signals of the pixels of (1) are independently read out without addition. The switching element T is driven by turning on the 1 st selection transistor SL1 of fig. 5₁₁～T₁₄The switching signals T1 to T4 are turned on in sequence to divide the pixel into X virtual pixels_ij、X_i，(j+1)、X_(i+1)，j、X_(i+1)，_(j+1)The 1 st low-resistivity region FD corresponding to the 1 st charge detector FD1₁₁2 nd low resistivity region FD₁₂3 rd low resistivity region FD₁₃And 4 th low resistivity region FD₁₄Are read out sequentially. Here, each switching element T₁₁～T₁₄The respective on states (on states) preferably do not overlap each other. At each switching element T₁₁～T₁₄The reset transistor RT is turned on and off in the middle of the on period of (b), and reset signals of the respective detection sections are obtained. That is, 4 kinds of signal/reset groups are obtained in time series in 1 signal line. If the CDS operation is performed in the subsequent stage of the signal line, the above-mentioned 4 kinds of net signals can be obtained.

Next, fig. 7 (c) shows a mode in which the unit cells including the 2 × 2 intersection common region are added and read. The switching element T is turned on by the 1 st selection transistor SL1 shown in fig. 5₁₁～T₁₄The switching signals T1 to T4 are turned on simultaneously to divide each virtual pixel into X_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}The 1 st low-resistivity region FD corresponding to the 1 st charge detector FD1₁₁2 nd low resistivity region FD₁₂3 rd low resistivity region FD₁₃And 4 th low resistivity region FD₁₄After the addition of the signals, the added signal is read out. At the switching element T₁₁～T₁₄The 1 st reset transistor RT1 in fig. 5 is turned on and off in the middle of the simultaneous on period, and the added reset signal of the detection unit is obtained. That is, one signal/reset group after addition is obtained in 1 signal line. If CDS operation is performed in the subsequent stage of the signal line, a net signal after addition can be obtained.

In the two-dimensional pixel array of the present invention shown in fig. 4 and 5, various signal line wiring schemes are variously modified, and an example thereof is shown in fig. 8. The drive wirings of the transfer control means G1 to G4, which are global operations, may be vertical or horizontal, but are illustrated in the horizontal direction in fig. 8. Further, by driving the upper and lower circuits in common by 1 wire, the number of wires can be reduced by using the odd-numbered rows as only the upper stage transfer control means G1 and G2 and the even-numbered rows as only the lower stage transfer control means G3 and G4.

Switching element T_c1～T_c4(corresponding to c 1-4: G1-G4) is a line-sequential driving mode, but 2 lines are driven simultaneously, and the odd-numbered lines may be only the 1 st switching elements T, as in the transfer control means G1-G4_c12 nd switching element T_c2Even rows are only used as the 3 rd switching element T_c3The 4 th switching element T_c4The number of wirings is reduced. The c-th reset transistor RTc (corresponding to c1 to 4: G1 to G4) and the c-th selection transistor SLc are arranged in a row order, and the drive lines are wired every 1 row. The vertical wirings are two output signal lines Sig1, Sig2 and the power supply wiring VDD. The output signal lines Sig1 and Sig2 are alternately arranged with 1 pixel apart in the horizontal direction.

Fig. 9 shows a case where all virtual pixels are divided into X in the two-dimensional pixel arrangement of the solid-state imaging device according to embodiment 1 shown in fig. 4, 5, and 8_ijThe timing of the output signal lines Sig1 and Sig2 in a mode in which the signals of the pixels are not added simultaneously but read out independently and sequentially. Here, the read lines are shown for the (k-1) th row, the k-th row, and the (k +1) th row, but the other rows are similarly repeated. In fig. 9, as an example, a virtual pixel is divided by X by a diagonal line rising rightward_(i+1)，_(j+1)And virtual pixel division X_(i+1)，jThe signals of the pixels of (1) are distinguished and illustrated. And virtual pixel division X_{(i+1)，(j+1)}And virtual pixel division X_(i+1)，jThe signals corresponding to the transfer control means G1 to G4 are distributed among two signal lines and four time slots, but are regular. Thus, X is divided for a particular virtual pixel_ijImage ofThe signals of the elements can be regularly obtained corresponding to the four transfer control means G1 to G4, and the distance information can be obtained by integration processing at a later stage.

Fig. 10 shows the timings of the output signal lines Sig1 and Sig2 in a mode in which signals from pixels including unit cells of the 2 × 2 intersection-sharing region are simultaneously added and read in the two-dimensional pixel array of the present invention shown in fig. 4, 5, and 8. Here, the read lines are shown for the (k-1) th row, the k-th row, and the (k +1) th row, but the other rows are similarly repeated. Among signals corresponding to the four transfer control means G1 to G4, signals of the transfer control means G1 and G3 can be obtained from the 1 st output signal line Sig1, and signals of the transfer control means G2 and G4 can be obtained from the 2 nd output signal line Sig2, with respect to signals of pixels of unit cells including a region shared by 2 × 2 intersections. In the case of the addition reading, the range of simultaneous addition differs depending on the type (ordinal number) of the transfer control means as shown in fig. 8.

As shown in fig. 8, for example, focusing on a particular virtual pixel division X_{(i+1)，(j+1)}In the case of the PD (i +1, j +1) of (2), the simultaneous addition range is expanded to a distance calculation allowable range within 3 × 3 pixels in a range where the 1 st transfer control means G1 is the 1 st addition region 81, the 2 nd transfer control means G2 is the 2 nd addition region 82, the 3 rd transfer control means G3 is the 3 rd addition region 83, and the 4 th transfer control means G4 is the 4 th addition region 84.

(embodiment 2)

Fig. 11 shows a circuit configuration of a transfer path control type pixel of a solid-state imaging device according to embodiment 2 of the present invention. If a virtual pixel respectively including three-tap one-tap type TOF pixels shown in FIG. 11 is divided into X_ijDivision X with virtual pixels containing four-tap type TOF pixels as shown in fig. 3_ijIn contrast, in fig. 3, the 4 th transfer control means G4, the 4 th charge detector FD4, the 4 th detector capacitor C4, the 4 th reset transistor RT4, the 4 th source follower transistor SF4, and the 4 th selection transistor SL4 connected to the photodiode PD are not connected to the photodiode PD in fig. 11, and are connected to the photodiode PD instead of the 4 th transfer control means G4And a charge and discharge mechanism GD. The charge discharging mechanism GD discharges charges other than the signal charges, such as charges due to background light (ambient light), to the power supply.

As already described in the description of fig. 4, the area of one unit cell 49 is divided into 2 × 2 virtual pixels. In fig. 4, when the unit cell 49 having a four-tap periodic pattern defined by the 2 × 2 arrangement of the 1 st to 4 th intersection common regions 41 to 44 is assumed, the unit cell 49 is regarded as a repetitive pattern, and in fig. 12, the positions corresponding to the lengths of the virtual pixel divisions in the adjacent columns of the unit cells 122 are repeatedly arranged while being shifted from each other in the column direction. That is, in the solid-state imaging device according to embodiment 2 shown in fig. 12, three tap type unit cells 122 of 2 × 2 group, each of which is composed of the 1 st to 3 rd intersection common regions 41 to 43 surrounded by the same transfer control means G1 to G3 at 4 corners and the discharge region (4 th intersection common region) 121 surrounded by the same charge discharge means GD at 4 corners, are repeatedly arranged with a shift of the length of one virtual pixel division between adjacent unit cells 122. Further, the positions of the 1 st transfer control means G1, the 2 nd transfer control means G2, and the 3 rd transfer control means G3 can be replaced while maintaining the periodicity.

If this is removed, the virtual pixel division X shown in fig. 12 including the three-tap one-bin TOF pixel_ijAnd the virtual pixel division X shown in FIG. 4, which includes four tap type TOF pixels_ijAre the same structure. Thus, the 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the charge discharging means GD shown in fig. 11 may be either insulated gate type transfer control means or transverse electric field control type transfer control means, as in the solid-state imaging device according to embodiment 1. A charge discharging line VRD is connected to one main electrode region (drain region) of the charge discharging mechanism GD. The potentials of the 1 st charge detector FD1, the 2 nd charge detector FD2, and the 3 rd charge detector FD3 are reset (initialized) by the 1 st reset transistor RT1, the 2 nd reset transistor RT2, and the 3 rd reset transistor RT3, respectively.

The reset potential and the signal potential after signal transfer of each of the 1 st charge detector FD1, the 2 nd charge detector FD2, and the 3 rd charge detector FD3 are amplified by the 1 st source follower transistor SF1, the 2 nd source follower transistor SF2, and the 3 rd source follower transistor SF3, respectively, and then the output signals O1 to O3 are read out through the 1 st selection transistor SL1, the 2 nd selection transistor SL2, and the 3 rd selection transistor SL 3. The reset potential and the signal potential read from the output signals O1 to O3 are subjected to CDS processing for obtaining a difference between the reset potential and the signal potential by the signal processing circuit 24 shown in fig. 2, and a net signal is obtained.

The virtual pixel division X including three-tap one-line TOF pixels shown in fig. 12 is used_ijThe two-dimensional array of (1) above can be realized by a method of realizing both a mode of cyclically reading signals from individual pixels and a mode of adding and reading signals from pixels in a 2 × 2 intersection common region in embodiment 1, and can be realized by replacing the 4 th transfer control means G4 with the charge discharging means GD in fig. 4.

Fig. 13 shows the mode switching circuit arranged in the intersection common region in detail. Here, the 3 transfer control means G1 to G3 are the same as those shown in fig. 3 as shown in fig. 13 (a). The charge draining means GD is connected directly to the charge draining wiring VRD as shown in fig. 13 (b), and the capacitance connected to the charge draining wiring VRD is omitted. The circuit configuration of the subsequent steps is the same as that of fig. 13 (a).

FIG. 14 shows the virtual pixel division X shown in FIG. 13_ijThe timing of the driving by the three-tap/one-discharge unit system in the structure. First, in the operation of the solid-state imaging device according to embodiment 2, as shown in fig. 14 (a), X is divided for all the virtual pixels in synchronization with the light emission pulse in the first half of the frame period_ijAnd a global storage period in which charges are distributed to the 1 st charge detector FD1, the 2 nd charge detector FD2, the 3 rd charge detector FD3, and the ejection unit, which constitute three taps, and storage is performed with respect to three taps, and ejection is performed with respect to one ejection unit. The 3 transfer control means G1 To G3 and the charge discharging means GD repeat operations at timings at which the on states of the pulses of the repetition period To do not overlap with each other. Closing deviceThe pulse widths Tw of the transfer control means G1 to G3 are short. If the storage period is over, divide X from each virtual pixel_ijThe pixels of (2) are read out in line order (scrolling).

First, fig. 14 (b) shows division X from all virtual pixels_ijThe operation mode of the solid-state imaging device according to embodiment 2 in which signals are not added simultaneously but read out independently and sequentially. The selection transistor SL is turned on, and the switching element T is driven₁₁～T₁₄The switching signals T1 to T4 are turned on in order to turn on the low-resistivity regions FD1, FD2 and FD3 of the 1 st charge detector FD2 and 3 rd charge detector FD3, respectively₁₁～FD₁₃And a low resistivity region FD corresponding to the drain₁₄Are read out sequentially.

Here, the switching elements preferably do not overlap each other. At each switching element T₁₁～T₁₄Turn on/off the 1 st reset transistor RT1 in the middle of the on period, and obtain the reset signal of each detection unit. That is, 4 kinds of signal/reset groups are obtained in time series in 1 signal line. If the CDS operation is performed in the subsequent stage of the signal line, the above four kinds of net signals can be obtained.

Next, fig. 14 (c) shows an operation mode of the solid-state imaging device according to embodiment 2 in which the unit cells including the 2 × 2 intersection common region are simultaneously added and read. Switching element T by putting the selection transistor SL in the on state₁₁～T₁₄The signals of the charge detection sections FD1 to FD4 are simultaneously added by simultaneously turning on, and then read. At the switching element T₁₁～T₁₄The 1 st reset transistor RT1 is turned on and off in the middle of the simultaneous on period, and a reset signal of the detection section after simultaneous addition is obtained. That is, one signal/reset group after simultaneous addition is obtained in 1 signal line. By performing CDS operation in the subsequent stage of the signal line, a net signal after simultaneous addition can be obtained.

Fig. 15 shows a two-dimensional pixel arrangement of the solid-state imaging device according to embodiment 2 shown in fig. 12 and 13Dividing X from all virtual pixels_ijThe timing of the output signal lines Sig1 and Sig2 in a mode in which the signals of the pixels are not added simultaneously but read out independently and sequentially. Here, the read lines are shown for the (k-1) th row, the k-th row, and the (k +1) th row, but the other rows are similarly repeated. In fig. 15, as an example, X is divided for a virtual pixel by a diagonal line rising rightward_{(i+1)，(j+1)}And virtual pixel division X_(i+1)，jThe signals of the pixels of (1) are distinguished and illustrated. Dividing X with respect to virtual pixels_{(i+1)，(j+1)}And virtual pixel division X_(i+1)，jThe signals of the pixels (b) and the signals corresponding to the 3 transfer control means G1 to G3 are distributed in two signal lines and four time slots, but are regular.

In this way, according to the solid-state imaging device of embodiment 2, X is divided for a specific virtual pixel_ijThe signals of the pixels (a) can regularly obtain signals corresponding to the 3 transfer control means G1 to G3, and can be integrated in the subsequent stage to obtain distance information. However, in comparison with the case of fig. 9, the dummy (dummy) signal D (i, j) is present on the 2 nd output signal line Sig2 side every 1 row. Further, as shown in fig. 12, since the unit cells 122 including the 2 × 2 intersection common region are repeatedly arranged with a shift of 1 pixel apart, the dummy signals D (i, j) are shifted by 1 line between signals of the 2 nd output signal line Sig2 located in the left-right direction with respect to the 1 st output signal line Sig 1.

That is, in the 2 nd output signal line Sig2 adjacent to the 2 nd output signal line Sig2 with the 1 st output signal line Sig1 interposed therebetween, the 2 nd output signal line Sig2 (k-1) and the 2 nd output signal line Sig2(k +1) become the 2 nd transfer control means G2 signal, and the 2 nd output signal line Sig2(k) becomes the dummy signal D. By doing so, the dummy signal D is included in all the line signals at 1 pixel intervals, and the difference between the in-line average value of the dummy signal and the in-line average value of each pixel signal can be obtained using the dummy signal as a reference for the line-related noise, thereby making it possible to suppress the line noise.

Fig. 16 shows timings of the 1 st output signal line Sig1 and the 2 nd output signal line Sig2 in a case of a mode in which signals from pixels of the unit cell 122 including the 2 × 2 intersection common region are simultaneously added and read out in the two-dimensional pixel arrangement of the solid-state imaging device according to embodiment 2 shown in fig. 12 and 13. Here, the read lines are shown for the (k-1) th row, the k-th row, and the (k +1) th row, but the other rows are similarly repeated. Regarding the signals of the pixels of the unit cell 122 including the 2 × 2 intersection common region, among the signals corresponding to the 3 transfer control means G1 to G3, the signals of the 1 st transfer control means G1 and the 3 rd transfer control means G3 are obtained from the 1 st output signal line Sig1, and the 2 nd transfer control means G2 signal and the dummy signal are obtained from the 2 nd output signal line Sig 2. In the 2 nd output signal line Sig2 adjacent to the 2 nd output signal line Sig2 of fig. 16 with the 1 st output signal line Sig1 interposed therebetween, the 2 nd output signal line Sig2 (k-1) and the 2 nd output signal line Sig2(k +1) are signals of the 2 nd transfer control means G2, and the 2 nd output signal line Sig2(k) is a dummy signal D.

The combination of the additions of the unit cells 122 is a form in which only G4 is removed in fig. 8, for example, focusing on a specific virtual pixel division X_{(i+1)，(j+1)}In the case of the PD (i +1, j +1) of (2), the addition range is expanded to a distance calculation allowable range within 3 × 3 pixels which is within a range where the 1 st transfer control means G1 is the 1 st addition region 51, the 2 nd transfer control means G2 is the 2 nd addition region 52, and the 3 rd transfer control means G3 is the 3 rd addition region 53. In addition, the method divides all virtual pixels into X_ijSimilarly to the case where the signals of the pixels are not added simultaneously but read out independently and sequentially, since the dummy signal D is obtained for all the rows from the 2 nd output signal line Sig2, the dummy signal D can be used as a reference for the row-related noise, and the difference from the in-row average value of the dummy signal D can be obtained from each pixel signal, thereby making it possible to suppress the row noise.

(embodiment 3)

Fig. 17 shows a two-dimensional arrangement different from fig. 4, with respect to a method capable of realizing a pattern in which signals are cyclically read from individual pixels and a pattern in which signals are additively read from pixels in a 2 × 2 intersection common region. In the solid-state imaging device according to embodiment 3, the unit cell including the 2 × 2 intersection common region is notArranged in a square shape, but divided into X virtual pixels adjacent to each other on the left and right_ijThe parallelogram array is shifted by 1/2 virtual pixel division length in the vertical direction (column direction). The 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the 4 th transfer control means G4 shown in fig. 17 may be transfer control means of an insulated gate type or transfer control means of a lateral electric field control type, as in the solid-state imaging devices according to the 1 st and 2 nd embodiments, respectively.

In addition, if a range including a 2 × 2 intersection common region arranged in a parallelogram is defined as the unit cell 171, a 2 × 2 virtual pixel division is accommodated in the area of one unit cell 171. Therefore, the periodic repetition shown in fig. 17 is an arrangement in which the unit cells 171 adjacent to each other on the left and right are shifted by the length of one virtual pixel division. By dividing X by two adjacent virtual pixels_ijThe virtual pixel divisions X are arranged so that transfer control means classified by the same ordinal number are close to each other in each transfer control means_ijThereby forming a division X for the virtual pixels by the same kind of transfer control mechanism_ijThe area surrounded by the mode switching circuit of (3) is repeated in units of 2 × 2 groups of the area, as in the case of fig. 4. The mode in which signals are cyclically read from individual pixels and the mode in which signals are additively read from pixels in a 2 × 2 intersection common region in this case are described below. The arrangement of fig. 17 is characterized by a different spatial resolution compared to the arrangement of fig. 4.

Fig. 18 shows an example of wiring of the solid-state imaging device according to embodiment 3 in the arrangement of fig. 17. The driving wirings of the transfer control means G1 to G4 which operate as a global circuit are arranged in the horizontal direction, and are connected to the driving lines RT of the reset transistor, the driving lines SL of the selection transistor, and the switching element T_c1～T_c4The driving lines T1 to T4 together form a vertical virtual pixel division X_ijThe space bending is in a triangular shape. Dividing X at virtual pixel requiring each gate drive signal_ijIn the common region of intersection points of (3), since the wiring bent in a triangular shape is configured to be concentrated from the top and bottom, it is possible to make the wiring in each rowAll the transverse wirings are divided into two. That is, 5 lines can be arranged for 10 lines in total of RT, SL, G1 to G4, and T1 to T4. The vertical wirings are two signal lines Sig1, Sig2 and a power supply wiring VDD, and divide X into left and right virtual pixels_ijThe space bending is in a triangular shape. The 1 st output signal line Sig1 and the 2 nd output signal line Sig2 are arranged alternately with 1 pixel apart in the horizontal direction.

FIG. 19 shows the layout of FIG. 17, with the wiring of FIG. 18 applied, with all the dummy pixels from the layout divided by X_ijThe timing of the 1 st output signal line Sig1 and the timing of the 2 nd output signal line Sig2 in the operation of the solid-state imaging device according to embodiment 3, in which the signals of the pixels are not added simultaneously but read out independently and sequentially. Here, the read lines are shown for the (k-1) th row, the k-th row, and the (k +1) th row, but the other rows are similarly repeated. With respect to a particular virtual pixel division X_ijThe signals of the pixels (2) are divided into X portions by the virtual pixels with a diagonal line rising leftward, as an example, among the signals corresponding to the four transfer control means G1-G4_{(i+1)，(j+1)}The signals of the pixels of (a) are shown as being distinguished. Each signal is dispersed in two signal lines and four time slots, but is regular, and distance information can be obtained by integration processing at a later stage.

Fig. 20 shows the timings of the 1 st output signal line Sig1 and the 2 nd output signal line Sig2 in the operation mode of the solid-state imaging device according to embodiment 3 in which the wiring of fig. 18 is applied to the arrangement of fig. 17 and signals from the pixels of the unit cell 171 including the 2 × 2 intersection common region are added and read out at the same time. Here, the read lines are shown for the (k-1) th row, the k-th row, and the (k +1) th row, but the other rows are similarly repeated. Among signals corresponding to the four transfer control means G1 to G4, signals of all of the four transfer control means G1 to G4 can be obtained from the 1 st output signal line Sig1 and the 2 nd output signal line Sig2 in different orders.

(embodiment 4)

Dividing X at virtual pixels each including three-tap one-tap TOF pixels_ijIn a two-dimensional arrangement of (2), can be oneThe method of realizing the mode of cyclically reading signals from individual pixels and the mode of adding and reading signals from pixels in the 2 × 2 intersection common region according to embodiment 1 can be realized by replacing the 4 th transfer control means G4 with the charge discharging means GD that discharges charges other than signal charges to the power supply in fig. 17. The method of cyclically reading signals from individual pixels and the method of additively reading signals from pixels in a 2 × 2 intersection common region in the solid-state imaging device according to embodiment 4 shown in fig. 21 are the same as in the case of fig. 17, and the description thereof is omitted. The 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the charge discharging means GD shown in fig. 21 may be either insulated gate type transfer control means or transverse electric field control type transfer control means, as in the solid-state imaging devices according to embodiments 1 to 3.

In the case where the wiring of fig. 18 is implemented in fig. 21, since the dummy signal corresponding to the charge draining means GD is included in all the rows, the solid-state imaging device according to embodiment 4 can use the dummy signal as a reference of the row-related noise, and can suppress the row noise by obtaining the difference from the pixel signal to the intra-row average value of the dummy signal, as in the case of fig. 12, 15, and 16.

(other embodiments)

The present invention is described in the above-described 1 st to 4 th embodiments, but the discussion and drawings which are part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and application techniques will be apparent to those skilled in the art in light of this disclosure. Having used fig. 22 (b), there is shown a division X of the four virtual pixels shown in fig. 22 (a)_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}The 1 st intersection common region 41 of a 45-degree-inclined quadrangle (rhombus) is defined by chamfering the respective vertex angles with 45-degree lines, and the virtual pixels are divided into X_(i－1)，j、X_{(i－1)，(j+1)}、X_i，j、X_i，(j+1)The respective apex angles are chamfered by 45 degrees to define the 2 nd intersection of the diamondA dot sharing region 42 for dividing the virtual pixel into X_i，(j+1)、X_i，(j+2)、X_{(i+1)，(j+1)}、X_{(i+1)，(j+2)}The 3 rd intersection common region 43 of the diamond shape is defined by line chamfering of 45 degrees at each vertex angle, and the virtual pixels are divided into X_{(i－1)，(j+1)}、X_{(i－1)，(j+2)}、X_i，(j+1)、X_i，(j+2)The top corners of the diamond-shaped common region 44 for the 4 th intersection are defined by line chamfers of 45 degrees, but this is merely an example.

For example, as shown in fig. 25, the four virtual pixels shown in fig. 22 (a) may be divided into X_ij、X_i，(j+1)、X_(i+1)，j、X_{(i+1)，(j+1)}The corner angles are cut out in a stepped manner by right-angled recesses to define a common region 41c for the 1 st intersection of the quadrangle. Likewise, the virtual pixels may also be divided into X_(i－1)，_j、X_{(i－1)，(j+1)}、X_i，j、X_i，(j+1)The vertex angles are cut out by right-angled recesses to define a 2 nd intersection common region 42c of a quadrangle, and the virtual pixels are divided into X_i，(j+1)、X_i，(j+2)、X_{(i+1)，(j+1)}、X_(i+1)，_(j+2)The 3 rd intersection common region 43c of a quadrangle is defined by cutting out a rectangular concave portion at each vertex angle, and the virtual pixels are divided into X_{(i－1)，(j+1)}、X_{(i－1)，(j+2)}、X_i，(j+1)、X_i，(j+2)The respective vertex angles are cut out with right-angled recesses to define the 4 th intersection common region 44 c.

Further, fig. 5 shows that the 1 st low resistivity region FD is disposed on each of 4 chamfer lines formed by cutting off the corner angle of each dummy pixel at 45 degrees₁₁2 nd low resistivity region FD₁₂3 rd low resistivity region FD₁₃And 4 th low resistivity region FD₁₄And defines four low resistivity regions FD realizing a four tap type₁₁～FD₁₄Examples of (3). However, the four-tap or three-tap/one-bank type pixels described in embodiments 1 to 4 are merely examples, and are not limited to the four-tap or three-tap/one-bank type pixels, and may be the pixels shown in fig. 26Such an eight tap type. In fig. 26, two low resistivity regions are disposed on 4 chamfer lines each having a vertex angle of a dummy pixel divided by 45 degrees, and eight tap types are realized by eight low resistivity regions. In this case, the unit cell is set in a range including the 2 × 2 intersection common region.

That is, in fig. 26 focusing on the 1 st intersection common region 41o, the 1 st transfer control means G1 of the four photodiode sections PD (i, j), PD (i +1, j), PD (i, j +1), and PD (i +1, j +1) is connected to the 1 st low resistivity region FD_11o3 rd low resistivity region FD_13o5 th low-resistivity region FD_15oAnd 7 th low resistivity region FD_17o. From four low-resistivity regions FD_11o～FD_17oThe output signals of the charge detection units are input to a common 1 st signal readout circuit via 1 st to 4 th switching elements, not shown. The 5 th transfer control means G5 of the four photodiode sections PD (i, j), PD (i +1, j), PD (i, j +1) and PD (i +1, j +1) surrounding the 1 st intersection common region 41o is connected to the 2 nd low resistivity region FD_12o4 th low resistivity region FD_14o6 th low-resistivity region FD_16oAnd 8 th low resistivity region FD_18o. From four low-resistivity regions FD_12o～FD_18oThe output signals of the charge detection units are input to a common 5 th signal readout circuit via 5 th to 8 th switching elements, not shown.

The same applies to the 2 nd to 4 th intersection common regions not shown in fig. 26, and even in the case of the eight tap type, similarly to the 1 st to 4 th embodiments, the eight switching elements are arranged in all the 1 st to 4 th intersection common regions, and the eight switching elements are operated to be able to merge (binding). In addition, if one low resistivity region is disposed on each of the sides constituting the step in fig. 25, which are cut out by the right-angled recesses at the corners of the virtual pixel division, two low resistivity regions are disposed at each of the cut-out corners, and therefore, even in the topology shown in fig. 25, an eight-tap type solid-state imaging device can be realized. In this case, the unit cell is also set in a range including the 2 × 2 intersection common region.

In embodiments 1 to 4, the virtual pixel division X is made_ijA photodiode section PD of a part of the transfer path control type pixel_ijThe planar pattern of (a) has been described as a case of a quadrangle, but if the shape of the front planar filling of pythagoras is adopted, the shape of the photodiode section PD may be a triangle as shown in fig. 27 or a hexagon as shown in fig. 28. FIG. 27 shows the topology of a virtual pixelized tile that forms a regular triangle, a kind of "planar filling shape" in geometric mathematics. Each pixel includes one photodiode section PD and three transfer control mechanisms connected to the photodiode section PD. The three transfer control means are respectively given the 1 st to 3 rd ordinal numbers (ordinal numbers), and are divided into the 1 st transfer control means G1, the 2 nd transfer control means G2 and the 3 rd transfer control means G3, and constitute a three-tap type pixel. The 1 st transfer control means G1, the 2 nd transfer control means G2, and the 3 rd transfer control means G3 control the transfer path and the transfer direction of the signal charge corresponding to the three taps independently.

In fig. 27, a region surrounded by the same ordinal number of regular hexagons surrounded by six adjacent 1 st transfer control mechanisms G1 at the center portion thereof is defined as "1 st intersection common region 45 t". The 1 st intersection common region 45t is a region where intersections are shared with each other around intersections of meshes defined by the outer peripheries divided by six virtual pixels. In the case of a regular triangle, as shown in fig. 27, six corners meet at a point of intersection. The 1 st intersection common region 45t is a region of a regular hexagon formed by chamfering the vertex where the 1 st transfer control means G1 is located, as shown in fig. 27, by dividing six virtual pixels. The 1 st intersection common region 45t is surrounded by the photodiode section PD (s, r), the photodiode section PD (s +1, r-1), the photodiode section PD (s-1, r-1), and the photodiode section PD (s-1, r) (r is 1 to m)₃，s＝1～n₃：m₃、n₃Each is a positive integer of 2 or more. ).

Similarly, a region surrounded by the same ordinal number of a regular hexagon surrounded by six adjacent 2 nd transfer control mechanisms G2 is defined as a "2 nd intersection common region 46 t". The 2 nd intersection common region 46t is a region where intersections where six vertex angles meet each other are shared, with the intersections of meshes defined by the outer peripheries of the six virtual pixels being the centers. As shown in fig. 27, the 2 nd intersection common region 46t is a region of a regular hexagon formed by chamfering a vertex where the 2 nd transfer control means G2 is located at each of six virtual pixels at an intersection. Further, a region surrounded by the same ordinal number of the regular hexagon surrounded by six adjacent 3 rd transfer control means G3 is referred to as "3 rd intersection common region 47 t". The 3 rd intersection common region 47t is a region where intersections where six vertex angles meet each other are shared, with the intersections of meshes defined by the outer peripheries of the six virtual pixels being the centers. The 3 rd intersection common region 47t is a region of a regular hexagon formed by chamfering the vertex where the 3 rd transfer control means G3 is located at the intersection with six virtual pixels, as shown in fig. 27.

Since three corners at which the 1 st transfer controller G1, the 2 nd transfer controller G2, and the 3 rd transfer controller G3 are located are chamfered and cut, outer shapes of the photodiode sections PD (s, r), PD (s +1, r +1), … …, and the like, which are scalene hexagons, are defined. As can be seen from fig. 27, the photodiode section PD (s, r) (s is 1 to m)₃，r＝1～n₃：m₃、n₃Each is a positive integer of 2 or more. ) The 1 st tile of the inequilateral hexagon occupied, and the 2 nd tile of the regular hexagon occupied by the 1 st intersection common region 45t, the 2 nd intersection common region 46t, and the 3 rd intersection common region 47 t. As shown in fig. 27, even when the virtual pixel division is formed as a regular triangle, as in the case of embodiments 1 to 4, six switching elements are arranged in all of the 1 st intersection common region 45t, the 2 nd intersection common region 46t, and the 3 rd intersection common region 47t, and the six switching elements are operated, whereby the 1 st intersection common region 45t, the 2 nd intersection common region 46t, and the 3 rd intersection common region 47t can be combined. In the above description, the virtual pixel division is not limited to the regular triangle, and may be the same as the regular triangleA waist triangle. In this case, in fig. 27, the entire pixel region is enlarged or reduced in the left-right direction or the up-down direction.

Fig. 28 and 29 show the topology of a tile forming a virtual pixel division of a regular hexagon, which is one kind of "planar filling shape" in geometric mathematics. As shown in the enlarged view of fig. 28 in fig. 29, each pixel includes one photodiode PD and six transfer control units connected to the photodiode PD. The six transfer control means are respectively given the 1 st to 6 th ordinal numbers (ordinal numbers), and are divided into the 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, … …, and the 6 th transfer control means G6, and constitute a six-tap type pixel. The 1 st to 6 th transfer control means G1 to G6 independently control the transfer path and the transfer direction of the signal charge corresponding to the six taps, respectively.

The same ordinal number surrounding region of the inequilateral nonagon surrounded by the three adjacent 1 st transfer control mechanisms G1 on the upper center side in fig. 29 is defined as "1 st intersection common region 61". The 1 st intersection common region 61 is a region where intersections are shared with each other around intersections of meshes defined by the outer peripheries divided by three virtual pixels. The 1 st intersection common region 61 is a region of an inequilateral nonagon formed by dividing three virtual pixels into corner chamfers where the 1 st transfer control mechanisms G1 are located, as shown in fig. 29. The 1 st intersection common region 61 is surrounded by the photodiode section PD (μ, ν), the photodiode section PD (μ +1, ν -1), and the photodiode section PD (μ -1, ν -1) (μ ═ 1 to m₄，ν＝1～n₄：m₄、n₄Each is a positive integer of 2 or more. ).

Similarly, in the lower right direction of the 1 st intersection common region 61, an area surrounded by the same ordinal number of the inequilateral nonagon surrounded by the three adjacent 2 nd transfer control mechanisms G2 is defined as the "2 nd intersection common region 62". The 2 nd intersection common region 62 is a region where intersections are shared with each other around intersections of meshes defined by the outer peripheries divided by the three virtual pixels. As shown in fig. 29, the 2 nd intersection common region 62 is a region of an inequilateral nonagon formed by dividing three virtual pixels at an intersection into chamfered corners where the 2 nd transfer control means G2 are located. The 2 nd intersection common region 62 is surrounded by the photodiode section PD (μ, ν), the photodiode section PD (μ +2, ν), and the photodiode section PD (μ +1, ν -1).

Further, below the 2 nd intersection common region 62, an enclosed region of the same ordinal number of the inequilateral nonagon enclosed by the three adjacent 3 rd transfer control means G3 is referred to as a "3 rd intersection common region 63". The 3 rd intersection common region 63 is a region where intersections are shared with each other around intersections of meshes defined by the outer peripheries of the three virtual pixels. As shown in fig. 29, the 3 rd intersection common region 63 is a region of an inequilateral nonagon formed by dividing three virtual pixels at an intersection into chamfered corners where the 3 rd transfer control means G3 is located. The 3 rd intersection common region 63 is surrounded by the photodiode section PD (μ, ν), the photodiode section PD (μ +1, ν +1), and the photodiode section PD (μ +2, ν).

Similarly, a "4 th intersection common region 64" of a scalene nonagon surrounded by three adjacent 4 th transfer controllers G4, a "5 th intersection common region 65" of a scalene nonagon surrounded by three adjacent 5 th transfer controllers G5, and a "6 th intersection common region 66" of a scalene nonagon surrounded by three adjacent 6 th transfer controllers G6 are defined. Since the three corners at which the 1 st to 6 th transfer control means G1 to G6 are located are chamfered and cut off, the photodiode section PD (μ, ν) is formed of a non-equilateral 24-sided polygon (μ ═ 1 to m)₄，ν＝1～n₄：m₄、n₄Positive integers of 2 or more, respectively).

As is clear from fig. 29, the tile is filled with two kinds of tiles, namely, the 1 st tile of the inequilateral 24-sided polygon occupied by the photodiode section PD (μ, ν) and the 2 nd tile of the inequilateral nonagon occupied by the 1 st intersection common region 61 to the 6 th intersection common region 66. As can be seen from fig. 28, in the case of the regular hexagonal virtual pixel division, unit cells 172 including a region shared by 13 × 2 — 26 intersections are used as units of a periodic pattern, and the respective virtual pixel divisions are repeatedly arranged in the pixel array unit 1 shown in fig. 2. As shown in fig. 29, even when the virtual pixel division is formed as a regular hexagon, the switching elements are arranged in all of the 1 st to 6 th intersection common regions 61 to 66, and the switching elements are operated, so that the switching elements can be integrated in all of the 1 st to 6 th intersection common regions 61 to 66, as in the 1 st to 4 th embodiments.

Planar filling is also possible when two kinds of rhombic Penrose lattices (Penrose tiles) are used, but a periodic pattern is not present in the Penrose lattices. In the case of non-periodic planar filling such as a penrose dot matrix, since a logic circuit for driving and reading is not configured and signal line routing is not possible any longer, it is practically impossible to form a two-dimensional solid-state imaging device. However, when the pattern has a periodic pattern, even if the pattern has a shape other than the regular planar filling shape, the number of taps corresponding to the shape can be used as long as the tile filling is possible, and a two-dimensional solid-state imaging device can be configured.

With respect to the convex pentagon which can be tiled in a manner that no gap occurs, the 15 th was found in 2015 after 30 years, and a paper of proof that does not exist beyond these was also proposed. For example, as one of the 15 types, it is possible to allow the filling with the pentagon as shown in fig. 30 and 31.

Fig. 30 and 31 show the topology of a tile of virtual pixel division forming an unequal-angle pentagon. As shown in the enlarged view of fig. 30 in fig. 31, each pixel includes one photodiode PD and five transfer control units connected to the photodiode PD. The five transfer control means are respectively given the 1 st to 3 rd and 1 st to 2 nd ordinal numbers, and are divided into the 1 st transfer control means G1, the 2 nd transfer control means G2 and the 3 rd transfer control means G3, and the 1 st charge discharging means GD1 and the 2 nd charge discharging means GD2, and constitute a pixel of a three-tap two-discharge-unit type. The 1 st to 3 rd transfer control means G1 to G3 control the transfer paths and the transfer directions of the signal charges corresponding to the three taps independently, and the 1 st and 2 nd charge discharging means GD1 and GD2 discharge the charges other than the signal charges, such as the charges due to the background light (ambient light), to the power supply.

The same ordinal number surrounding region of a triangle surrounded by three adjacent 1 st transfer control mechanisms G1 on the left side of the center in fig. 31 is defined as "1 st intersection common region 71". The 1 st intersection common region 71 is a region where intersections are shared with centers of intersections of meshes defined by the outer peripheries divided by three virtual pixels. The 1 st intersection common region 71 is a triangular region formed by chamfering the vertex where the 1 st transfer control means G1 is located, with three virtual pixels, as shown in fig. 31. Intersection 1-th common region 71 is surrounded by photodiode section PD (w-1, x +1), photodiode section PD (w-1, x-1), and photodiode section PD (w-3, x) (w is 1 to m)₅，x＝1～n₅：m₅、n₅Each is a positive integer of 2 or more. ).

Similarly, the same ordinal number surrounding area of the triangle surrounded by three adjacent 2 nd transfer control mechanisms G2 is defined as "2 nd intersection common area 72". The 2 nd intersection common region 72 is a region where intersections are shared with each other around intersections of meshes defined by the outer peripheries divided by the three virtual pixels. The 2 nd intersection common region 72 is, as shown in fig. 31, a triangular region formed by chamfering the vertex where the 2 nd transfer control means G2 is located at each intersection by dividing three virtual pixels. The 2 nd intersection common region 72 is surrounded by the photodiode section PD (w-1, x +1), the photodiode section PD (w +1, x), and the photodiode section PD (w-1, x-1).

Next, a "3 rd intersection common region 73" of a quadrangle surrounded by four adjacent 1 st electric charge discharging mechanisms GD1 is defined as a "1 st discharging region". The 3 rd intersection common region 73 is a region where intersections are shared with each other around intersections of meshes defined by the outer peripheries divided by four virtual pixels. As shown in fig. 31, the 3 rd common intersection region 73 is a quadrangular region formed by chamfering the vertex where the 1 st charge-discharging means GD1 is located at the intersection to divide the four virtual pixels. Intersection 3-th common region 73 is surrounded by photodiode section PD (w-1, x +1), photodiode section PD (w +1, x +2), and photodiode section PD (w, x + 3).

Further, the same ordinal number surrounding regions of the triangle surrounded by the three adjacent 3 rd transfer control means G3 are referred to as "4 th intersection common region 74", respectively. The 4 th intersection common region 74 is a region where intersections are shared with each other around intersections of meshes defined by the outer peripheries divided by the three virtual pixels. The 4 th intersection common region 74 is a triangular region formed by chamfering the vertex where the 3 rd transfer control means G3 is located at each of the three virtual pixels at the intersection, as shown in fig. 31. Intersection 4 common region 74 is surrounded by photodiode section PD (w-1, x +1), photodiode section PD (w, x +3), and photodiode section PD (w-2, x + 3).

Further, "the 5 th intersection common region 75" of a quadrangle surrounded by four adjacent 2 nd electric-charge discharging mechanisms GD2 is defined as a "2 nd discharging region". The 5 th intersection common region 75 is a region where intersections are shared with each other around intersections of meshes defined by the outer peripheries divided by four virtual pixels. As shown in fig. 31, the 5 th common intersection region 75 is a quadrangular region formed by chamfering the vertex where the 2 nd charge discharging means GD2 is located at the intersection to divide the four virtual pixels. As is clear from fig. 30, the 5 th intersection common region 75 is surrounded by the photodiode section PD (w-1, x +1), the photodiode section PD (w +1, x), the photodiode section PD (w-2, x +3), the photodiode section PD (w-4, x +2), and the photodiode section PD (w-3, x).

Since five vertex angles at which the 1 st transfer control means G1, the 2 nd transfer control means G2, the 3 rd transfer control means G3, and the 1 st electric charge discharge means GD1 and the 2 nd electric charge discharge means GD2 are located are chamfered and cut out, the photodiode section PD (w, x) formed of an inequilateral decagon is defined (w is 1 to m)₅，x＝1～n₅：m₅、n₅Positive integers of 2 or more, respectively). As is clear from fig. 31, three types of tiles, i.e., the 1 st tile of the inequilateral decagon occupied by the photodiode section PD (w, x), the 2 nd tile of the triangle occupied by the 1 st intersection common region 71, the 2 nd intersection common region 72, and the 4 th intersection common region 74, and the 3 rd tile of the quadrangle occupied by the 3 rd intersection common region 73 and the 5 th intersection common region 75 are filled.

As shown in fig. 31, even when the virtual pixel division is formed by an unequal-angle pentagon, as in embodiments 1 to 4, the switching elements are arranged in all of the 1 st intersection common region 71, the 2 nd intersection common region 72, and the 4 th intersection common region 74, and by operating the switching elements, the switching elements can be integrated in all of the 1 st intersection common region 71, the 2 nd intersection common region 72, and the 4 th intersection common region 74.

In the explanation of fig. 31, the charge discharging mechanism is provided in the 1 st charge discharging mechanism GD1 and the 2 nd charge discharging mechanism GD2 surrounded by four virtual pixel divisions, but these mechanisms may be used for individual and combined reading of the charges of the corresponding four virtual pixel divisions. In this case, 3/4 times the added pixel signal may be used to match the added pixel signal with the added pixel signals in the three virtual pixel divisions.

In this specification, the description of the tiles formed by 14 types of pentagons other than the pentagon shown in fig. 30 and 31 will be omitted. However, regarding the three-pixel addition group and the four-pixel addition group similar to those shown in fig. 31, the periodicity of the pattern can be possessed by the pentagonal tiles, and the two-dimensional arrangement of the solid-state imaging device can be configured using the other 14 types of pentagons.

As can be understood from fig. 30 and 31, regarding the periodicity of the patterns of the 15 kinds of pentagonal tiles which are mathematically considered possible, when three pixels of the intersection common region where the three corners meet are set as a group, repetition in units of four groups can be selected. When four pixels in an intersection common region where four corners meet each other are set as a group, repetition in units of each group can be selected.

In the case of a pattern in which the repetition period is long, the arrangement direction is inclined, and the wirings for driving and reading become complicated, the arrangement of the wirings which are substantially horizontal and vertical can be selected by elaborating the layout by rotating the pattern by 45 degrees or the like. The two-dimensional arrangement of pixels may not be a complete tile fill as long as the allowable area efficiency is reduced, and a solid-state imaging device may be configured by arranging horizontal and vertical wirings by providing a small space.

As such, it is known in the field of geometric mathematics to: there is a method in which tiles can be tiled without gaps by pentagons and hexagons, but there is no method in which tiles can be tiled without gaps by a convex pattern of heptagons or more. As for the convex hexagons that can be tiled without generating gaps such as small triangles, the mathematic charter Karl-ogust-leinhardt (Karl August Reinhardt) in 1918 issued 3 types of convex hexagons other than the regular hexagons, proving that there are no convex hexagons other than the regular hexagons.

On the other hand, all parallelograms can be plane-filled in one way. All the triangles are made into a parallelogram by combining two equal triangles. Thus, all triangles can be plane-filled in such a way that six vertices meet at an intersection. Since the intersection-sharing region can be defined if the planar tiling can be performed without generating a gap, the intersection-sharing regions can be merged as in embodiments 1 to 4.

The parallel hexagon is divided into two equal pentagons by a straight line passing through the center. As can be appreciated from fig. 30, such a pentagon can be flat and full. Thus, in embodiments 1 to 4, a four-tap or three-tap/one-drain type pixel is exemplified for description, but a three-tap/two-drain type, a five-tap/one-drain type, a six-tap type, or the like may be adopted as the pixel structure.

As a more general example, consider a case where L is a positive integer of 3 or more, and corners of virtual pixel divisions having L corners are next to each other at intersections of meshes of a tile constituted by the outline of the virtual pixel division. In a virtual pixelized tile having L corners, three or four corners meet at an intersection of the meshes of the tile. If the M-L tap type solid-state imaging device is realized if the M-L low resistivity regions as described in embodiments 1 to 4 are disposed in the L intersection common regions defined by cutting out the L apex angles, respectively, and if one charge discharging unit is provided at one of the L apex angles, a solid-state imaging device for distance imaging or the like of the M-L tap type can be realized. Thus, M is a positive integer of 2 or more.

However, if M is 2L low resistivity regions are disposed in each of the L intersection common regions, a solid-state imaging device such as a 2L tap type distance imaging device can be realized, and if one charge discharging unit is provided at one of the L apex angles, a solid-state imaging device such as a (2L-1) tap type distance imaging device can be realized. As shown in fig. 31, if two charge discharging units are provided in each pixel, a solid-state imaging device for distance imaging of the M-2 (L-2) tap type or the like can be realized. Similarly, if 3L low resistivity regions are disposed in each of the L intersection common regions, it is possible to realize a 3L tap type (3L-1) tap type, 3 (L-2) tap type solid-state imaging device for distance imaging, and the like.

For example, if the virtual pixels are divided into corners and the corners are cut out by recesses having three sides intersecting at an angle of 135 degrees in fig. 25, and one low-resistivity region constituting the charge detection section is disposed on each of the three sides constituting the cut-out section, three low-resistivity regions can be disposed on each of the cut-out corners. However, even if each pixel is of a 3-tap type as shown in fig. 27, N2M 6 charge detection units are disposed in each intersection common region 45t, 46t, and 47 t. On the other hand, even if each pixel is of a 6 tap type as shown in fig. 29, N-3 charge detection units are arranged in each intersection common region 61-66. Thus, N is a positive integer of 3 or more. Thus, the number of corners L, the number of taps M, and the number N of charge detection units arranged in the intersection-common region of the polygons forming the virtual pixel division of the planar fill shape do not need to match each other.

Further, although the description of embodiment 1 and the like have been given with reference to the 1 st conductivity type being p-type and the 2 nd conductivity type being n-type, it should be readily understood that even if the 1 st conductivity type is n-type and the 2 nd conductivity type is p-type, the same effects can be obtained by reversing the electrical polarities.

As described above, the present invention includes various embodiments and the like not described above, and the technical scope of the present invention is determined only by the invention specific matters of the appropriate claims from the above description.

Description of the reference symbols

1 … pixel array section; 11 … TOF range camera system; 12 … light source; 13 … imaging optics; 14 … solid-state imaging device (TOF imaging device); 15 … image processing circuitry; 16 … object; 17 … irradiating light; 18 … reflects light; 23 … horizontal scanning circuit; 24 … signal processing circuitry; 25 … control circuitry; 41-44, 41 c-44 c, 45 t-47 t, 61-66, 71-75 … intersection point sharing region, 49, 122, 171, 172 … unit cells; 51. 81 … addition 1 region; 52. 82 … addition 2 region; 53. 83 … addition 3 region; 84 … addition 4 region; 121 … discharge area (4 th intersection common area).