阅读说明：本技术 显示基板、显示面板和显示装置 (Display substrate, display panel and display device ) 是由 徐文结 赵雪 谢晓冬 何敏 桑华煜 张新秀 庞斌 於飞飞 于 2021-09-06 设计创作，主要内容包括：本公开实施例提供一种显示基板、显示面板和显示装置。显示基板,具有第一边缘,包括衬底基板以及位于衬底基板上且阵列排布的多个焊盘组,绑定区位于第一边缘与第一行焊盘组之间,绑定区设置有多个绑定焊垫,多个绑定焊垫位于衬底基板的朝向焊盘组的一侧,扇出区的至少部分位于第一行焊盘组和第三行焊盘组之间,扇出区设置有多条信号引线,多条信号引线位于衬底基板的朝向焊盘组的一侧。本公开实施例中的显示基板适用于拼接显示装置,显示基板避免了采用侧面走线以及绑定区设置在显示基板背侧等复杂工艺,降低了显示装置的制作成本,可以满足对成本敏感的客户需求。(The embodiment of the disclosure provides a display substrate, a display panel and a display device. The display base plate is provided with a first edge and comprises a substrate base plate and a plurality of pad groups which are arranged on the substrate base plate in an array mode, a binding region is located between the first edge and the first row of pad groups and is provided with a plurality of binding pads, the binding pads are located on one side, facing the pad groups, of the substrate base plate, at least part of a fan-out region is located between the first row of pad groups and the third row of pad groups, the fan-out region is provided with a plurality of signal leads, and the signal leads are located on one side, facing the pad groups, of the substrate base plate. The display substrate in the embodiment of the disclosure is suitable for a splicing display device, the display substrate avoids complex processes such as side wiring and binding area setting on the back side of the display substrate, the manufacturing cost of the display device is reduced, and the customer requirement sensitive to cost can be met.)

1. A display substrate is provided with a first edge, a binding area and a fan-out area, the display substrate comprises a substrate and a plurality of pad groups which are arranged on one side of the substrate in an array mode, the orthographic projection of the binding area on the substrate is positioned between the first edge and the orthographic projection of a first row of pad groups on the substrate, the binding area is provided with a plurality of binding pads, the binding pads are positioned on one side of the substrate, which faces the pad groups, at least part of the orthographic projection of the fan-out area on the substrate is positioned between the orthographic projection of the first row of pad groups and a third row of pad groups on the substrate, the fan-out area is provided with a plurality of signal leads, the signal leads are positioned on one side of the substrate, which faces the pad groups, the first row of pad groups are one row of pad groups close to the first edge, the third row of pad groups is located on one side of the first row of pad groups away from the first edge.

2. The display substrate of claim 1, wherein an orthographic projection of the fan-out area on the substrate is located between the orthographic projection of the third row of pad groups and the orthographic projection of the bonding area on the substrate.

3. The display substrate according to claim 2, wherein the number of the fan-out regions is one or at least two, and in the case where the number of the fan-out regions is at least two, at least two of the fan-out regions are arranged in the first direction.

4. The display substrate according to any one of claims 1 to 3, further comprising a plurality of first power lines extending along a first direction, wherein the plurality of first power lines correspond to a plurality of rows of pad groups one to one, the first power lines corresponding to the first row of pad groups are located between the plurality of bond pads and the first row of pad groups, and the first direction is a direction in which one row of pad groups is located.

5. The display substrate of claim 4, wherein a first power line corresponding to a second row of pad groups is located between the second row of pad groups and the third row of pad groups, and a distance between the first power line corresponding to the second row of pad groups and the third row of pad groups is smaller than a distance between the first power line corresponding to the second row of pad groups and the second row of pad groups.

6. The display substrate according to claim 5, wherein the display substrate further comprises a plurality of signal line groups extending along a second direction, the plurality of signal line groups correspond to a plurality of rows of pad groups one to one, the signal line groups and the pad groups are located on different layers, the corresponding pad groups are connected to the signal line groups through via holes, an orthogonal projection of a first power line corresponding to a first row of pad groups on the substrate is not overlapped with an orthogonal projection of the via holes on the substrate, an orthogonal projection of a first power line corresponding to a second row of pad groups on the substrate is not overlapped with an orthogonal projection of the via holes on the substrate, and the second direction is a direction in which the one row of pad groups is located.

7. The display substrate of claim 6, wherein the via corresponding to the first row of pad group and the via corresponding to the second row of pad group are both located between the first power line corresponding to the first row of pad group and the first power line corresponding to the second row of pad group.

8. The display substrate according to claim 5, wherein the first power line corresponding to the third row of pad groups is located on a side of the third row of pad groups facing away from the second row of pad groups, a distance between the first power line corresponding to the third row of pad groups and the third row of pad groups ranges from 0.5mm to 1mm, and a distance between the first power line corresponding to the second row of pad groups and the third row of pad groups ranges from 0.5mm to 1 mm.

9. The display substrate of any one of claims 1 to 3, wherein each of the bonding pads is not parallel to a second direction, and the second direction is a direction in which a column of the pad group is located.

10. The display substrate of claim 9, wherein the bond pads are parallel to each other, and an angle between the bond pads and the second direction is in a range of 30 ° to 45 °.

11. A display panel comprising the display substrate of any one of claims 1 to 10, wherein the pad group comprises a first pad group on which a light emitting diode chip is bonded.

12. A display device characterized by comprising the display panel according to claim 11.

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a display panel, and a display device.

Background

Small-pitch Light Emitting Diode (LED) display devices are becoming increasingly popular in the market, especially with Mini LED displays being the dominant. Due to LED size limitations, transparent Mini LED displays are commonly used for remote viewing scenes such as advertising or cabinet displays. The screen size of the Mini LED display device is usually more than 100 inches, the pitch (pitch) of the LEDs is usually 0.6mm to 10mm, wherein the LED display with the pitch <1.25mm is called ultra-small pitch LED display, the LED display with the pitch between 1.25mm and 3mm is called small pitch display, and the display with the pitch >3mm is called normal LED display.

In a large-size transparent display application scene, a large-size display device is generally formed by infinitely splicing small-size display devices, and the splicing seam is required to be smaller than the distance between LEDs so as to realize uniform display of a full picture. The splicing display device in the prior art has the disadvantages of complex infinite splicing realization process mode and high cost, and is difficult to meet the requirements of certain low-cost customers.

Disclosure of Invention

Embodiments of the present disclosure provide a display substrate, a display panel and a display device to solve or alleviate one or more technical problems in the prior art.

As a first aspect of embodiments of the present disclosure, embodiments of the present disclosure provide a display substrate having a first edge, the display substrate comprises a substrate base plate and a plurality of pad groups which are located on one side of the substrate base plate and are arranged in an array mode, the orthographic projection of the binding region on the substrate base plate is located between a first edge and the orthographic projection of a first row of pad groups on the substrate base plate, the binding region is provided with a plurality of binding pads, the binding pads are located on one side, facing the pad groups, of the substrate base plate, at least part of the orthographic projection of the fan-out region on the substrate base plate is located between the orthographic projection of the first row of pad groups and the orthographic projection of a third row of pad groups on the substrate base plate, the fan-out region is provided with a plurality of signal leads, the signal leads are located on one side, facing the pad groups, of the substrate base plate, the first row of pad groups are close to the first edge, and the third row of pad groups are located on one side, far away from the first edge, of the first row of pad groups.

In some possible implementations, the orthographic projection of the fan-out area on the substrate base plate is located between the orthographic projection of the third row of pad groups and the orthographic projection of the bonding area on the substrate base plate.

In some possible implementations, the number of the fan-out regions is one or at least two, and in the case where the number of the fan-out regions is at least two, the at least two fan-out regions are arranged in the first direction.

In some possible implementation manners, the display substrate further includes a plurality of first power lines extending along the first direction, the plurality of first power lines correspond to the plurality of rows of pad groups one to one, the first power line corresponding to the first row of pad group is located between the plurality of bonding pads and the first row of pad group, and the first direction is a direction in which the one row of pad group is located.

In some possible implementation manners, the first power line corresponding to the second row of pad groups is located between the second row of pad groups and the third row of pad groups, and a distance between the first power line corresponding to the second row of pad groups and the third row of pad groups is smaller than a distance between the first power line corresponding to the second row of pad groups and the second row of pad groups.

In some possible implementation manners, the display substrate further includes a plurality of signal line groups extending along the second direction, the plurality of signal line groups correspond to the plurality of rows of pad groups one to one, the signal line groups and the pad groups are located on different layers, the corresponding pad groups are connected to the signal line groups through via holes, an orthogonal projection of the first power line corresponding to the first row of pad groups on the substrate is not overlapped with an orthogonal projection of the via holes on the substrate, an orthogonal projection of the first power line corresponding to the second row of pad groups on the substrate is not overlapped with an orthogonal projection of the via holes on the substrate, and the second direction is a direction in which the one row of pad groups is located.

In some possible implementation manners, the via hole corresponding to the first row of pad group and the via hole corresponding to the second row of pad group are both located between the first power line corresponding to the first row of pad group and the first power line corresponding to the second row of pad group.

In some possible implementation manners, the first power line corresponding to the third row of pad group is located on a side of the third row of pad group away from the second row of pad group, a range of a distance between the first power line corresponding to the third row of pad group and the third row of pad group is 0.5mm to 1mm, and a range of a distance between the first power line corresponding to the second row of pad group and the third row of pad group is 0.5mm to 1 mm.

In some possible implementations, each bond pad is not parallel to a second direction, and the second direction is a direction in which a column of the pad groups are located.

In some possible implementations, the bond pads are parallel to each other, and an angle between the bond pads and the second direction ranges from 30 ° to 45 °.

As a second aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a display panel, including the display substrate in any embodiment of the present disclosure, the pad group includes a first pad group, and a light emitting diode chip is welded on the first pad group.

As a third aspect of the embodiments of the present disclosure, embodiments of the present disclosure provide a display device including the display panel in the embodiments of the present disclosure.

The technical scheme of this disclosure, through setting up the at least part of fan-out zone between first row pad group and third row pad group, can set up the display side at display substrate with the binding area, not only can reduce frame district width, can not lead to when realizing the tiled display device to be located the interval between the pixel of piece both sides too big, and in addition, signal lead no longer walks the line through the display substrate side, thereby can reduce the piece width, be favorable to realizing the even demonstration of full picture, promote the picture quality. In addition, the display substrate in the embodiment of the disclosure avoids complex processes such as side routing and setting of the binding region on the back side of the display substrate, reduces the manufacturing cost of the display substrate, and can meet the customer requirements sensitive to cost.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.

FIG. 1a is a schematic diagram of a structure of an LED display panel in the related art;

FIG. 1b is a schematic diagram of another LED display panel in the related art;

FIG. 1c is a schematic diagram of another LED display panel in the related art;

FIG. 2 is a schematic view of a partial structure of a display substrate;

FIG. 3 is a schematic top view of a display substrate according to an embodiment of the present disclosure;

fig. 4 is a schematic cross-sectional structure diagram of a display substrate according to an embodiment of the disclosure.

Description of reference numerals:

10. an LED; 21. a PCB board; 22. a glass substrate; 30. a driver IC; 41. a signal lead; 42/72, a binding region; 43. a PI substrate; 51. a pad group; 511. a first pad group; 512. a second pad group; 61. a signal line group; 71. a first edge; 721. bonding the welding pad; 73. a fan-out region; 74. a substrate base plate; 81. a marking layer; 82. a buffer layer; 83. a first metal layer; 831. a first MTD layer; 832. a first copper metal layer; 833. a second copper metal layer; 84. a first insulating layer; 841. a first passivation layer; 842. a first planar layer; 843. a second passivation layer; 85. a second metal layer; 86. a second insulating layer; 87. a light-shielding layer; 88. a second planar layer; 911. a first via hole; 912. a second via hole; 913. a third via hole; 914. and a fourth via.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art can appreciate, the described embodiments can be modified in various different ways, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

FIG. 1a is a schematic diagram of a structure of an LED display panel in the related art; FIG. 1b is a schematic diagram of another LED display panel in the related art; fig. 1c is a schematic structural diagram of another LED display panel in the related art. In the splicing of the LED display panels, different modes of infinite splicing are realized aiming at the LED display panels with different substrates. For example, for an LED display panel with a flexible substrate such as a PCB, signal routing and Bonding (Bonding) areas can be disposed on the back of the substrate by using a multilayer board press-fit drilling technology, and circuit component integration is implemented on the back of the substrate, as shown in fig. 1a, the LED10 is located on the upper side of the PCB 21, and the driver IC 30 is located on the lower side of the PCB 21. For the LED display panel with a glass substrate, the bonding area may be transferred to the back side of the substrate for component integration through side pad printing traces, as shown in fig. 1b, the LED10 and the driving IC 30 are located on the upper side of the glass substrate 22, the signal leads 41 extend to the lower side of the glass substrate 22 through the side pad printing traces, and the bonding area 42 is formed on the lower side of the glass substrate 22. For a display panel using a glass substrate and a flexible substrate such as Polyimide (PI), a part of PI is peeled off, and the signal lead 41 and the bonding area 42 are bent to the back surface of the glass substrate 22 along with the PI substrate 43 to realize component integration, as shown in fig. 1 c. When the display panel shown in fig. 1a, 1b and 1c is used to realize tiled display, the display panel shown in fig. 1a, 1b and 1c has complex preparation process, so that the infinite tiled display has complex process and high cost, and is difficult to meet the requirements of some low-cost customers. In the display panel shown in fig. 1b and 1c, since the signal leads 41 are routed from the side, when the tiled display device is implemented, in order to avoid the signal leads 41 from being broken by friction, the width of the seams needs to be increased, and the picture quality of the tiled display device is reduced.

Fig. 2 is a schematic partial structure diagram of a display substrate. The driving circuit of the display substrate is shown in fig. 2, and one pad group 51 and one signal line group 61 are shown in fig. 2. The pad group 51 includes a first pad group 511 and a second pad group 512. The first pad group 511 is used for bonding the light emitting diode chip, and the first pad group 511 may bond three light emitting diode chips. The second pad group 512 is used for bonding a driving IC, such as a constant current source IC, to realize control of the LED pixel. The signal line group 61 includes a first power line branch VCC, a second power line GND, a Data line Data, a first driving signal line VR, and a second driving signal line VGB. The first pad group 511 may include three pairs of LED pads, one LED chip being soldered to each pair of LED pads. As shown in fig. 2, the P-pole of the first pair of LED pads is connected to the first driving signal line VR, for example, the P-pole of the first pair of LED pads is connected to the first driving signal line VR through a via; the P poles of the second pair of LED pads and the third pair of LED pads are both connected to the second driving signal line VGB, for example, the P poles of the second pair of LED pads and the third pair of LED pads are connected to the second driving signal line VGB through vias. Thus, the first driving signal line VR drives the LED chip connected to the first pair of LED pads, and the second driving signal line VGB simultaneously drives the LED chip connected to the second pair of LED pads and the LED chip connected to the third pair of LED pads.

The second pad group 512 includes a Data pad Data, a first power supply pad PWR, a second power supply pad GND, a first output pad OUT _ R, a second output pad OUT _ G, and a second output pad OUT _ B. The first output pad OUT _ R, the second output pad OUT _ G, and the second output pad OUT _ B are sequentially connected to N-poles of the first pair of LED pads, the second pair of LED pads, and the third pair of LED pads, respectively, so that the driving IC connected to the second pad group 512 by welding serves as a control switch for the three LEDs. The Data pad Data is connected with the Data line Data through a via hole, and the second power supply pad GND is connected with the second power supply line GND through a via hole. The display substrate may further include a first power line VCC corresponding to the pad group 51, the first power supply pad PWR is connected to the first power line VCC, and the first power line VCC provides a voltage signal to the driving IC.

Illustratively, the first power line VCC corresponds to a row of the pad group 51 to implement a row scan driving. The second power supply pad GND is a reference voltage input port, and the Data pad Data is an address signal input port.

Fig. 3 is a schematic top view structure diagram of a display substrate according to an embodiment of the disclosure, fig. 4 is a schematic cross-sectional structure diagram of the display substrate according to an embodiment of the disclosure, fig. 4 may be a schematic cross-sectional structure diagram B-B in fig. 2, and fig. 4 illustrates an upper-lower position relationship among film layers, but does not limit an actual projection position relationship of the film layers. As shown in fig. 3 and 4, the display substrate has a first edge 71, a bonding region 72, and a fan-out region (Fanout) 73. The display substrate includes a substrate 74 and a plurality of pad sets 51 located at one side of the substrate 74, and the plurality of pad sets 51 are arranged in an array. The orthographic projection of the bonding region 72 on the substrate base plate 74 is located between the first edge 71 and the orthographic projection of the first row of pad groups 51a on the substrate base plate 74, and as can be seen from fig. 3, the bonding region 72 is located between the first edge 71 and the first row of pad groups 51 a. As shown in fig. 3, the bonding region 72 is provided with a plurality of bonding pads 721, and the plurality of bonding pads 721 are located on the side of the substrate base 74 facing the pad group 51.

As shown in fig. 3, at least a part of the forward projection of the fan-out area 73 on the substrate base 74 is located between the forward projections of the first row pad group 51a and the third row pad group 51c on the substrate base 74, and as can be seen from fig. 3, at least a part of the fan-out area 73 is located between the first row pad group 51a and the third row pad group 51 c. The fan-out area 73 is provided with a plurality of signal leads 731, the plurality of signal leads 731 are located on one side of the substrate base plate 74 facing the pad group 51, and the plurality of signal leads 731 are connected with the plurality of bonding pads 721 in a one-to-one correspondence manner. The first row pad group 51a is a row of pad groups close to the first edge 71, and the third row pad group 51c is located on a side of the first row pad group 51a away from the first edge 71, that is, rows of each row of pad groups sequentially increase from the first edge 71 toward the inner side of the display substrate, and in fig. 3, the rows are the first row pad group, the second row pad group, the third row pad group, and … sequentially from bottom to top.

It should be noted that, as shown in fig. 2, the pad group 51 may include a first pad group 511, and the first pad group 511 is used for soldering an LED chip to implement pixel display, so that the first row pad group 51a corresponds to a first row of pixels, and the third row pad group 51c corresponds to a third row of pixels.

In the correlation technique, if set up fan-out zone and binding area simultaneously at the demonstration side of display substrate, fan-out zone and binding area all are located the frame district, can increase display substrate's frame district width to when being applicable to tiled display device, lead to being located the interval between the pixel of piece both sides too big, can't realize the even demonstration of full picture. In the display devices shown in fig. 1b and 1c, the bonding region is disposed on the back side of the display substrate (i.e., the side of the display substrate away from the display side), so that although the width of the frame region can be reduced, the signal leads 41 are routed through the side of the display substrate, which results in a large seam width and affects the picture quality.

The display substrate in the embodiment of the disclosure, at least part of the fan-out area 73 is arranged between the first row of the pad group 51a and the third row of the pad group 51c, that is, at least part of the fan-out area 73 is arranged between the first row of the pixels and the third row of the pixels, so that the binding area 72 can be arranged on the display side of the display substrate, not only can the width of the frame area be reduced, the interval between the pixels on two sides of the joint seam is not too large when the display substrate is suitable for a splicing display device, but also the signal lead 731 is not routed through the side face of the display substrate any more, so that the width of the joint seam can be reduced, the realization of uniform display of a full picture is facilitated, and the picture quality is improved. In addition, the display substrate in the embodiment of the disclosure avoids complex processes such as side routing and setting of the binding region on the back side of the display substrate, reduces the manufacturing cost of the display substrate, and can meet the customer requirements sensitive to cost.

In the display substrate in the embodiment of the disclosure, at least part of the fan-out area 73 is disposed between the first row of pad groups 51a and the third row of pad groups 51c, so that the space of the fan-out area 73 is maximized, a short circuit caused by too small distance between the signal leads 731 of the fan-out area 73 can be avoided, the yield of products is improved, and the competitiveness of products is improved.

In one embodiment, the forward projection of the fan-out region 73 on the substrate base 74 is located between the third row of pad groups 51c and the forward projection of the bonding regions 72 on the substrate base 74, and referring to fig. 3, the fan-out region 73 is located between the third row of pad groups 51c and the bonding regions 72.

It is to be understood that, referring to fig. 2 and 3, each signal lead 731 of the fan-out area 73 is correspondingly connected to each signal line in the signal line group 61, and a plurality of pads in the pad group 51 are correspondingly connected to a plurality of signal lines in the signal line group 61; the signal lead 731 is located in a different layer from the pad group 51. Illustratively, as shown in fig. 4, the signal lead 731 is located on one side of the substrate board 74, and the signal lead 731 is located on the first metal layer 83. The side of the signal lead 731 facing away from the substrate 74 is provided with a first insulating layer 84, and the pad group 51 is located on the side of the first insulating layer 84 facing away from the signal lead 731. If the fan-out area 73 is overlapped with the area where the third row of pad group 51c is located or the upper edge of the fan-out area 73 is located on the upper side of the third row of pad group 51c, the metal routing of the layer where the pad group 51 is located is complicated, and the arrangement of the metal routing is not favorable. The orthographic projection of the fan-out area 73 on the substrate base plate 74 is arranged between the orthographic projection of the third row of the pad group 51c and the orthographic projection of the binding area 72 on the substrate base plate 74, so that the metal routing of the layer where the pad group 51 is located can be conveniently wired, the wiring difficulty is reduced, and the product performance is improved.

It should be noted that, in other embodiments, the area where the fan-out region is located is not limited to the area between the third row of pad group 51c and the bonding region 72, and the area where the fan-out region is located may also have an overlapping portion with the area where the third row of pad group 51c is located, and an arrangement manner of the metal routing lines of the layer where the pad group 51 is located needs to be additionally set.

Note that the fan-out area 73 shown in fig. 3 is a half area of the entire fan-out area. Illustratively, a direction in which a row of pad groups is located is defined as a first direction X, and a direction in which a column of pad groups is located is defined as a second direction Y. The signal lead 731 disposed in the fan-out region 73 may include a first portion extending in the first direction X and a second portion extending in the second direction Y. Illustratively, the size w ≧ (m/2) × d of the fan-out area 73 in the second direction Y, where m is the number of the signal leads 731 in the fan-out area 73 and d is the sum of the line width and the line spacing of the first portion of the signal leads 731 in the fan-out area 73.

In one embodiment, the fan-out region 73 has a dimension w ═ m/2 × d in the second direction Y. For example, in the case that the spacing between the third row pad group 51c and the bonding region 72 is greater than or equal to (m/2) × d, the display substrate may include one fan-out region 73. Under the condition that the distance between the third row of pad group 51c and the bonding region 72 is smaller than (m/2) × d, the number of the fan-out regions 73 can be set to be at least two, and at least two fan-out regions 73 can be arranged along the first direction X, so that the number of the signal leads 731 of each fan-out region 73 can be reduced, each fan-out region 73 is ensured to be positioned between the third row of pad group 51c and the bonding region 72, and the routing of the metal routing of the layer where the pad group 51 is positioned is facilitated.

The signal lead 731 shown in fig. 3 includes a first portion extending in the first direction X and a second portion extending in the second direction Y. It should be noted that, in other embodiments, the signal lead 731 is not limited to the shape shown in fig. 3, and the signal lead 731 may be any broken line or arc shape as long as the signal lead can connect each signal line in the signal line group 61 with the corresponding bond pad 721.

Note that the bonding areas 72 correspond to the fan-out areas 73 one by one. The bonding regions 72 are used to bond Chips On Film (COF) or flexible circuit boards (FPC), and when the number of bonding regions 72 increases, the number of Chips On Film (COF) or flexible circuit boards (FPC) increases correspondingly.

In one embodiment, as shown in fig. 3, the display substrate may further include a plurality of first power lines VCC extending along the first direction X, and the plurality of first power lines VCC are in one-to-one correspondence with the plurality of rows of pad groups. For example, the first power line VCC corresponding to the first row of pad group 51a is the first power line VCC1, the first power line VCC corresponding to the second row of pad group 51b is the first power line VCC2, and the first power line VCC corresponding to the third row of pad group 51c is the first power line VCC 3. The first power line VCC1 is located between the plurality of bond pads 721 and the first row pad group 51 a.

It should be noted that the first power line VCC may be located at the same layer as the pad group 51, and the first power line VCC1 is disposed between the plurality of bonding pads 721 and the first row of pad group 51a, so that the connection and routing between the first row of pad group 51a and the signal lead 731 in the fan-out region 73 may be facilitated, and the routing layout is avoided. Also, the bonding pads 721 need to be bond-connected to the COF or the FPC, the first power line VCC1 is disposed between the plurality of bonding pads 721 and the first row pad group 51a, and the plurality of bonding pads 721 are disposed between the first power line VCC1 and the first edge 71, so that the plurality of bonding pads 721 avoid the first power line VCC1, facilitating the bond-connection of the bonding pads 721 to the COF or the FPC.

Illustratively, the distance between the first power supply line VCC1 and the first row pad group 51a may range from 0.5mm to 1mm (inclusive). For example, the distance between the first power supply line VCC1 and the first row pad group 51a may be 0.6 mm.

In one embodiment, as shown in fig. 3, the first power line VCC2 is located between the second row pad set 51b and the third row pad set 51c, and a distance between the first power line VCC2 and the third row pad set 51c is smaller than a distance between the first power line VCC2 and the second row pad set 51 b.

Illustratively, the orthographic projection of the fan-out region 73 on the substrate baseplate 74 is located between the first power supply line VCC2 and the orthographic projection of the bonding region 72 on the substrate baseplate 74, and referring to fig. 3, the fan-out region 73 is located between the first power supply line VCC2 and the bonding region 72. In this way, when the first row pad group 51a and the second row pad group 51b are connected to the signal lead 731 for wiring, the influence of the first power supply line VCC2 on the wiring can be avoided, and the wiring design can be further simplified.

In one embodiment, as shown in fig. 3, the first power line VCC3 is located at a side of the third row of pad groups 51c facing away from the second row of pad groups 51b, and in fig. 3, the first power line VCC3 is located at an upper side of the third row of pad groups 51 c.

Illustratively, the distance between the first power supply line VCC2 and the third row pad group 51c may range from 0.5mm to 1mm (inclusive). For example, the distance between the first power supply line VCC2 and the third row pad group 51c may be 0.6 mm. The distance between the first power supply line VCC3 and the third row pad group 51c may range from 0.5mm to 1mm (inclusive). For example, the distance between the first power supply line VCC3 and the third row pad group 51c may be 0.6 mm.

For example, the first power line corresponding to the fourth row of pad group may be arranged with reference to the arrangement manner of the first power line corresponding to the third row of pad group, for example, the first power line corresponding to the nth row of pad group is located on a side of the nth row of pad group away from the n-1 row of pad group, and a distance between the first power line corresponding to the nth row of pad group and the nth row of pad group may range from 0.5mm to 1mm (inclusive), where n is a positive integer greater than 3.

In one embodiment, as shown in fig. 3, the display substrate may further include a plurality of signal line groups 61 extending along the second direction Y, and the plurality of signal line groups 61 correspond to the plurality of columns of pad groups 51 one to one. The signal line group 61 is located at a different layer from the pad group 51, and the signal line group 61 is located at the same layer as the signal lead 731 of the fan-out region 73 and the bonding pad 721 of the bonding region 72. The corresponding pad group 51 is connected to the signal line group 61 through a via.

For example, an enlarged schematic view of a portion a in fig. 3 may be as shown in fig. 2. The pad group 51 includes a first pad group 511 and a second pad group 512. The first pad group 511 is used for bonding the light emitting diode chip, and the first pad group 511 may bond three light emitting diode chips. The second pad group 512 is used for bonding a driving IC, such as a constant current source IC, to realize control of the LED pixel. The signal line group 61 includes a first power line branch VCC, a second power line GND, a Data line Data, a first driving signal line VR, and a second driving signal line VGB. The first pad group 511 may include three pairs of LED pads, one LED chip being soldered to each pair of LED pads. As shown in fig. 2, the P-pole of the first pair of LED pads is connected to the first driving signal line VR, for example, the P-pole of the first pair of LED pads is connected to the first driving signal line VR through the first via 911; the P-poles of the second pair of LED pads and the third pair of LED pads are both connected to the second driving signal line VGB, for example, the P-poles of the second pair of LED pads and the third pair of LED pads are connected to the second driving signal line VGB through the second via 912. Thus, the first driving signal line VR drives the LED chip connected to the first pair of LED pads, and the second driving signal line VGB simultaneously drives the LED chip connected to the second pair of LED pads and the LED chip connected to the third pair of LED pads.

As shown in fig. 2, the second pad group 512 includes a Data pad Data, a first power supply pad PWR, a second power supply pad GND, a first output pad OUT _ R, a second output pad OUT _ G, and a second output pad OUT _ B. The first output pad OUT _ R, the second output pad OUT _ G, and the second output pad OUT _ B are sequentially connected to N-poles of the first pair of LED pads, the second pair of LED pads, and the third pair of LED pads, respectively, so that the driving IC connected to the second pad group 512 by welding serves as a control switch for the three LEDs. The Data pad Data is connected to the Data line Data through a third via 913, and the second power pad GND is connected to the second power line GND through a fourth via 914. The first power supply pad PWR is connected to a corresponding first power supply line VCC, which provides a voltage signal to the driving IC.

In one embodiment, the orthographic projection of the first power line VCC1 corresponding to the first row land set 51a on the substrate 74 does not overlap with the orthographic projection of the via hole on the substrate 74, and the orthographic projection of the first power line VCC2 corresponding to the second row land set 51b on the substrate 74 does not overlap with the orthographic projection of the via hole on the substrate 74. Therefore, the wiring of the film layer where the pad group is located is further facilitated.

Illustratively, the vias corresponding to the first row pad group 51a (i.e., the first via 911, the second via 912, the third via 913, and the fourth via 914 corresponding to the first row pad group 51 a) and the vias corresponding to the second row pad group 51b (i.e., the first via 911, the second via 912, the third via 913, and the fourth via 914 corresponding to the second row pad group 51 b) are located between the first power line VCC1 corresponding to the first row pad group 51a and the first power line VCC2 corresponding to the second row pad group 51 b. The via hole corresponding to the first row of pad group 51a is a via hole provided for connecting the first row of pad group 51a to the corresponding signal line group, and the via hole corresponding to the second row of pad group 51b is a via hole provided for connecting the second row of pad group 51b to the corresponding signal line group.

In one embodiment, as shown in fig. 3, in the bonding region 72, each bonding pad 721 is not parallel to the second direction Y. In this way, the width dimension of the bonding region 72 can be reduced while ensuring the length of the bonding pad 721, thereby reducing the width of the frame region (e.g., a lower frame). It is understood that the width of the binding region is the dimension of the binding region in the second direction Y.

In one embodiment, the bond pads 721 are parallel to each other, as shown in fig. 3. The angle β between each of the bonding pads 721 and the second direction Y may range from 30 ° to 45 ° (inclusive). For example, an angle between each of the bonding pads 721 and the second direction Y may be any one of 30 ° to 45 °, for example, 30 ° or 45 °. In the case where the angle β is 30 °, the length of the bonding pad 721 is L, and the width dimension occupied by the bonding pad 721 is L/2, which can save the width space of L/2.

Note that, in one half of the fan-out area shown in fig. 3, the bonding pad 721 is inclined toward the lower left. In the other half area of the fan-out area, the tie pad 721 may be inclined toward the lower left, or the tie pad may be inclined toward the lower right.

The embodiment of the present disclosure further provides a display panel, which includes the display substrate in any embodiment of the present disclosure, the pad group 51 may include a first pad group 511, and a light emitting diode chip is welded on the first pad group 511. For example, the first pad group 511 may include three pairs of LED pads to which three LED chips are respectively soldered. The display panel may be a glass-based transparent display panel, the viewing distance may be greater than or equal to 5m, and the pixel pitch is greater than or equal to 2.5 mm.

The Light Emitting Diode (LED) chip may include a sub-millimeter Light Emitting Diode (Mini LED) chip and a Micro Light Emitting Diode (Micro LED) chip.

The embodiment of the disclosure also provides a display device, which comprises the display panel in the embodiment of the disclosure. Illustratively, the display device may be a tiled display device comprising a plurality of sequentially tiled display panels. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

The technical solution of the embodiment of the present disclosure is further described below by the preparation process of the display substrate in an embodiment of the present disclosure. It is to be understood that "patterning" as used herein includes processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. when the material to be patterned is an inorganic material or a metal, and processes of mask exposure, development, etc. when the material to be patterned is an organic material, and evaporation, deposition, coating, etc. as used herein are well-known preparation processes in the related art.

Preparation of marking layer: a marker film is deposited on one side of the base substrate 74, and the marker film is patterned to form a marker layer 81. The material of the marking layer 81 may be a metal, such as at least one of molybdenum and titanium.

Preparing a buffer layer: and depositing a buffer film on the side of the marking layer 81, which is far away from the substrate, to form a buffer layer 82, wherein the thickness of the buffer layer 82 can be 1000-4000 angstroms.

Preparation of the first metal layer 83, the first metal layer including each signal line in the signal line group, each signal lead in the fan-out region, and each bonding pad in the bonding region, for example, the first metal layer 83 may include a first MTD layer 831, a first copper metal layer 832, and a second copper metal layer 833 sequentially stacked, and the preparation process may include:

(1) and sequentially depositing a first MTD film and a first copper metal film on the side, away from the substrate 74, of the buffer layer 82, wherein the film deposition can be performed in a magnetron sputtering manner. The first MTD film may have a thickness of 250 to 350 angstroms, such as 300 angstroms; the first copper metal film can have a thickness of 2500 to 3500 angstroms, such as 3000 angstroms. The material of the first MTD thin film may include at least one of metal molybdenum, metal titanium, or an alloy of both, and the material of the first copper metal may include metal copper. The first metal layer may include a plurality of signal line groups, a plurality of signal leads 731 at the fan-out region, and a plurality of bonding pads 721 at the bonding region. Coating photoresist on one side of the first copper metal film, which is far away from the substrate base plate 74, wherein the thickness of the photoresist can be 9-10 microns, exposing and developing the photoresist by adopting a mask, removing the photoresist at each signal wire position, each signal lead position and each bonding pad position in the signal wire group, reserving the photoresist at the rest positions, and drying the reserved photoresist.

(2) And forming a second copper metal film at the position without the photoresist by adopting an electroplating process, wherein the photoresist position cannot form copper metal due to the adoption of the electroplating process. The thickness of the second copper metal film may be 6 μm to 7 μm. And stripping the photoresist, carrying out integral etching, completely etching the first copper metal film and the first MTD film which are positioned at the positions outside the signal lines, the signal leads and the bonding pads by controlling the etching time, and forming a first metal layer 83 by the residual metal films positioned at the positions of the signal lines, the signal leads and the bonding pads. Since the thickness of the second copper metal film is greater than the sum of the thicknesses of the first copper metal film and the first MTD film, each signal line, each signal lead, and each bond pad includes a first MTD layer 831, a first copper metal layer 832, and a second copper metal layer 833 that are stacked.

The first insulating layer 84 is prepared, and the first insulating layer 84 may include a first passivation layer 841, a first planarization layer 842, and a second passivation layer 843, and the preparation process may include:

(1) a first passivation layer 841 is formed on a side of the first metal layer 83 facing away from the substrate base plate 74, and the thickness of the first passivation layer 841 may be greater than or equal to 3000 angstroms. The first passivation layer 841 may be deposited by magnetron sputtering.

(2) A resin film is coated on a side of the first passivation layer 841 away from the substrate 74 twice to perform planarization respectively, so as to form a first planarization layer 842, wherein the thickness of the first resin film may be 6 μm to 7 μm, and the thickness of the second resin film may be 2 μm to 3 μm. The first planarization layer 842 serves primarily for planarization and for via formation.

(3) A second passivation layer 843 is formed on a side of the first planarization layer 842 facing away from the substrate base 74, and the thickness of the second passivation layer 843 may be greater than or equal to 1500 angstroms. The second passivation layer 843 may be deposited by magnetron sputtering.

The second metal layer 85 is prepared, and the second metal layer 85 may include each pad in the pad group, the first power line VCC, a connection line between the pad group and the signal line group, and a connection line between the pad group and the first power line VCC. The preparation process of the step can comprise the following steps: and depositing a second MTD film, a third copper metal film and a protective metal film in sequence on the side, away from the substrate 74, of the first insulating layer 84 by magnetron sputtering, wherein the thickness of the second MTD film can be 250-350 angstroms (for example, 300 angstroms), the thickness of the third copper metal film can be 8500-9500 angstroms (for example, 9000 angstroms), and the thickness of the protective metal film can be 450-550 angstroms (for example, 500 angstroms). The second MTD film, the third copper metal film, and the protective metal film are patterned to form a second metal layer 85.

Preparation of the second insulating layer 86: a second insulating layer 86 is formed on a side of the second metal layer 85 facing away from the substrate base plate 74, and the thickness of the second insulating layer 86 may be greater than or equal to 1500 angstroms. The second insulating layer 86 may be deposited by magnetron sputtering. The second insulating layer 86 may also be referred to as a third passivation layer PVX 3.

Preparing a shading layer: a photoresist is applied to the side of the second insulating layer 86 facing away from the base substrate 74 to form a light-shielding layer 87. The light shielding layer 87 is made of a low-reflectivity photoresist to cover the metal traces, thereby preventing the metal traces from reflecting light to affect the display effect. Illustratively, the optical density OD of the light-shielding layer 87 is > 5.

Preparation of the second planarization layer 88: a photoresist is applied to the side of the light shielding layer 87 facing away from the base substrate 74, and the photoresist is exposed and developed by using a mask, thereby forming a second planarization layer 88. And drying and dry etching are carried out subsequently, so that each bonding pad and each bonding pad in the bonding pad group are exposed.

It can be understood that during the process of preparing each passivation layer, each planarization layer and the light shielding layer, a corresponding via needs to be formed to achieve the corresponding connection between the second metal layer 85 and the first metal layer 84, and expose each bonding pad and each bonding pad in the bonding pad group. A schematic diagram in which the second power supply pad GND is connected to the second power supply line GND through the fourth via 914 is shown in fig. 4.

As will be understood by those skilled in the art, in the subsequent processes of manufacturing the display panel, dicing, printing of the reflective layer, die bonding processes (including die bonding of the LED chip and die bonding of the driver IC), reflow soldering, full-surface lamination, bonding processes, assembly, and the like are required.

In an exemplary embodiment, the first passivation layer, the second passivation layer, the third passivation layer, and the buffer layer may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. A Buffer layer for improving the water and oxygen resistance of the substrate.

In the description of the present specification, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present disclosure and to simplify the description, but are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being in direct contact, or may comprise the first and second features being in contact, not directly, but via another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Moreover, the present disclosure may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.

While the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.