Vertical cavity surface emitting laser with tunnel junction
阅读说明：本技术 具有隧道结的垂直腔面发射激光器 (Vertical cavity surface emitting laser with tunnel junction ) 是由 杨军 赵国为 M.G.彼得斯 E.R.黑布洛姆 A.V.巴韦 B.克斯勒 于 2021-05-20 设计创作，主要内容包括：VCSEL可以包括n型衬底层和在n型衬底层表面上的n型底镜。VCSEL可以包括在n型底镜上的有源区和在有源区上的p型层。VCSEL可以包括有源区上的氧化层,以提供VCSEL的光学和电学限制。VCSEL可以包括在p型层上的隧道结,以反转n型顶镜的载体类型。氧化层在p型层上或p型层中,隧道结在氧化层上,或者隧道结在p型层上,氧化层在隧道结上。VCSEL可以包括隧道结上的n型顶镜、n型顶镜上的顶部接触层和顶部接触层上的顶部金属。(The VCSEL can include an n-type substrate layer and an n-type bottom mirror on a surface of the n-type substrate layer. The VCSEL can include an active region on the n-type bottom mirror and a p-type layer on the active region. The VCSEL can include an oxide layer on the active region to provide optical and electrical confinement of the VCSEL. The VCSEL can include a tunnel junction on the p-type layer to invert the carrier type of the n-type top mirror. The oxide layer is on or in the p-type layer, the tunnel junction is on the oxide layer, or the tunnel junction is on the p-type layer, the oxide layer is on the tunnel junction. The VCSEL can include an n-type top mirror on the tunnel junction, a top contact layer on the n-type top mirror, and a top metal on the top contact layer.)
1. A vertical-cavity surface-emitting laser (VCSEL), comprising:
an n-type substrate layer having a top surface and a bottom surface;
an n-type metal on a bottom surface of the n-type substrate layer, the n-type metal being a cathode of the VCSEL;
an n-type bottom mirror on a top surface of the n-type substrate layer;
an active region on the n-type bottom mirror;
a p-type layer on the active region;
an oxide layer over the active region, wherein the oxide layer provides optical and electrical confinement of the VCSEL;
a tunnel junction over the p-type layer, wherein the tunnel junction is to invert a carrier type of the n-type top mirror, and wherein:
the oxide layer is on or in the p-type layer, the tunnel junction is on the oxide layer, or
The tunnel junction is on the p-type layer, and the oxide layer is on the tunnel junction;
an n-type top mirror over the tunnel junction;
a top contact layer over the n-type top mirror; and
a top metal on the top contact layer, the top metal being an anode of the VCSEL.
2. The VCSEL of claim 1, wherein the top contact layer is an n-type contact layer and the top metal is another n-type metal, the n-type contact layer on the n-type top mirror and the another n-type metal on the n-type contact layer.
3. The VCSEL of claim 1, wherein the p-type layer is a p-type Distributed Bragg Reflector (DBR).
4. The VCSEL of claim 1, wherein the p-type layer is a p-type spacer layer.
5. The VCSEL of claim 1, wherein the oxide layer is in an n-type top mirror.
6. The VCSEL of claim 1, wherein the p-type layer has less than six layer pairs.
7. The VCSEL of claim 1, wherein a thickness of the p-type layer is less than or equal to 0.5 microns.
8. The VCSEL of claim 1, further comprising another tunnel junction on the n-type top mirror,
wherein the top contact layer is a p-type contact layer, the top metal is a p-type metal, the p-type contact layer is on another tunnel junction, and the p-type metal is on the p-type contact layer.
9. A Vertical Cavity Surface Emitting Laser (VCSEL) array, comprising:
an active region on the n-type bottom mirror;
a p-type layer on the active region;
an oxide layer over the active region to provide optical and electrical confinement for the VCSELs in the VCSEL array; and
a tunnel junction over the p-type layer to invert a carrier type of the n-type top mirror over the tunnel junction, wherein:
the oxide layer is on or in the p-type layer, the tunnel junction is on the oxide layer, or
The tunnel junction is on the p-type layer and the oxide layer is on the tunnel junction.
10. The VCSEL array of claim 9, further comprising an n-type top contact layer on the n-type top mirror and an n-type top metal on the n-type top contact layer.
11. A VCSEL array in accordance with claim 9, wherein the p-type layer is a p-type Distributed Bragg Reflector (DBR).
12. The VCSEL array of claim 9, wherein the p-type layer is a p-type spacer layer.
13. A VCSEL array in accordance with claim 9, wherein the oxide layer is in the n-type top mirror.
14. A VCSEL array in accordance with claim 9, wherein the p-type layer has less than six layer pairs or has a thickness less than or equal to 0.5 microns.
15. The VCSEL array of claim 9, further comprising another tunnel junction, a p-type top contact layer, and a p-type top metal,
wherein another tunnel junction is on the n-type top mirror, a p-type top contact layer is on the another tunnel junction, and a p-type top metal is on the p-type top contact layer.
16. A method, comprising:
forming an n-type bottom mirror on the surface of the n-type substrate layer;
forming an active region on the n-type bottom mirror;
forming a p-type layer on the active region;
forming an oxide layer over the active region;
forming a tunnel junction over the p-type layer, wherein any of:
an oxide layer formed on or in the p-type layer and a tunnel junction formed on the oxide layer, or
A tunnel junction is formed on the p-type layer, and an oxide layer is formed on the tunnel junction; and
an n-type top mirror is formed over the tunnel junction.
17. The method of claim 16, further comprising:
forming an n-type top contact layer on the n-type top mirror, and
an n-type top metal is formed on the n-type top contact layer.
18. The method of claim 16, wherein the p-type layer is a p-type Distributed Bragg Reflector (DBR).
19. The method of claim 16, wherein the p-type layer is a p-type spacer layer.
20. The method of claim 16, further comprising:
another tunnel junction is formed over the n-type top mirror,
forming a p-type top contact layer on the other tunnel junction, and
a p-type top metal is formed on the p-type top contact layer.
Technical Field
The present disclosure relates generally to Vertical Cavity Surface Emitting Lasers (VCSELs), and more particularly to VCSELs that include a tunnel junction that improves VCSEL performance.
Background
A VCSEL is a semiconductor laser, more specifically, a diode laser having a monolithic laser resonator in which light is emitted in a direction perpendicular to the chip surface. Typically, a laser resonator consists of two Distributed Bragg Reflector (DBR) mirrors parallel to the chip surface, between which is an active region (consisting of one or more quantum wells) that generates light. Typically, the upper and lower mirrors of a VCSEL are doped with p-type and n-type materials, respectively, to form diode junctions.
Disclosure of Invention
In some embodiments, a VCSEL includes: an n-type substrate layer having a top surface and a bottom surface; an n-type metal on a bottom surface of the n-type substrate layer, the n-type metal being a cathode of the VCSEL; an n-type bottom mirror on a top surface of the n-type substrate layer; an active region on the n-type bottom mirror; a p-type layer on the active region; an oxide layer over the active region, wherein the oxide layer provides optical and electrical confinement of the VCSEL; a tunnel junction over the p-type layer, wherein the tunnel junction is to invert a carrier type of the n-type top mirror, and wherein either: the oxide layer is on or in the p-type layer and the tunnel junction is on the oxide layer, or the tunnel junction is on the p-type layer and the oxide layer is on the tunnel junction; an n-type top mirror over the tunnel junction; a top contact layer over the n-type top mirror; and a top metal on the top contact layer, the top metal being an anode of the VCSEL.
In some embodiments, a VCSEL array comprises: an active region on the n-type bottom mirror; a p-type layer on the active region; an oxide layer over the active region to provide optical and electrical confinement for the VCSELs in the VCSEL array; and a tunnel junction over the p-type layer to invert a carrier type of the n-type top mirror over the tunnel junction, wherein any of: the oxide layer is on or in the p-type layer and the tunnel junction is on the oxide layer, or the tunnel junction is on the p-type layer and the oxide layer is on the tunnel junction.
In some embodiments, a method comprises: forming an n-type substrate mirror on a surface of the n-type substrate layer; forming an active region on the n-type bottom mirror; forming a p-type layer on the active region; forming an oxide layer over the active region; forming a tunnel junction over the p-type layer, wherein any of: the oxide layer is formed on or in the p-type layer and the tunnel junction is formed on the oxide layer, or the tunnel junction is formed on the p-type layer and the oxide layer is formed on the tunnel junction; and forming an n-type top mirror over the tunnel junction.
Drawings
Fig. 1A and 1B are schematic diagrams showing an example of a conventional VCSEL.
Figure 2 is a schematic diagram illustrating a VCSEL having a tunnel junction as described herein.
Fig. 3A and 3B are diagrams illustrating a first exemplary embodiment of a VCSEL having a tunnel junction as described herein.
Fig. 4A and 4B are diagrams illustrating a second exemplary embodiment of a VCSEL having a tunnel junction as described herein.
Fig. 5A and 5B are schematic diagrams illustrating a third exemplary embodiment of a VCSEL having a tunnel junction as described herein.
Fig. 6A and 6B are diagrams illustrating a fourth exemplary embodiment of a VCSEL having a tunnel junction as described herein.
Fig. 7A and 7B are schematic diagrams illustrating an exemplary implementation of a VCSEL having two tunnel junctions as described herein.
Fig. 8A and 8B are graphs illustrating a comparison of a typical current-voltage curve of a conventional VCSEL and a simulated current-voltage curve of a VCSEL including a tunnel junction.
Fig. 9 is a flow chart of an example process related to fabricating a VCSEL including a tunnel junction as described herein.
Detailed Description
The following detailed description of exemplary embodiments refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements.
For diode lasers, such as VCSELs, electrons and holes (holes) need to be injected into the active region (e.g., quantum well active region) from opposite sides. This is typically achieved by placing a p-type contact and p-type DBR on the top side of the active region and an n-type contact and n-type DBR on the bottom side of the active region. Under positive bias, holes are injected into the active region from the p-type DBR and electrons are injected into the active region from the n-type DBR. Holes and electrons recombine in the active region to emit light. Typically, the p-type DBR is the upper mirror of the VCSEL and the n-type DBR is the lower mirror of the VCSEL; but this arrangement can be reversed depending on the geometry of the VCSEL.
Fig. 1A and 1B are schematic diagrams illustrating an example of a conventional VCSEL 100. Fig. 1A is a schematic diagram showing the respective layers of the VCSEL100, and fig. 1B is a schematic diagram showing an example of a cross-section of the VCSEL100 having the layers shown in fig. 1A. As shown in fig. 1A and 1B, a conventional VCSEL includes an n-type substrate 102 with an n-type metal 104 (serving as a cathode) on the bottom surface and an n-type DBR 106 on the top surface. As further shown, the VCSEL100 includes an active region 108 on the n-type DBR 106 and a p-type DBR 112 on the active region 108. As further shown, a p-type contact 114 is placed on the p-type DBR 112, and a p-type metal 116 (which serves as an anode) is on the p-type contact 114. As further shown, the VCSEL100 includes an oxide layer 110, the oxide layer 110 forming an oxide aperture (for providing optical and electrical confinement of the VCSEL 100). As shown in fig. 1B, an oxide layer 110 is typically located over the active region 108 in the p-type DBR 112. Notably, as shown in fig. 1B, the VCSEL100 further includes a dielectric layer 118 and an isolation implant 120.
The p-type DBR (e.g., p-type DBR 112) and the p-type contact (e.g., p-type contact 114) have holes as the majority carrier, while the n-type DBR (e.g., n-type DBR 106) and the n-type contact (e.g., n-type metal 104) have electrons as the carrier. In conventional III-V semiconductors, the mobility of holes is lower than that of electrons. For example, in gallium arsenide (GaAs) at room temperature, the electron mobility is 8500 square centimeters per volt-second (cm)2V.s) and a hole mobility of about 400cm2V · s, therefore, the resistance of the n-type DBR is significantly lower than the p-type DBR.
One parameter for evaluating VCSEL performance is the voltage drop across the VCSEL. For a conventional VCSEL, such as VCSEL100, the resistance of the p-type DBR is higher than the resistance of the n-type DBR, which means that the voltage drop across the p-type DBR is significantly higher (e.g., about twice as high) than across the n-type DBR. Reducing the voltage drop across the VCSEL will improve the performance of the VCSEL.
Some embodiments described herein provide a VCSEL including a tunnel junction. As described in further detail below, the tunnel junction allows for a reduction in the amount of p-type material in the VCSEL (e.g., as compared to the VCSEL 100). In other words, the tunnel junction allows at least some p-type (e.g., a portion of the top mirror) material to be replaced with n-type material within the VCSEL structure. As a result, the voltage drop across the VCSEL is reduced, thereby improving the performance of the VCSEL. Furthermore, replacing the p-type material with n-type material in the top mirror of the VCSEL reduces the light absorption losses in the top mirror and also allows lower doping in the top mirror (e.g., due to the higher conductivity of n-type material compared to p-type material). Other details are as follows.
Figure 2 is a schematic diagram illustrating an example of a VCSEL200 with a tunnel junction as described herein. As shown in fig. 2, the VCSEL200 can include an n-type substrate layer 202, an n-type metal 204, an n-type bottom mirror 206, an active region 208, a p-type layer 210, an oxide layer 212, a tunnel junction 214, an n-type top mirror 216, a top contact layer 218, and a top metal 220. It is noted that the order and arrangement of the p-type layer 210, the oxide layer 212, and the tunnel junction 214 within the VCSEL200 shown in figure 2 is for illustrative purposes, and the order may be different than that shown in figure 2 (depending on the design of the VCSEL 200). Various exemplary embodiments of the VCSEL200 are described below.
In some embodiments, the VCSEL200 can be fabricated using a series of procedures. For example, in other examples, one or more growth processes, one or more deposition processes, one or more etching processes, one or more oxidation processes, one or more implantation processes, and/or one or more metallization processes may be used to produce one or more layers of the VCSEL 200.
The n-type substrate layer 202 includes a substrate comprising an n-type material. In some embodiments, other layers of the VCSEL200 are grown on the n-type substrate layer 202. In some embodiments, the n-type substrate layer 202 may be formed of a semiconductor material, such as gallium arsenide (GaAs), indium phosphide (InP), or another type of semiconductor material.
The n-type metal 204 comprises an n-type metal layer on the backside of the VCSEL 200. For example, the n-type metal 204 may be a layer in electrical contact with the n-type substrate layer 202 (e.g., the backside of the n-type substrate layer 202). As a particular example, the n-type metal 204 may include an annealed metallization layer, such as a gold-germanium-nickel (AuGeNi) layer, a palladium-germanium-gold (PdGeAu) layer, and so forth. In some embodiments, as shown in fig. 2, an n-type metal 204 may be used as the cathode of the VCSEL 200.
The n-type bottom mirror 206 is the bottom reflector of the optical resonator of the VCSEL200 formed of n-type material. For example, the n-type bottom mirror 206 may include a DBR, a dielectric mirror, or other type of mirror structure. In some embodiments, the n-type bottom mirror 206 can have a thickness in a range from about 3.5 micrometers (μm) to about 9 μm (e.g., 5 μm). In some embodiments, the n-type bottom mirror 206 comprises a set of layers (e.g., aluminum gallium arsenide (AlGaAs) layers) grown using Metal Organic Chemical Vapor Deposition (MOCVD) techniques, Molecular Beam Epitaxy (MBE) techniques, or other techniques.
The active region 208 includes one or more layers in which electrons and holes recombine to emit light and define the emission wavelength range of the VCSEL 200. For example, the active region 208 may include one or more quantum wells. In some embodiments, the active region 208 may include one or more cavity spacers between the n-type top mirror 216 and the n-type bottom mirror 206. The optical thickness of the active region 208 (including the cavity spacer layer) and the optical thicknesses of the n-type top mirror 216 and the n-type bottom mirror 206 define the resonant cavity wavelength of the VCSEL200, which can be designed to achieve lasing over the emission wavelength range of the active region. In some embodiments, the thickness of the active region 208 may be in a range from about 0.06 μm to about 0.5 μm, such as 0.15 μm or 0.30 μm. In some embodiments, active region 208 includes a set of layers grown using MOCVD techniques, MBE techniques, or other techniques.
The p-type layer 210 is a layer comprising p-type material disposed between the tunnel junction 214 and the active region 208. In some embodiments, the p-type layer 210 is a thin p-type DBR (p-DBR). In this case, the p-type DBR is part of the top reflector of the optical resonator of the VCSEL 200. For example, the p-type layer 210 may be a p-DBR having less than six layer pairs (e.g., one to four layer pairs). In some embodiments, such thin p-DBRs have a thickness of less than or equal to 0.5 μm. Fig. 3A and 3B, 4A and 4B, 5A and 5B, and 7A and 7B illustrate an exemplary embodiment of the VCSEL200 in which the p-type layer 210 is a thin p-DBR.
In some embodiments, the p-type layer 210 is a p-type spacer layer. The p-type spacer layer is a layer that supports hole injection in the active region 208, but does not act as part of the top reflector of the optical resonator of the VCSEL 200. In some embodiments, the p-type spacer layer is one layer of a single material (e.g., rather than multiple layers of alternating materials). In some embodiments, the p-type spacer layer may comprise, for example, GaAs, AlGaAs (e.g., 85% Al% AlGaAs), and the like. In some embodiments, the p-type spacer layer may have a thickness in a range from about 0.1 μm to about 1.0 μm. 6A and 6B illustrate exemplary embodiments of the VCSEL200 where the p-type layer 210 is a p-type spacer layer.
The oxide layer 212 includes an oxide layer that forms an oxide aperture for providing optical and electrical confinement of the VCSEL 200. In some embodiments, the oxide layer 212 is formed as a result of oxidation of one or more epitaxial layers of the VCSEL. For example, the oxide layer 212 may be aluminum oxide (Al) formed as a result of oxidation of an epitaxial layer (e.g., an AlGaAs layer, an aluminum arsenide (AlAs) layer, etc.)2O3) And (3) a layer. In some embodiments, the thickness of the oxide layer 212 may be in a range from about 0.007 μm to about 0.04 μm, such as 0.02 μm. In some embodiments, an oxide trench (not shown in fig. 2) etched around the VCSEL200 may allow vapor to enter the epitaxial layer forming the oxide layer 212. In some embodiments, the oxide pores have a circular shape. In some embodiments, the oxide pores have a non-circular shape. In some embodiments, the size (e.g., diameter) of the oxide pores formed by oxide layer 212 is in a range from about 1 μm to about 300 μm, such as 5 μm or 8 μm. In some embodiments, the oxide layer 212 may be on or in the p-type layer 210. In some embodiments, an oxide layer may be on tunnel junction 214. In some embodiments, the oxide layer 212 may be in the n-type top mirror 216. In some embodiments, the oxide layer 212 may be n-type (e.g., when the oxide layer 212 is on the opposite side of the tunnel junction 214 from the p-type layer 210).
The tunnel junction 214 includes one or more layers to invert the carrier type of the n-type top mirror 216. That is, the tunnel junction 214 includes one or more layers that convert electrons from the n-type top mirror 216 to holes in the p-type layer 210. In some embodiments, tunnel junction 214 is formed by placing one or more layers of highly doped n-type and p-type materials (commonly referred to as n + + and p + +), respectively. The tunnel junction 214 allows electrons injected from above the tunnel junction 214 (through the n-type top mirror 216) to be transferred to holes below the tunnel junction 214 (in the p-type layer 210) due to the high intrinsic electric field formed by the junction of the highly doped material. In some embodiments, the tunnel junction 214 may have a total thickness in a range from about 0.01 μm to about 0.12 μm.
In some embodiments, the tunnel junction 214 improves the performance of the VCSEL200 by reducing the voltage drop across the VCSEL200 (e.g., as compared to the VCSEL 100). For example, the use of the tunnel junction 214 enables the VCSEL200 to include the n-type top mirror 216 and the relatively thin p-type layer 210 over the active region 208 (while the VCSEL100 includes the relatively thick p-type DBR 112 and no n-type material over the active region 108). As a result, the voltage drop across the VCSEL200 is reduced, thereby improving the performance of the VCSEL200 (compared to the VCSEL 100). It is worth noting that in operation of the VCSEL200, there may be some voltage drop across the tunnel junction 214 (e.g., about 0.3V for a well optimized junction), which may increase at higher current densities. Accordingly, the tunnel junction 214 may be placed so as to minimize optical loss and additional voltage drop, and maximize the benefit of higher mobility of the n-type carrier.
The n-type top mirror 216 is at least a portion of a top reflector of an optical resonator of the VCSEL200 formed from an n-type material. For example, the n-type top mirror 216 may include a DBR mirror, a dielectric mirror, and the like. In some embodiments, the n-type top mirror 216 may have a thickness in a range from about 1 μm to about 6 μm, such as 3 μm.
The top contact layer 218 is a layer in electrical contact (e.g., directly or through one or more other layers, as described below) with the n-type top mirror 216 through which current can flow. In some embodiments, the top contact layer 218 comprises an annealed metallization layer. For example, the top contact layer 218 may include a chromium-gold (Cr-Au) layer, a gold-zinc (Au-Zn) layer, a titanium-platinum-gold (TiPtAu) layer, a gold-germanium-nickel (AuGeNi) layer, a palladium-germanium-gold (PdGeAu) layer, and the like. In some embodiments, the thickness of top contact layer 218 is in a range from about 0.03 μm to about 0.3 μm, such as 0.2 μm. In some embodiments, the top contact layer 218 has an annular shape, a slotted annular shape, a gear shape, or another circular or non-circular shape (e.g., depending on the design of the VCSEL 200). In some embodiments, top contact layer 218 is formed of an n-type material (i.e., top contact layer 218 may be an n-type contact layer). For example, when the VCSEL200 includes a single tunnel junction, the top contact layer 218 may be an n-type contact layer. Fig. 3A and 3B, 4A and 4B, 5A and 5B, and 6A and 6B illustrate an exemplary embodiment of the VCSEL200 in which the top contact layer 218 is an n-type contact layer. In some embodiments, the top contact layer 218 is formed of a p-type material (i.e., the top contact layer 218 may be a p-type contact layer). For example, when the VCSEL200 includes two tunnel junctions, the top contact layer 218 may be a p-type contact layer. Fig. 7A and 7B illustrate an exemplary embodiment of a VCSEL200 in which the top contact layer 218 is a p-type contact layer.
The top metal 220 comprises a metal layer on the front side of the VCSEL 200. For example, the top metal 220 may be a layer in electrical contact with the top contact layer 218. In some embodiments, as shown in fig. 2, the top metal 220 may serve as the anode of the VCSEL 200. In some embodiments, top metal 220 is formed of an n-type material (i.e., top metal 220 may be an n-type metal). For example, when the VCSEL200 includes a single tunnel junction, the top metal 220 may be an n-type metal. Fig. 3A and 3B, 4A and 4B, 5A and 5B, and 6A and 6B illustrate an exemplary embodiment of a VCSEL200 in which the top metal 220 is an n-type metal. In some embodiments, the top metal 220 is formed of a p-type material (i.e., the top metal 220 may be a p-type metal). For example, when the VCSEL200 includes two tunnel junctions, the top metal 220 may be a p-type metal. Fig. 7A and 7B show an exemplary embodiment of a VCSEL200 in which the top metal 220 is a p-type metal.
The number, arrangement, thickness, order, symmetry, etc. of the layers shown in fig. 2 are provided as examples. In practice, the VCSEL200 may include additional layers, fewer layers, different layers, layers of different configurations, or layers arranged differently than the layers shown in FIG. 2. Additionally or alternatively, one set of layers (e.g., one or more layers) of the VCSEL200 can perform one or more functions described as being performed by another set of layers of the VCSEL200, and any layer can include more than one layer.
Figures 3A and 3B are diagrams illustrating a first exemplary embodiment of a VCSEL200 with a tunnel junction 214 as described herein. In the example shown in fig. 3A and 3B, the p-type layer 210 is a p-type DBR, the oxide layer 212 is on or in the p-type DBR (e.g., the topmost portion of the p-type DBR), and the tunnel junction 214 is on the oxide layer 212. Notably, the VCSEL200 shown in figure 3B includes a dielectric layer 222 isolation implant 224. The exemplary embodiment of the VCSEL200 shown in fig. 3A and 3B may be desirable because most of the structure of the VCSEL200 is unchanged (e.g., compared to the VCSEL 100), which means that the manufacturability of this exemplary embodiment of the VCSEL200 is increased.
The number, arrangement, thickness, order, symmetry, etc. of the layers shown in fig. 3A and 3B are provided as examples. In practice, the VCSEL200 may include additional layers, fewer layers, different configurations of layers, or different arrangements of the layers 3A and 3B.
Fig. 4A and 4B are diagrams illustrating a second exemplary embodiment of a VCSEL200 with a tunnel junction 214 as described herein. In the example shown in fig. 4A and 4B, the p-type layer 210 is a p-type DBR, the oxide layer 212 is in the p-type DBR (e.g., such that a first portion of the p-type DBR is above the oxide layer 212 and a second portion of the p-type DBR is below the oxide layer 212), and the tunnel junction 214 is on the p-type DBR. Similar to the exemplary embodiment shown in fig. 3A and 3B, the exemplary embodiment of the VCSEL200 shown in fig. 4A and 4B may be desirable because most of the structure of the VCSEL200 is unchanged (e.g., compared to the VCSEL 100), which means that the manufacturability of this exemplary embodiment of the VCSEL200 is increased.
The number, arrangement, thickness, order, symmetry, etc. of the layers shown in fig. 4A and 4B are provided as examples. In practice, the VCSEL200 may include additional layers, fewer layers, different configurations of layers, or different arrangements of the layers 4A and 4B.
Fig. 5A and 5B are diagrams illustrating a third exemplary embodiment of a VCSEL200 with a tunnel junction 214 as described herein. In the example shown in fig. 5A and 5B, the p-type layer 210 is a p-type DBR, the tunnel junction 214 is on the p-type DBR, and the oxide layer 212 is on the tunnel junction 214. The exemplary embodiment shown in fig. 5A and 5B moves the p-type DBR and the oxide layer 212 more over the tunnel junction 214 than the exemplary embodiment shown in fig. 3A and 3B and the exemplary embodiment shown in fig. 4A and 4B, which may improve resistance, optical loss, and current injection, and thus overall device performance.
The number, arrangement, thickness, order, symmetry, etc. of the layers shown in fig. 5A and 5B are provided as examples. In practice, the VCSEL200 may include additional layers, fewer layers, different structural layers, or a different arrangement of layers.
Fig. 6A and 6B are diagrams illustrating a fourth exemplary embodiment of a VCSEL200 with a tunnel junction 214 as described herein. In the example shown in fig. 6A and 6B, the p-type layer 210 is a p-type spacer, the tunnel junction 214 is on the p-type spacer, and the oxide layer 212 is on the tunnel junction 214. Notably, in the exemplary embodiment shown in fig. 6A and 6B, there is no p-DBR (i.e., the top mirror of the VCSEL200 consists entirely of the n-type top mirror 216). This design may provide the greatest performance improvement over VCSEL 100.
The number, arrangement, thickness, order, symmetry, etc. of the layers shown in fig. 6A and 6B are provided as examples. In practice, the VCSEL600 may include additional layers, fewer layers, different structured layers, or different arrangements of the layers 6A and 6B.
As described above, in the exemplary embodiments of the VCSEL200 shown in fig. 3A and 3B, fig. 4A and 4B, fig. 5A and 5B, and fig. 6A and 6B, the top contact layer 218 and the top metal 220 are n-type materials (rather than p-type materials, as in the VCSEL 100). Thus, doping, metal composition, metal deposition methods, and/or alloying may need to be designed to achieve low resistance contacts that are also able to withstand subsequently performed wafer fabrication process steps, some of which are performed at high temperatures or, like oxidation processes, at high temperatures and high humidity. Thus, in some cases, to simplify fabrication and follow similar fabrication steps associated with fabricating the VCSEL100, the VCSEL200 can include a second tunnel junction.
Fig. 7A and 7B are schematic diagrams illustrating an exemplary VCSEL200 having a tunnel junction 214 and a tunnel junction 226 as described herein. As shown in fig. 2 and 3, and as shown in fig. 7A and 7B, a (second) tunnel junction 226 may be placed over the n-type top mirror 216 (e.g., with the p + + layer continuing to the surface). In this implementation, the top contact layer 218 and the top metal 220 may be p-type materials and thus may be formed as a tunnel contact compatible with high temperature oxidation. Notably, the tunnel junction 226 may have a lower resistance than the tunnel junction 214 because the tunnel junction 214 may be exposed to the elevated growth temperature in a relatively short time.
The number, arrangement, thickness, order, symmetry, etc. of the layers shown in fig. 7A and 7B are provided as examples. In practice, VCSEL700 may include additional layers, fewer layers, different configurations of layers, or different arrangements of layers.
Fig. 8A and 8B are graphs showing a comparison of a typical current-voltage curve of the VCSEL100 and a simulated current-voltage curve of the VCSEL 200. Line 802 corresponds to VCSEL100 and line 804 corresponds to VCSEL200 (i.e., a VCSEL in which portions of the p-type material are replaced with n-type material). In this example, the resistance of the VCSEL100 is 70 ohms (Ω)), and the ratio of the p-type DBR resistance to the n-type DBR resistance is approximately 2. This results in a p-type DBR resistance of about 40 Ω, an n-type DBR resistance of about 20 Ω, and other layers with resistances of about 10 Ω. In contrast, in the VCSEL200, the resistance across the p-type DBR is reduced to about 25 Ω and there is an additional resistance of 8 Ω across the tunnel junction 214. In this case, the net result is a reduced voltage drop across the chip, which improves overall efficiency. This improvement is higher for devices operating at high peak currents (e.g., typically with low duty cycles), such as devices used for direct time-of-flight sensing.
As described above, fig. 8A and 8B are provided as examples. Other examples may be different than that described with respect to fig. 8A and 8B.
Fig. 9 is a flow chart of an example process 900 related to fabricating a VCSEL including a tunnel junction as described herein.
As shown in fig. 9, the process 900 may include forming an n-type bottom mirror on a surface of an n-type substrate layer (block 910). For example, as described above, an n-type mirror may be formed on the surface of an n-type substrate layer.
As further shown in fig. 9, the process 900 may include forming an active region on the n-type bottom mirror (block 920). For example, as described above, the active region may be formed on an n-type bottom mirror.
As further shown in fig. 9, the process 900 may include forming a p-type layer over the active region (block 930). For example, as described above, a p-type layer may be formed on the active region.
As further shown in fig. 9, the process 900 may include forming an oxide layer over the active region (block 940). For example, as described above, an oxide layer may be formed over the active region.
As further shown in fig. 9, the process 900 may include forming a tunnel junction over the p-type layer, wherein the oxide layer is formed on or in the p-type layer and the tunnel junction is formed on the oxide layer, or the tunnel junction is formed on the p-type layer and the oxide layer is formed on the tunnel junction (block 950). For example, the tunnel junction may be formed over a p-type layer, with either an oxide layer formed on or in the p-type layer and the tunnel junction formed on the oxide layer, or a tunnel junction formed on a p-type layer and the oxide layer formed on the tunnel junction, as described above.
As further shown in fig. 9, the process 900 may include forming an n-type top mirror over the tunnel junction (block 960). For example, as described above, an n-type top mirror may be formed over the tunnel junction.
Process 900 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and/or in conjunction with one or more other processes described elsewhere herein.
In a first embodiment, the process 900 includes forming an n-type top contact layer on the n-type top mirror and forming an n-type top metal on the n-type top contact layer.
In a second embodiment, alone or in combination with the first embodiment, the p-type layer is a p-type DBR.
In a third embodiment, alone or in combination with one or more of the first and second embodiments, the p-type layer is a p-type spacer layer.
In a fourth embodiment, alone or in combination with one or more of the first through third embodiments, the process 900 includes forming another tunnel junction on the n-type top mirror, forming a p-type top contact layer on the another tunnel junction, and forming a p-type top metal on the p-type top contact layer.
In a fifth embodiment, alone or in combination with one or more of the first through fourth embodiments, the oxide layer is in an n-type top mirror.
In a sixth embodiment, alone or in combination with one or more of the first through fifth embodiments, the p-type layer has less than six layer pairs.
In a seventh embodiment, alone or in combination with one or more of the first through sixth embodiments, the p-type layer has a thickness of less than or equal to 0.5 microns.
Although fig. 9 shows example blocks of the process 900, in some implementations, the process 900 may include additional blocks, fewer blocks, different blocks, or a different arrangement of blocks than those depicted in fig. 9. Additionally or alternatively, two or more blocks of process 900 may be performed in parallel.
The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Modifications and variations are possible in light of the above disclosure or may be acquired from practice of the embodiments. Furthermore, any of the embodiments described herein may be combined unless the foregoing disclosure explicitly provides a reason that one or more embodiments may not be combined.
Even if specific combinations of features are cited in the claims and/or disclosed in the description, these combinations are not intended to limit the disclosure of the various embodiments. In fact, many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of the various embodiments includes each dependent claim in combination with every other claim in the claim set.
No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more," and further, as used herein, the article "the" is intended to include one or more items associated with the article "the" and may be used interchangeably with "the one or more," and further, as used herein, the term "group" is intended to include one or more items (e.g., related items, unrelated items, combinations of related and unrelated items, etc.) and may be used interchangeably with "one or more. When only one item is intended, the phrase "only one" or similar language is used. Furthermore, as used herein, the term "having" and the like are intended to be open-ended terms. In addition, the phrase "based on" is intended to mean "based, at least in part, on" unless explicitly stated otherwise. Further, as used herein, the term "or" when used in series is intended to be inclusive and may be used interchangeably with "and/or" unless specifically stated otherwise (e.g., if used in conjunction with "either" or "only one of"). Furthermore, spatially relative terms, such as "above," "below," "lower," "beneath," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device, apparatus, and/or element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.
Cross Reference to Related Applications
This patent application claims priority from U.S. provisional patent application No. 63/028,248 entitled "improving performance of vertical cavity surface emitting lasers using tunnel junctions", filed on 21/5/2020. The disclosure of the prior application is considered to be part of the present patent application and is incorporated by reference into the present patent application.