阅读说明：本技术 基于自对准技术的vcsel芯片柱面刻蚀方法及其应用 (VCSEL chip cylindrical surface etching method based on self-alignment technology and application thereof ) 是由 王光辉 王青 江蔼庭 吕朝晨 赵风春 钱旭 于 2021-07-15 设计创作，主要内容包括：本发明公开了基于自对准技术的VCSEL芯片柱面刻蚀方法及其应用。该VCSEL芯片柱面刻蚀方法包括：在衬底上逐层形成N接触层、NDBR层、有源层、氧化层、PDBR层和P接触层,P接触层上形成有金属圆环；对金属圆环外缘外的区域进行刻蚀,以便在金属圆环下方刻蚀出柱形面并裸露出氧化层,其中,刻蚀利用金属圆环做硬掩膜层,并利用中心掩膜层遮挡金属圆环的中空位置,中心掩膜层的边缘位于金属圆环的外缘和内缘之间。该方法不仅工艺简单,便于实施,而且采用自对准工艺,掩膜层中心无需正对圆环中心,减小了对套刻精度的依赖,能够大大提高VCSEL芯片的质量和成品率,有效克服了光刻套刻精度问题带来的氧化孔偏移的风险。(The invention discloses a VCSEL chip cylindrical surface etching method based on a self-alignment technology and application thereof. The VCSEL chip cylindrical surface etching method comprises the following steps: forming an N contact layer, an NDBR layer, an active layer, an oxide layer, a PDBR layer and a P contact layer on a substrate layer by layer, wherein a metal ring is formed on the P contact layer; and etching the area outside the outer edge of the metal ring so as to etch a cylindrical surface below the metal ring and expose the oxide layer, wherein the metal ring is used as a hard mask layer in the etching process, the hollow position of the metal ring is shielded by using a central mask layer, and the edge of the central mask layer is positioned between the outer edge and the inner edge of the metal ring. The method has the advantages that the process is simple and convenient to implement, the self-alignment process is adopted, the center of the mask layer does not need to be over against the center of the circular ring, the dependence on the alignment precision is reduced, the quality and the yield of the VCSEL chip can be greatly improved, and the risk of oxide hole deviation caused by the problem of the photoetching alignment precision is effectively overcome.)

1. A VCSEL chip cylindrical surface etching method is characterized by comprising the following steps:

(1) forming an N contact layer, an NDBR layer, an active layer, an oxide layer, a PDBR layer and a P contact layer on a substrate layer by layer, wherein a metal ring is formed on the P contact layer;

(2) etching the area outside the outer edge of the metal ring so as to etch a cylindrical surface below the metal ring and expose the oxide layer,

the etching method comprises the steps of etching a metal ring, wherein the metal ring is used as a hard mask layer, a central mask layer is used for shielding the hollow position of the metal ring, and the edge of the central mask layer is located between the outer edge and the inner edge of the metal ring.

2. The method of claim 1, wherein the central mask layer is circular, and a diameter of the central mask layer is larger than an inner diameter of the metal ring and smaller than an outer diameter of the metal ring.

3. The method of claim 1 or 2, wherein the central masking layer is a photoresist layer.

4. The method according to claim 3, wherein in the step (2), the PDBR layer outside the hollow position of the metal ring and the outer edge of the metal ring is covered with a photoresist layer respectively so as to etch a cylindrical surface below the metal ring.

5. A method according to claim 1 or 4, characterized in that the etching extends to the active layer.

6. The method of claim 1, wherein the substrate is a GaAs substrate and the active layer is a MQW quantum well active layer.

7. A method of fabricating a VCSEL chip, comprising: the method of any one of claims 1 to 6.

8. The method of claim 7, further comprising:

oxidizing the oxide layer exposed from the cylindrical surface so as to oxidize the oxide layer from outside to inside and form a part of non-oxidized area below the metal ring; and/or the presence of a gas in the gas,

and removing the mask layer except the metal ring.

9. A VCSEL chip, characterized in that the VCSEL chip is prepared by the method for etching the cylindrical surface of the VCSEL chip as claimed in any one of claims 1 to 6 or the method for preparing the VCSEL chip as claimed in any one of claims 7 to 8.

10. An electronic device comprising the VCSEL chip of claim 9.

Technical Field

The invention belongs to the field of chips, and particularly relates to a VCSEL chip cylindrical surface etching method based on a self-alignment technology and application thereof.

Background

In the prior VCSEL device process, photoresist is used as a mask in a cylindrical surface etching procedure, and a circular cylindrical surface is etched by a dry etching method. However, the lithography process has a problem of a certain alignment accuracy, and the center of the circular mask pattern deviates from the center of the metal ring after the cylindrical surface lithography development. And the center position of the oxidation hole deviates from the center of the metal ring after the subsequent oxidation process is finished, so that the metal ring shields a laser beam, the laser power is reduced, and the shape of a light spot is distorted.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the invention aims to provide a VCSEL chip cylindrical surface etching method based on a self-alignment technology and application thereof. The VCSEL chip cylindrical surface etching method is simple in process and convenient to implement, and adopts a self-alignment process, the center of the mask layer does not need to be over against the center of the circular ring, so that the dependence on the alignment precision is reduced, the quality and the yield of the VCSEL chip can be greatly improved, and the risk of oxide hole deviation caused by the problem of the photoetching alignment precision is effectively overcome.

According to a first aspect of the invention, the invention provides a method for etching a cylindrical surface of a VCSEL chip. According to an embodiment of the invention, the method comprises:

(1) forming an N contact layer, an NDBR layer, an active layer, an oxide layer, a PDBR layer and a P contact layer on a substrate layer by layer, wherein a metal ring is formed on the P contact layer;

(2) etching the area outside the outer edge of the metal ring so as to etch a cylindrical surface below the metal ring and expose the oxide layer,

the etching method comprises the steps of etching a metal ring, wherein the metal ring is used as a hard mask layer, a central mask layer is used for shielding the hollow position of the metal ring, and the edge of the central mask layer is located between the outer edge and the inner edge of the metal ring.

The VCSEL chip cylindrical surface etching method of the embodiment of the invention at least has the following advantages: 1. the existing metal ring is used as a hard mask, and the mask layer smaller than the outer diameter of the ring is used for shielding the hollow position of the ring to serve as the mask of the central part, wherein the mask of the central part of the metal ring only needs to shield the hollow part of the ring and does not overflow the outer diameter of the ring, and the size of the mask layer of the middle part is smaller than the outer diameter of the metal ring, so that the mask does not need to be over against the center of the ring, the dependence on the alignment precision is reduced, and therefore, the self-alignment process of cylindrical surface etching can be realized, and even if the alignment is deviated left and right, the center of a non-oxidation area of a subsequent oxide layer can be ensured to be aligned with the center of a light-emitting window, and the mask is prevented from being shielded by the metal ring; 2. the method is simple in process and convenient to implement, and the quality and yield of the VCSEL chip can be greatly improved.

In addition, the VCSEL chip cylindrical surface etching method according to the above embodiment of the present invention may further have the following additional technical features:

in some embodiments of the present invention, the central mask layer is circular, and a diameter of the central mask layer is larger than an inner diameter of the metal ring and smaller than an outer diameter of the metal ring.

In some embodiments of the present invention, the central mask layer is a photoresist layer.

In some embodiments of the invention, in the step (2), a photoresist layer covers the hollow position of the metal ring and the PDBR layer outside the outer edge of the metal ring respectively, so as to etch a cylindrical surface below the metal ring.

In some embodiments of the invention, the etching extends to the active layer.

In some embodiments of the invention, the substrate is a GaAs substrate and the active layer is a MQW quantum well active layer.

According to a second aspect of the invention, a method of fabricating a VCSEL chip is provided. According to an embodiment of the invention, the method comprises: the VCSEL chip cylindrical surface etching method is disclosed. Compared with the prior art, the method is simple in process, the center of the non-oxidation area of the oxidation layer in the finally manufactured VCSEL chip is always opposite to the center of the light outlet window, and the laser power of the VCSEL chip is stable.

In some embodiments of the present invention, the method of fabricating a VCSEL chip further comprises: oxidizing the oxide layer exposed from the cylindrical surface so as to oxidize the oxide layer from outside to inside and form a part of non-oxidized area below the metal ring; and/or removing the mask layer except the metal ring.

According to a third aspect of the invention, the invention proposes a VCSEL chip. According to the embodiment of the invention, the VCSEL chip is manufactured by adopting the VCSEL chip cylindrical surface etching method or the VCSEL chip manufacturing method. Compared with the prior art, the laser power of the VCSEL chip is more stable.

According to a fourth aspect of the invention, an electronic device is presented. According to an embodiment of the invention, the electronic device comprises the VCSEL chip described above. Compared with the prior art, the electronic device has better stability and higher reliability.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a flow chart of a VCSEL chip cylinder etching method according to one embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a fully structured epitaxial wafer after normal cylindrical etching and oxidation by a conventional process, in accordance with one embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of a fully structured epitaxial wafer after completion of its cylindrical etching and oxidation with abnormal exposure and alignment according to an embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of a VCSEL chip after a cylindrical etching and oxidation of a fully structured epitaxial wafer is completed according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

In the description of the present invention, it is to be understood that the terms "center", "thickness", "upper", "lower", "inner", "outer", "circumferential", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Further, in the present invention, unless otherwise explicitly specified or limited, a first feature "on" or "under" a second feature may be directly contacted with the first and second features, or indirectly contacted with the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

According to a first aspect of the invention, the invention provides a method for etching a cylindrical surface of a VCSEL chip. According to the embodiment of the invention, the method adopts the self-alignment process, and effectively overcomes the risk of oxide hole deviation caused by the photoetching alignment precision problem. The following describes the VCSEL chip cylindrical surface etching method in detail with reference to fig. 1 to 4.

(1) Forming an N contact layer, an NDBR layer, an active layer, an oxide layer, a PDBR layer and a P contact layer on a substrate layer by layer, wherein a metal ring is formed on the P contact layer

According to the embodiment of the invention, an N contact layer, an NDBR layer, an active layer, an oxide layer, a PDBR layer and a P contact layer are sequentially grown on a GaAs substrate according to a layered structure, wherein the substrate can be a GaAs substrate, and the active layer can be an MQW quantum well active layer. Wherein, the cross-sectional view after the VCSEL chip shown in fig. 4 is used to complete the cylindrical etching and oxidation of the full-structure epitaxial wafer is understood, and 1 is a substrate; 2 is an N contact layer which is used for forming N-type ohmic contact; NDBR 3, which is used for forming a reflector; 4 is an active region which functions as a light emitting region; 5 is an oxide layer which is used for limiting current and light; PDBR 6 is used for forming a reflector; 7 is a P contact layer for forming a P-type ohmic contact; 9 is the aperture (namely, non-oxidation area) formed after the oxidation of the oxidation layer, and the function is to form the limitation of optical field and current; 10 is a metal ring; 11 is the laser exit window area. Wherein, 8 and 81 are developed photoresist, which has the function of forming a soft mask, and the residual photoresist after etching can be cleaned and removed, so that the process is convenient and reserved. It should be noted that the growth process of the N contact layer, the NDBR layer, the active layer, the oxide layer, the PDBR layer, and the P contact layer in the present invention is not particularly limited, and those skilled in the art can select the growth process according to actual needs, for example, the growth process can be completed by using a conventional process, and the materials of the substrate and each epitaxial layer are not particularly limited, and those skilled in the art can select the growth process according to actual needs.

(2) Etching the outer edge of the metal ring to form a cylindrical surface and expose the oxide layer, wherein the metal ring is used as a hard mask layer, the central mask layer is used for shielding the hollow position of the metal ring, and the edge of the central mask layer is positioned between the outer edge and the inner edge of the metal ring

According to the embodiment of the invention, the etching process adopted by the invention is equivalent to the reduction of the diameter of the circular pattern in the mask pattern compared with the prior art. Referring to fig. 4, after etching, the pillar diameter is the same as the outer diameter of the metal ring.

Wherein, as understood by combining with the schematic cross-sectional view of fig. 2 after the conventional process is adopted to normally complete the cylindrical etching and oxidation of the epitaxial wafer with the full structure, if the exposure alignment is abnormal, the situation shown in fig. 3 will occur: the position of the photoresist mask deviates due to the alignment precision, the center position of the etched cylindrical surface deviates from the center position of the metal ring position, the center of the oxidized hole deviates from the center of the light-emitting window after oxidation, and the emergent laser is shielded by the metal ring. Aiming at the technical problem, the inventor of the application finds that the problem can be solved by reducing the diameter (refer to 81 in fig. 4) of a circular mask in a mask pattern covered on a metal circular ring, the partial mask only needs to shield the hollow part of the circular ring and does not overflow the outer diameter of the circular ring, the method can realize self-aligned cylindrical surface etching by using the existing metal circular ring as a hard mask, and therefore even if the overlay is deviated left and right, the center of an oxidation hole can be ensured to be aligned with the center of a light-emitting window, and the shielding by the metal circular ring is avoided. As shown in fig. 4: by adopting the self-alignment improved process, even if the photoresist slightly deviates to the right, the center of the oxidized hole is still aligned to the center of the light-emitting window.

According to an embodiment of the present invention, referring to fig. 4, it is understood that the shape of the central mask layer 81 for shielding the hollow position of the metal ring 10 in the present invention is not particularly limited, and those skilled in the art may select the central mask layer according to actual needs by only controlling the edge of the central mask layer 81 to be located between the inner edge and the outer edge of the metal ring 10, for example, the central mask layer 81 may be circular, and the diameter of the central mask layer 81 may be larger than the inner diameter of the metal ring and smaller than the outer diameter of the metal ring, so that the self-alignment process may be implemented by using the central mask layer 81 as a soft mask and combining the metal ring as a hard mask.

According to a further embodiment of the present invention, the central mask layer may preferably be a photoresist layer, whereby the substrate epitaxy etching may be performed in combination with photolithography techniques to etch the pillar-shaped surface under the metal ring and expose the oxide layer. During etching, the etching depth may extend to the active layer but not penetrate the active layer, so that the oxide layer on the pillar surface is fully exposed, so as to perform subsequent oxidation treatment, such that the outer portion of the oxide layer under the metal ring is oxidized, and an unoxidized region (as shown in fig. 4 at 9) remains in the middle.

According to another embodiment of the present invention, referring to fig. 4, when the etching process in step (2) is performed, a photoresist layer may be respectively covered on the hollow position of the metal ring 10 and the PDBR layer 7 outside the outer edge of the metal ring, so as to etch a cylindrical surface below the metal ring.

In summary, the VCSEL chip cylindrical surface etching method of the above embodiment of the present invention has at least the following advantages: 1. the existing metal ring is used as a hard mask, and the mask layer smaller than the outer diameter of the ring is used for shielding the hollow position of the ring to serve as the mask of the central part, wherein the mask of the central part of the metal ring only needs to shield the hollow part of the ring and does not overflow the outer diameter of the ring, and the size of the mask layer of the middle part is smaller than the outer diameter of the metal ring, so that the mask does not need to be over against the center of the ring, the dependence on the alignment precision is reduced, and therefore, the self-alignment process of cylindrical surface etching can be realized, and even if the alignment is deviated left and right, the center of a non-oxidation area of a subsequent oxide layer can be ensured to be aligned with the center of a light-emitting window, and the mask is prevented from being shielded by the metal ring; 2. the method is simple in process and convenient to implement, and the quality and yield of the VCSEL chip can be greatly improved.

According to a second aspect of the invention, a method of fabricating a VCSEL chip is provided. According to an embodiment of the invention, the method comprises: the VCSEL chip cylindrical surface etching method is disclosed. Compared with the prior art, the method is simple in process, the center of the non-oxidation area of the oxidation layer in the finally manufactured VCSEL chip is always opposite to the center of the light outlet window, and the laser power of the VCSEL chip is stable. Wherein, the method of fabricating the VCSEL chip may further include: oxidizing the oxide layer exposed from the cylindrical surface so as to oxidize the oxide layer from outside to inside and form a part of non-oxidized area below the metal ring; and/or removing the mask layer except the metal ring. It should be noted that the features and effects described for the above VCSEL chip cylindrical surface etching method are also applicable to the method for preparing a VCSEL chip, and are not described in detail here.

According to a third aspect of the invention, the invention proposes a VCSEL chip. According to the embodiment of the invention, the VCSEL chip is manufactured by adopting the VCSEL chip cylindrical surface etching method or the VCSEL chip manufacturing method. Compared with the prior art, the laser power of the VCSEL chip is more stable. It should be noted that the features and effects described for the above-mentioned VCSEL chip cylindrical surface etching method and the method for manufacturing a VCSEL chip are also applicable to the VCSEL chip, and are not described in detail here.

According to a fourth aspect of the invention, an electronic device is presented. According to an embodiment of the invention, the electronic device comprises the VCSEL chip described above. Compared with the prior art, the electronic device has better stability and higher reliability. It should be noted that the kind of the electronic device in the present invention is not particularly limited, and those skilled in the art can select the electronic device according to actual needs. In addition, it should be noted that the features and effects described for the VCSEL chip are also applicable to the electronic device, and are not described in detail here.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.