阅读说明：本技术 垂直腔面发射激光器芯片 (Vertical cavity surface emitting laser chip ) 是由 佟存柱 王延靖 汪丽杰 王立军 于 2021-09-24 设计创作，主要内容包括：本发明提供一种垂直腔面发射激光器芯片,包括衬底和从下至上依次制备在衬底上的缓冲层、N型DBR层、第一SCH层、第二SCH层、量子阱结构层、第三SCH层、氧化结构层、P型DBR层、P型接触层,在第一SCH层与量子阱结构层之间制备有隧穿层,隧穿层的禁带宽度大于量子阱结构层的禁带宽度,载流子依次经N型DBR层、第一SCH层传输到隧穿层,再以隧穿方式穿过隧穿层注入量子阱结构层中以隧穿方式传输。本发明通过在SCH层与量子阱结构层之间增加隧穿层,并且优化量子阱结构层中势垒层的厚度,使得载流子以隧穿的方式注入量子阱结构层并且在量子阱层与势垒层之间隧穿传输,从而改善载流子传输效应与热载流子效应并提高微分增益,最终实现高调制带宽。(The invention provides a vertical cavity surface emitting laser chip, which comprises a substrate, and a buffer layer, an N-type DBR layer, a first SCH layer, a second SCH layer, a quantum well structure layer, a third SCH layer, an oxidation structure layer, a P-type DBR layer and a P-type contact layer which are sequentially prepared on the substrate from bottom to top, wherein a tunneling layer is prepared between the first SCH layer and the quantum well structure layer, the forbidden bandwidth of the tunneling layer is larger than that of the quantum well structure layer, and a current carrier is transmitted to the tunneling layer through the N-type DBR layer and the first SCH layer in sequence, then is injected into the quantum well structure layer through the tunneling layer in a tunneling mode and is transmitted in the tunneling mode. According to the invention, the tunneling layer is added between the SCH layer and the quantum well structure layer, and the thickness of the barrier layer in the quantum well structure layer is optimized, so that a current carrier is injected into the quantum well structure layer in a tunneling mode and is transmitted between the quantum well layer and the barrier layer in a tunneling mode, the current carrier transmission effect and the hot carrier effect are improved, the differential gain is improved, and the high modulation bandwidth is finally realized.)

1. The utility model provides a vertical cavity surface emitting laser chip, includes the substrate and from supreme preparation in proper order down buffer layer, N type DBR layer, first SCH layer, quantum well structural layer, second SCH layer, oxidation structural layer, P type DBR layer, P type contact layer on the substrate, its characterized in that first SCH layer with it has prepared the tunneling layer to be in between the quantum well structural layer, the forbidden bandwidth width of tunneling layer is greater than the forbidden bandwidth of quantum well structural layer, the current carrier passes through in proper order N type DBR layer first SCH layer transmits the tunneling layer passes again the tunneling layer pours into in the quantum well structural layer, and transmit with the tunneling mode in the quantum well structural layer.

2. A vertical cavity surface emitting laser chip as claimed in claim 1, wherein said quantum well structure layer comprises a quantum well layer and a barrier layer stacked in this order, a forbidden bandwidth of said tunneling layer is larger than a forbidden bandwidth of said barrier layer, and said carriers are transported between said quantum well layer and said barrier layer in a tunneling manner.

3. A vertical cavity surface emitting laser chip according to claim 2, wherein the number of said quantum well layers is three to five.

4. A vertical cavity surface emitting laser chip according to any one of claims 1 to 3, wherein said first SCH layer includes a first SCH sublayer and a second SCH sublayer, a forbidden bandwidth of said second SCH sublayer being smaller than a forbidden bandwidth of said first SCH sublayer, and a forbidden bandwidth of said second SCH layer being the same as a forbidden bandwidth of said first SCH sublayer.

5. A vertical cavity surface emitting laser chip according to any one of claims 1 to 3, wherein said oxide structure layer includes at least one oxide layer.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a tunneling injection high-speed vertical cavity surface emitting laser chip.

Background

The vertical cavity surface emitting laser used in the communication field has many advantages of high data transmission rate, low cost, low power consumption and the like. With the rapid increase of communication capacity, a vertical cavity surface emitting laser with a higher data transmission rate is urgently needed, the data transmission rate of the vertical cavity surface emitting laser is determined by the modulation bandwidth of the vertical cavity surface emitting laser, the higher the modulation bandwidth is, the higher the data transmission rate is, and the factors limiting the modulation bandwidth of the vertical cavity surface emitting laser are mainly the carrier transmission effect and the hot carrier effect. The important reason for limiting the carrier transmission effect and the hot carrier effect is that the forbidden bandwidths of an SCH (Separate Confinement Heterostructure) layer and a barrier layer are high, carriers need to cross the high energy levels of the SCH layer and the barrier layer for transmission, and effective injection of the carriers and transmission between quantum wells are greatly hindered, so that the improvement of the carrier transmission effect of the carriers through the SCH layer and the barrier layer can greatly improve the modulation bandwidth of the vertical cavity surface emitting laser.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a vertical cavity surface emitting laser chip, in which a tunneling layer is added between an SCH layer and a quantum well layer, and the thickness of a barrier layer is optimized, so that carriers are injected into the quantum well in a tunneling manner and are tunneled between the quantum wells, thereby improving a carrier transport effect and a carrier thermal effect, and increasing a modulation bandwidth of the vertical cavity surface emitting laser.

In order to achieve the purpose, the invention adopts the following specific technical scheme:

the invention provides a vertical cavity surface emitting laser chip, which comprises a substrate, and a buffer layer, an N-type DBR layer, a first SCH layer, a second SCH layer, a quantum well structure layer, a third SCH layer, an oxidation structure layer, a P-type DBR layer and a P-type contact layer which are sequentially prepared on the substrate from bottom to top, wherein a tunneling layer is prepared between the first SCH layer and the quantum well structure layer, the forbidden bandwidth of the tunneling layer is larger than that of the quantum well structure layer, and a current carrier is transmitted to the tunneling layer through the N-type DBR layer and the first SCH layer in sequence, then is injected into the quantum well structure layer through the tunneling layer in a tunneling mode, and is transmitted in the quantum well structure layer in a tunneling mode.

Preferably, the quantum well structure layer comprises a quantum well layer and a barrier layer which are sequentially stacked, the forbidden bandwidth of the tunneling layer is larger than that of the barrier layer, and carriers are transmitted between the quantum well layer and the barrier layer in a tunneling mode.

Preferably, the number of quantum well layers is three to five.

Preferably, the first SCH layer includes a first SCH sublayer and a second SCH sublayer, a forbidden bandwidth of the second SCH sublayer is smaller than that of the first SCH sublayer, and a forbidden bandwidth of the second SCH layer is the same as that of the first SCH sublayer.

Preferably, the oxide structure layer comprises at least one oxide layer.

Compared with the conventional vertical cavity surface emitting laser, the tunneling layer is additionally arranged between the SCH layer and the quantum well structure layer, and the thickness of the barrier layer in the quantum well structure layer is optimized, so that carriers are injected into the quantum well structure layer in a tunneling mode and are transmitted between the quantum well layer and the barrier layer in a tunneling mode, the carrier transmission effect and the hot carrier effect are improved, the differential gain is improved, and the high modulation bandwidth is finally realized.

Drawings

FIG. 1 is a schematic structural diagram of a VCSEL chip provided according to an embodiment of the invention;

FIG. 2 is a schematic diagram illustrating a carrier tunneling transmission principle of a VCSEL chip provided according to an embodiment of the invention;

fig. 3 is a schematic diagram of an energy band structure and an optical field distribution inside a vcsel chip according to an embodiment of the present invention.

Wherein the reference numerals include: the light-emitting diode comprises a substrate 1, a buffer layer 2, an N-type DBR layer 3, a first SCH layer 4, a first SCH sublayer 41, a second SCH sublayer 42, a quantum well structure layer 5, a quantum well layer 51, a barrier layer 52, a second SCH layer 6, an oxidation structure layer 7, a P-type DBR layer 8, a P-type contact layer 9 and a tunneling layer 10.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same reference numerals are used for the same blocks. In the case of the same reference numerals, their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention.

Fig. 1 illustrates a structure of a vertical cavity surface emitting laser chip provided according to an embodiment of the present invention.

As shown in fig. 1, a vertical cavity surface emitting laser chip provided by an embodiment of the present invention includes: the light-emitting diode comprises a substrate 1, a buffer layer 2, an N-type DBR layer 3, a first SCH layer 4, a quantum well structure layer 5, a second SCH layer 6, an oxidation structure layer 7, a P-type DBR layer 8 and a P-type contact layer 9; the substrate 1, the buffer layer 2 and the P-type contact layer 9 are made of GaAs materials, the N-type DBR layer 3 and the P-type DBR layer 8 are made of AlGaAs materials, the tunneling layer 10 is made of AlAs materials, the first SCH layer 4 and the second SCH layer 6 are made of AlGaAs materials, the quantum well structure layer 5 is made of InGaAs, AlGaAs and GaAsP materials, and the oxidation structure layer 7 is made of AlGaAs materials.

The novel quantum well tunneling structure comprises a buffer layer 2, an N-type DBR layer 3, a first SCH layer 4, a quantum well structure layer 5, a second SCH layer 6, an oxide structure layer 7, a P-type DBR8 and a P-type contact layer 9, wherein the two layers are sequentially prepared on a substrate 1 from bottom to top. And transported in a tunneling manner in the quantum well structure layer 5.

The quantum well structure layer 5 includes quantum well layers 51 and barrier layers 52 alternately laminated in this order, for example: the quantum well structure layer 5 is an nth quantum well layer including a first quantum well layer, a first barrier layer, a second quantum well layer, and a second barrier layer … … from bottom to top.

The forbidden band width of the tunneling layer 10 is larger than those of the quantum well layer 51 and the barrier layer 52, and the quantum tunneling effect is obtained.

According to the invention, by optimizing the thickness of the barrier layer 52, when the thickness of the barrier layer 52 reaches a specific value, a quantum tunneling effect is realized, so that carriers can be transmitted in a tunneling manner in the quantum well structure layer 5.

In addition, the thickness of the barrier layer is optimized, so that the coupling effect can be generated among the quantum wells, and the differential gain can be improved.

The forbidden bandwidth of the first SCH layer 4 may be the same as that of the second SCH layer 6, and the second SCH layer 6 plays a role in limiting leakage of carriers out of the active region in the laser.

The forbidden bandwidth of the first SCH layer 4 may be different from the forbidden bandwidth of the second SCH layer 6, and at this time, the first SCH layer 4 is divided into two sublayers with different forbidden bandwidths, which are respectively a first SCH sublayer 41 and a second SCH sublayer 42, the forbidden bandwidth of the second SCH sublayer 42 is smaller than the forbidden bandwidth of the first SCH sublayer 41, and the forbidden bandwidth of the first SCH sublayer 41 is the same as the forbidden bandwidth of the second SCH layer 6.

The purpose of designing the forbidden bandwidth of the second SCH sublayer 42 to be smaller than that of the first SCH sublayer 41 is to increase the energy level difference between the tunneling layer 10 and the second SCH sublayer 42, better achieve quantum tunneling effect and improve hot carrier effect.

Of course, the first SCH layer 4 may employ other numbers of sublayers to tunnel the energy level difference between the layer 10 and the second SCH sublayer 42. The second SCH layer 6 may also be formed of sublayers having different forbidden bandwidths to prevent carriers from leaking out of the active region.

The oxidation structure layer 7 comprises at least one oxidation layer, preferably 6 oxidation layers, and the more oxidation layers, the more parasitic capacitance can be reduced, and the better photoelectric limiting effect can be achieved.

Fig. 2 illustrates the carrier tunneling transmission principle of the vcsel chip provided in accordance with an embodiment of the present invention.

As shown in fig. 2, carriers are transmitted to the tunneling layer 10 sequentially through the N-type DBR layer 3, the first SCH sublayer 41, and the second SCH sublayer 42, and are injected into the first quantum well layer through the tunneling layer 10 in a tunneling manner, and are transmitted among the first quantum well layer, the first barrier layer, the second quantum well layer, and the second barrier layer … … in a tunneling manner.

Since tunneling is a relatively fast process, the carriers can be transported rapidly, and therefore the transport effect of the carriers can be improved. Tunneling transport can avoid relaxation of carriers from a higher energy band to a lower energy band (relaxation process releases a large amount of heat) and does not release a large amount of heat, thereby improving hot carrier effect.

In addition, the modulation bandwidth is related to a carrier transmission effect, a hot carrier effect and a differential gain, the faster the carrier transmission rate is, the higher the modulation bandwidth is, the smaller the thermal effect is, the higher the modulation bandwidth is, and the higher the differential gain is, the higher the modulation bandwidth is. The current carrier is transmitted in a tunneling mode, the current carrier transmission effect and the hot carrier effect can be greatly improved by adopting tunneling transmission, the thickness of the barrier layer is optimized, the coupling effect is generated among all quantum wells, the differential gain is improved, and the modulation bandwidth is improved by the improvement of the three aspects.

Fig. 3 illustrates an energy band structure and an optical field distribution inside a vcsel chip provided according to an embodiment of the present invention.

As shown in FIG. 3, the present invention adopts 5 quantum wells with a resonant cavity length of λ/2, and the quantum wells are located at the peak of the optical field to obtain maximum gain.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "one example," "another example" or "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

The above embodiments of the present invention should not be construed as limiting the scope of the present invention. Any other corresponding changes and modifications made according to the technical idea of the present invention should be included in the protection scope of the claims of the present invention.