阅读说明：本技术 光电子封装和其制造方法 (Optoelectronic package and method of manufacturing the same ) 是由 林长佑 陈纪翰 杨佩蓉 于 2020-05-12 设计创作，主要内容包括：本公开提供了一种光电子封装,所述光电子封装包含：衬底,所述衬底具有第一表面和与所述第一表面相反的第二表面；位于所述衬底的所述第一表面上的光电子组件；以及第一导电通孔,所述第一导电通孔连接所述衬底的所述第一表面和所述第二表面。所述光电子组件电连接到所述第一导电通孔。还提供了一种用于制造所述光电子封装的方法。(The present disclosure provides an optoelectronic package comprising: a substrate having a first surface and a second surface opposite the first surface; an optoelectronic component located on the first surface of the substrate; and a first conductive via connecting the first surface and the second surface of the substrate. The optoelectronic component is electrically connected to the first conductive via. A method for manufacturing the optoelectronic package is also provided.)

1. An optoelectronic package, comprising:

a substrate having a first surface and a second surface opposite the first surface;

an optoelectronic component located on the first surface of the substrate; and

a first conductive via connecting the first surface and the second surface of the substrate,

wherein the optoelectronic component is electrically connected to the first conductive via.

2. The optoelectronic package of claim 1, further comprising a first conductive pattern on the first surface of the substrate, the first conductive pattern electrically connected to the first conductive via.

3. The optoelectronic package of claim 2, further comprising a conductive bump connecting a first electrode of the optoelectronic component to the first conductive pattern.

4. The optoelectronic package of claim 2, further comprising a second conductive pattern on the second surface of the substrate, the second conductive pattern electrically connected to the first conductive via.

5. The optoelectronic package of claim 1, wherein the first conductive via does not overlap a projection of the optoelectronic component.

6. The optoelectronic package of claim 1, further comprising an anti-reflective coating over the first and second surfaces of the substrate.

7. The optoelectronic package of claim 3, further comprising a second conductive via connecting the first and second surfaces of the substrate, wherein a second electrode of the optoelectronic assembly is electrically connected to the second conductive via.

8. The optoelectronic package of claim 1, wherein the first conductive via includes an insulating portion and a conductive portion surrounding the insulating portion.

9. The optoelectronic package of claim 3, wherein the conductive bump is wider than the optoelectronic component.

10. A photonic integrated circuit, comprising:

a carrier having an upper surface;

a filled trench in the carrier and open at the upper surface;

a waveguide adjacent to the filled trench and adjacent to the upper surface; and

an optoelectronic package on the upper surface having an optoelectronic component in the filled trench and aligned with the waveguide.

11. The photonic integrated circuit of claim 10, wherein the filled trench is filled with a glue transparent to electromagnetic signals emitted from the optoelectronic component.

12. The photonic integrated circuit of claim 10, further comprising an optical element in the filled trench, the optical element disposed between the waveguide and the optoelectronic component.

13. The photonic integrated circuit of claim 10, wherein the optical package comprises:

a substrate having a first surface and a second surface opposite the first surface;

the optoelectronic component on the first surface of the substrate; and

a first conductive via connecting the first surface and the second surface of the substrate,

wherein the optoelectronic component is electrically connected to the first conductive via.

14. The photonic integrated circuit of claim 12, wherein the optical package further comprises a conductive pattern on the second surface, the conductive pattern electrically connected to the first via.

15. The photonic integrated circuit of claim 14, further comprising a conductive via connecting a contact pad of the carrier and the conductive pattern on the second surface.

16. The photonic integrated circuit of claim 14, wherein the contact pads are located on the upper surface of the carrier.

17. A method for fabricating an optoelectronic package, comprising:

providing a substrate having a first surface and a second surface;

forming a first via connecting the first surface and the second surface in the substrate;

filling a conductive material in the first through hole to form a first conductive through hole; and

an optoelectronic component is bonded on the first surface and electrically connected to the first conductive via.

18. The method of claim 18, further comprising:

forming a conductive bump on the first surface; and

forming the first via in the substrate so as not to overlap with a projection of the conductive bump.

19. The method of claim 19, further comprising increasing a temperature of the conductive bump by radiation from the second surface of the substrate.

20. The method of claim 19, further comprising forming a first conductive pattern on the first surface prior to forming the conductive bump.

Technical Field

The present disclosure relates to photonic integrated circuits, and in particular to photonic integrated circuits including optoelectronic packages.

Background

To accommodate the development of 5G and cloud computing, communication bandwidth plays an important role. Optical communication has become the primary direction for higher bandwidth communications, as conventional cables are no longer adequate. Edge-coupled lasers are widely used as signal sources in optical communication package packages. The edge-coupled laser die may be integrated with a conventional IC in a face-up or face-down manner.

In the current face-down packaging approach, the active surface of the edge-coupled laser die faces and is bonded to a carrier with an integrated circuit to form a Photonic Integrated Circuit (PIC). The electrodes on the active surface of the edge-coupled laser are bonded to the PIC carrier surface by alloying, making it difficult to perform active alignment when bonding the laser die to the PIC carrier. In addition, the conductive patterns on the PIC carrier must be carefully designed to route the electrical path from the downward-facing electrode of the laser die to the power input without obstructing the optical path. Furthermore, after integration, the laser die is exposed from the PIC package, making the laser die quite fragile to the environment.

Disclosure of Invention

In some embodiments, the present disclosure provides an optoelectronic package comprising: a substrate having a first surface and a second surface opposite the first surface; an optoelectronic component located on the first surface of the substrate; and a first conductive via connecting the first surface and the second surface of the substrate. The optoelectronic component is electrically connected to the first conductive via.

In some embodiments, the present disclosure provides a photonic integrated circuit comprising: a carrier having an upper surface; a filled trench in the carrier and open at the upper surface; a waveguide adjacent to the filled trench and adjacent to the upper surface; and an optoelectronic package on the upper surface having an optoelectronic component in the filled trench and aligned with the waveguide.

In some embodiments, the present disclosure provides a method for fabricating an optoelectronic package, the method comprising: providing a substrate having a first surface and a second surface; forming a first via connecting the first surface and the second surface in the substrate; filling a conductive material in the first through hole to form a first conductive through hole; and bonding an optoelectronic component on the first surface and electrically connected to the first conductive via.

Drawings

Aspects of the present disclosure may be readily understood by the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A illustrates a cross-sectional view of an optoelectronic package, according to some embodiments of the present disclosure.

Figure 1B illustrates a cross-sectional view of an optoelectronic package, according to some embodiments of the present disclosure.

Figure 1C illustrates a cross-sectional view of an optoelectronic package, according to some embodiments of the present disclosure.

FIG. 2 illustrates a top view of an optoelectronic package according to some embodiments of the present disclosure.

Fig. 3 illustrates a cross-sectional view of a Photonic Integrated Circuit (PIC) in accordance with some embodiments of the present disclosure.

Fig. 4 illustrates a cross-sectional view of a PIC according to some embodiments of the present disclosure.

Fig. 5 shows a top view of a PIC according to the PIC in fig. 4.

Fig. 6 illustrates a cross-sectional view of a PIC according to some embodiments of the present disclosure.

Fig. 7A-7F illustrate cross-sectional views of an intermediate product during various manufacturing operations of an optoelectronic package according to some embodiments of the present disclosure.

Fig. 8A-8D illustrate cross-sectional views of a PIC during various manufacturing operations, in accordance with some embodiments of the present disclosure.

Detailed Description

Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like components. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

Spatial descriptions such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," and the like are given with respect to an orientation of a component or a group of components or a plane of a group of components with respect to the component or components, as shown in the associated drawings. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner without departing from the advantages of the embodiments of the present disclosure.

The present disclosure provides a substrate having at least one conductive via to be integrated with a laser die to form an optoelectronic package. The optoelectronic package is then integrated into a PIC carrier. The laser die is bonded to a first surface of the substrate and electrical connections of the laser die are accessible through conductive vias through a second surface opposite the first surface of the substrate. The optoelectronic package is then connected to the PIC carrier by: the laser die is embedded in the filled trench of the PIC carrier and forms an electrical connection between the second surface of the substrate and the PIC carrier.

By having the package structure described in this disclosure, the laser die can be integrated in a face down manner while performing active alignment. Furthermore, electrical access to the laser die is routed to a second surface of the substrate on the opposite side of the active surface of the laser die, thereby reducing routing complexity in conventional approaches. Conductive vias and electrical routing on the substrate may provide additional thermal pathways for the laser die to dissipate heat. In addition, the laser die is embedded in the filled trench of the PIC carrier. Because the laser die is surrounded by the curable material in the filled trench, the laser die can be better protected from the environment.

Referring to fig. 1A, fig. 1A illustrates a cross-sectional view of an optoelectronic package 10A, in accordance with some embodiments of the present disclosure. In FIG. 1A, an optoelectronic package 10A includes a substrate 100 and an optoelectronic assembly 101 stacked over the substrate 100. In some embodiments, the substrate 100 may be composed of a suitable material that allows for the formation of vias. For example, the substrate 100 may be a silicon substrate. The substrate 100 has a first surface 100A and a second surface 100B opposite the first surface 100A. The via 103A connects the first surface 100A and the second surface 100B to achieve electrical connection between components on the two surfaces. In some embodiments, more than one via may be formed in the substrate 100 of the optoelectronic package 10A to enable electrical connection between components on both surfaces.

Conductive patterns 1051 and 1052 are formed over the first surface 100A of the substrate 100 to electrically couple electrodes of the optoelectronic element 101 to at least one of the vias 103A and 103B. Referring to fig. 1A and 2, the conductive patterns 1051 and 1052 may be electrically separated from a top view. The conductive pattern 1051 may be in contact with the conductive bump 107 and the optoelectronic element 101, while the conductive pattern 1052 may be separated from the conductive bump 107 and the optoelectronic element 101. The electrical coupling between the optoelectronic element 101 and the electrically conductive pattern 1052 may be achieved by other means, such as wire bonding. In some embodiments, conductive patterns 1051 and 1052 may be Under Bump Metal (UBM) structures that include one or more conductive patterns.

In some embodiments, via 103A includes a conductive portion 103A1 and an insulating portion 103A 2. Conductive portion 103a1 is electrically connected to conductive pattern 1051. The insulating portion 103A2 fills the remaining portion of the space in the open trench of the via 103A. As shown in fig. 1A, conductive portion 103a1 and insulating portion 103a2 share a coplanar surface adjacent first surface 100A and in contact with conductive pattern 1051. The conductive portion 103a1 covers a side portion of the insulating portion 103a2 adjacent to the second surface 100B and forms a conductive pattern 105B over the second surface 100B. The conductive portion 103a1 exposes a central portion of the insulating portion 103a2 adjacent to the second surface 100B. In some embodiments, the conductive patterns 105B on the second surface 100B may include a redistribution layer (RDL).

In some embodiments, via 103B includes a conductive portion 103B1 and an insulating portion 103B 2. The conductive portion 103B is electrically connected to the conductive pattern 1052. The insulating portion 103B2 fills the remaining portion of the space in the open trench of the via 103B. As shown in fig. 1A, conductive portion 103B1 and insulating portion 103B2 share a coplanar surface adjacent first surface 100A and in contact with conductive pattern 1052. The conductive portion 103B1 covers a side portion of the insulating portion 103B2 adjacent to the second surface 100B and forms a conductive pattern 105B over the second surface 100B. The conductive portion 103B1 exposes a central portion of the insulating portion 103B2 adjacent to the second surface 100B. In some embodiments, the conductive patterns 105B on the second surface 100B may include a redistribution layer (RDL).

In some embodiments, optoelectronic element 101 is stacked over first surface 100A by conductive bump 107/107'. In some embodiments, conductive bump 107/107' comprises an AuSn solder bump. In some embodiments, conductive bump 107/107 'includes AuSn solder layer 107 and gold layer 107'. However, other suitable conductive materials may be applied in the present disclosure and act as a conductive medium between the optoelectronic component 101 and the via 103A. Referring to fig. 1A and 2, the area of the conductive bump 107/107' may be larger than the area of the optoelectronic element 101 from a top view perspective. In some embodiments, the area of the conductive bump 107/107' may be substantially equal to the area of the optoelectronic element 101 from a top view perspective. In some embodiments, the via 103A does not overlap with the projection of the optoelectronic component 101, alternatively, the via 103A does not overlap with the projection of the conductive bump 107/107'. During the manufacturing operation as illustrated in fig. 7F, the conductive bump is transformed into a molten state by performing a laser heating operation irradiated from the second surface 100B of the substrate 100. The laser light applied in such an operation is transparent to the silicon substrate, and thus it is impossible to place other materials that can absorb the energy of the applied laser light on the laser light propagation path in the substrate 100. In order to allow laser light to enter the substrate 100 from the second surface 100B and leave the substrate from the first surface 100A, anti-reflection coatings 102B and 102A may be formed on the second surface 100B and the first surface 100A, respectively.

In some embodiments, the optoelectronic component 101 is an edge emitting laser. The first electrode 101A is adjacent the bottom of the optoelectronic component 101 and is electrically coupled to the conductive pattern 1051 by conductive bumps 107'/107. The second electrode 101B is adjacent the top of the optoelectronic element 101 and is electrically coupled to the conductive pattern 1052 by a bond wire 111. The conductive pattern 1051 further transfers electrical signals from the first surface 100A to the second surface 100B of the substrate 100 through the conductive portion 103A1 of the via 103A. Similarly, the conductive pattern 1052 further transfers the electrical signal from the first surface 100A to the second surface 100B of the substrate 100 through the conductive portion 103B1 of the via 103B.

FIG. 1B illustrates a cross-sectional view of an optoelectronic package 10B, according to some embodiments of the present disclosure. The optoelectronic package 10B is similar to the optoelectronic package 10A except that the structure of the via 103A in fig. 1B is different from the structure of the via 103A in fig. 1A. As shown in fig. 1B, the via 103A includes a conductive portion 103A1 and an insulating portion 103A 2. Conductive portion 103a1 is electrically connected to conductive pattern 1051. The insulating portion 103A2 fills the remaining portion of the space in the open trench of the via 103A. As shown in fig. 1B, conductive portion 103a1 and insulating portion 103a2 share a coplanar surface adjacent to first surface 100A and in contact with conductive pattern 1051. The conductive portion 103a1 covers a side portion of the insulating portion 103a2 adjacent to the second surface 100B and forms a conductive pattern 105B over the second surface 100B. The central portion of the via 103A is filled with the conductive portion 103A 1. The via 103A in fig. 1B provides a better heat dissipation channel and lower resistance than the via in fig. 1A, and thus can be applied to an optoelectronic package requiring superior heat dissipation and better electrical connection.

Figure 1C illustrates a cross-sectional view of an optoelectronic package 10C, in accordance with some embodiments of the present disclosure. Optoelectronic package 10C is similar to optoelectronic package 10B except that optoelectronic component 101 is electrically connected to conductive pattern 1052 through conductive bumps 107/107' rather than bond wires. As shown in fig. 1C, both the first electrode 101A and the second electrode 101B are located at the bottom of the optoelectronic element 101 (e.g., an edge-emitting laser diode). The optoelectronic element 101 is arranged to be disposed across adjacent conductive patterns 1051 and 1052, connecting the first electrode 101A to the conductive pattern 1051 via a first conductive bump 107/107 'and connecting the electrode 101B to the conductive pattern 1052 via a second conductive bump 107/107'. Similar to the previous description, the first conductive bump 107/107 'and the second conductive bump 107/107' do not overlap with any of the vias 103A and 103B.

FIG. 2 illustrates a top view of an optoelectronic package according to some embodiments of the present disclosure. Referring to fig. 1A and 2, the optoelectronic element 101 is bonded or electrically connected to the conductive pattern 1051 over the first surface 100A of the substrate 100. The conductive pattern 1052 is separated from the conductive pattern 1051 and is electrically connected to the optoelectronic element 101 by other connecting means such as a bonding wire. In some embodiments as shown in fig. 1C, the optoelectronic element 101 spans the space between the conductive patterns 1051 and 1052, connecting to each of the conductive patterns 1051 and 1052 through two separate conductive bumps.

Fig. 3 illustrates a cross-sectional view of a Photonic Integrated Circuit (PIC)30 in accordance with some embodiments of the present disclosure. PIC 30 includes a carrier 30 having an upper surface 300A that receives optoelectronic package 10A. The carrier 30 has filled trenches 301 open at the upper surface 300A. In some embodiments, the filled trench 301 is filled with a polymer material, such as UV glue, that is transparent to the electromagnetic signals emitted from the optoelectronic element 101. The UV glue solidifies after the UV treatment and provides mechanical support to the optoelectronic package 10A. The cured polymer material in the filled trench 301 has an upper surface that is substantially coplanar with the upper surface 300A of the carrier 300. PIC 30 further includes a waveguide 303 adjacent to filled trench 301 and adjacent to upper surface 300A. In some embodiments, the waveguide 303 is embedded or at least partially embedded in the carrier 300. The waveguide 303 is laterally aligned with the optoelectronic component 101 of the optoelectronic package 10A. In other words, when the optoelectronic component 101 (e.g., an edge-emitting laser diode) emits a laser beam from the left edge (dashed line), the laser beam then enters the waveguide 303 according to a lateral alignment arrangement.

Like reference numerals in the optoelectronic package 10A of fig. 3 correspond to substantially equivalent components in the optoelectronic package of fig. 1A and may be referred to therewith. The conductive portion 103a1 electrically connected to the conductive pattern 1051 covers a side portion of the insulating portion 103a2 adjacent to the second surface 100B and forms a conductive pattern 105B over the second surface 100B. The conductive portion 103a1 exposes a central portion of the insulating portion 103a2 adjacent to the second surface 100B. In some embodiments, the conductive patterns 105B on the second surface 100B may include a redistribution layer (RDL). The conductive pattern 105B is further connected to a conductive pad 305A on the upper surface 300A of the carrier 300 by a conductive via (e.g., a bond wire 302A). Similarly, the conductive portion 103B1 electrically connected to the conductive pattern 1052 covers a side portion of the insulating portion 103B2 adjacent to the second surface 100B and forms a conductive pattern 105B over the second surface 100B. The conductive portion 103B1 exposes a central portion of the insulating portion 103B2 adjacent to the second surface 100B. In some embodiments, the conductive patterns 105B on the second surface 100B may include a redistribution layer (RDL). The conductive pattern 105B is further connected to conductive pads 305B on the upper surface 300A of the carrier 300 by conductive vias (e.g., bond wires 302B). As shown in fig. 3, conductive pattern 1051 is electrically connected to conductive portion 103A1 of via 103A, and conductive pattern 1052 is electrically connected to conductive portion 103B1 of via 103B.

Fig. 4 illustrates a cross-sectional view of the PIC 40, in accordance with some embodiments of the present disclosure. PIC 40 is similar to PIC 30 except that optical elements may optionally be disposed in the filled trench 301 between the optoelectronic package 10A and the waveguide 303. In some embodiments, the optical element includes a lens 401 and a rotator 403. The optical element may be fixed in the cured polymer material and positioned in the path of the beam emitted from the optoelectronic component 101. In some embodiments, the bottom of the optical component may or may not contact the bottom of the filled trench 301, as the cured polymer material may provide mechanical support to the optical element.

Fig. 5 shows a top view of a PIC according to PIC 40 in fig. 4. Referring to fig. 4 and 5, contact pads 305A on the upper surface 300A of carrier 300 may be electrically coupled to conductive patterns 105B and conductive patterns 1051 of optoelectronic package 10A by bond wires 302A. Similarly, conductive pads 305B on the upper surface 300A of the carrier 300 are electrically coupled to the conductive pattern 105B and the conductive pattern 1052 of the optoelectronic package 10A by bonding wires 302B. In some embodiments, a first portion of the optoelectronic package 10A adjacent to the via 103A is stacked on the upper surface 300A of the carrier 300. A second portion of the optoelectronic assembly 101 and the adjacent via 103B of the optoelectronic package 10B are stacked on the upper surface 300A of the filled trench 301. Optionally, a lens 401 and rotator 403 are disposed between the waveguide 303 and the optoelectronic package 10A.

Fig. 6 illustrates a cross-sectional view of a PIC 60 in accordance with some embodiments of the present disclosure. The optoelectronic package 10B is mounted on a Printed Circuit Board (PCB)600 by flip-chip bonding. Conductive portion 103A1 of via 103A is connected to contact pad 600A on the PCB by solder bump 1053 or its equivalent, and conductive portion 103B1 of via 103B is connected to contact pad 600B by solder bump 1053 or its equivalent. Contact pad 600A is electrically coupled to first electrode 101A through a conductive path including solder bump 1053, conductive portion 1031A of via 103A, conductive pattern 1051, and conductive bump 107/107'. Similarly, contact pad 600B is electrically coupled to second electrode 101B through a conductive path that includes solder bump 1053, conductive portion 1031B of via 103B, conductive pattern 1052, and bond wire 302B. Heat generated by the optoelectronic element 101 may be efficiently dissipated from the conductive portions 103A1 and 103B1 of the vias 103A, 103B, respectively.

As shown in fig. 6, the optoelectronic assembly 101 is disposed on the first surface 100A of the substrate 100 so as to be laterally aligned with the optical element 605 by connection of the optical fiber 603. Optical element 605 is disposed on substrate 601 of PCB 600 so as to be laterally aligned with optoelectronic component 101. An optical switch 607 may be disposed on substrate 601 and aligned with optical element 605 via an optical fiber 603 connection. In some embodiments, the thickness of the substrate is designed in consideration of the thickness of the optoelectronic package 10B.

Fig. 7A-7F illustrate cross-sectional views of an optoelectronic package during various fabrication operations, according to some embodiments of the present disclosure. In fig. 7A, the substrate 100 has a first surface 100A and a second surface 100B opposite the first surface 100A. In fig. 7B, anti-reflection coatings 102A and 102B are formed over the first surface 100A and the second surface 100B by a suitable operation. In fig. 7C, conductive patterns 1051 and 1052 are formed on the first surface 100A by blanket deposition of a conductive layer, followed by a photolithographic operation for patterning such conductive layer. Referring back to fig. 2, after the photolithography operation, the conductive patterns 1051 and 1052 may be two discrete conductive patterns. In some embodiments, conductive patterns 1051 and 1052 are Under Bump Metal (UBM) structures. A conductive bump 107/107' is formed on at least one of the conductive patterns 1051 and 1052. Conductive bump 107/107 'may include AuSn solder layer 107 and gold layer 107'. The method of forming the conductive bump 107/107' includes an electroplating or electroless plating operation.

In fig. 7D, at least one via is formed in the substrate 100. For example, via trenches are formed by performing Deep Reactive Ion Etching (DRIE) until conductive pattern 1051 and/or conductive pattern 1052 are exposed. Subsequently, a passivation material is deposited in the via trench, forming a liner on the sidewalls and bottom of the via trench. Then, the passivation material at the bottom of the via trench is removed by a photolithography operation to expose the conductive patterns 1051 and/or 1052, thereby forming the insulating portions 103a2 and/or 103B 2. Then, a conductive material is deposited in the via trench, thereby forming a liner on the sidewalls of the insulating portions 103a2 and/or 103B2 and the bottom of the via trench. The conductive material contacts the previously exposed conductive patterns 1051 and/or 1052. The conductive material extends over the second surface 100B of the substrate 100 forming a second conductive pattern 105B or redistribution layer (RDL). Subsequently, a passivation material is deposited again in the via trench so as to fill the remaining space of the via trench, thereby forming insulating portions 103a2 and/or 103B2 surrounded by conductive portions 103a1 and/or 103B1, respectively.

In fig. 7E, optoelectronic element 101 is bonded to substrate 100 through conductive bump 107/107' on first surface 100A of substrate 100. The laser heating operation is performed by irradiating the laser beam 701 from the second surface 100B of the substrate 100. Due to the pre-formed anti-reflection coating 102B, the laser beam enters the substrate 100 with minimal reflection. The laser traverses the thickness of the substrate 100 without substantial attenuation because the material of the substrate (e.g., silicon) is transparent to the laser energy. Then, the laser reaches the AuSn alloy layer, thereby melting the eutectic AuSn alloy, and when the laser is turned off, the AuSn alloy solidifies and the bonding operation is completed. Since the laser beam 701 must traverse the thickness direction of the substrate 100 and reach the AuSn alloy layer, any of the vias 103A and 103B does not overlap with a projection of the AuSn alloy layer or a portion of the conductive bump 107/107'.

In FIG. 7F, a bond wire 111 is formed to connect a first electrode (not shown in FIG. 7F) of the optoelectronic package with the conductive pattern 1052 and the via 103B.

Fig. 8A-8D illustrate cross-sectional views of a PIC during various fabrication operations, according to some embodiments of the present disclosure. In fig. 8A, a carrier 300 having an upper surface 300A is provided. The waveguide 303 is embedded or partially embedded in the carrier 300 and adjacent to the upper surface 300A. In fig. 8B, trenches 301' are formed from the upper surface 300A of the carrier 300. In fig. 8C, a curable polymer material (e.g., UV glue) is filled into the trench 301' until the upper surface of the polymer material is substantially coplanar with the upper surface 300A of the carrier 300. In fig. 8D, optoelectronic package 10A is partially disposed over upper surface 300A of carrier 300 prior to curing the polymer material in which optoelectronic element 101 is embedded. In some embodiments, an active alignment operation is performed to align the optoelectronic device 101 with the waveguide 303, and then the polymer material is cured in the filled trench 301. Subsequently, connections between the via 103A and the conductive pad 305A and between the via 103B and the conductive pad 305B are subsequently formed by, for example, a wire bonding operation. In some embodiments, bond wire 302A connects a redistribution layer on optoelectronic package 10A to contact pad 305A, and bond wire 302B connects an RDL on optoelectronic package 10A to contact pad 305B.

As used herein, and not otherwise defined, the terms "substantially", "about" and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms can encompass an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can encompass variations that are less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. The term "substantially coplanar" may mean that the two surfaces are positioned along the same plane with a positional difference within a few microns, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm.

As used herein, the singular forms "a" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, another component disposed "on" or "over" a component may encompass both the case where the preceding component is directly on (e.g., in physical contact with) the subsequent component, as well as the case where one or more intervening components are positioned between the preceding and subsequent components.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and drawings are not to be considered in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the disclosure as defined by the claims. The illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be a distinction between artistic renditions in this disclosure and actual devices. There may be other embodiments of the disclosure that are not specifically shown. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or rearranged to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless explicitly indicated otherwise herein, the order and grouping of the operations is not a limitation.