阅读说明：本技术 集成式trx开关的设计原理和技术 (Design principles and techniques for integrated TRX switches ) 是由 摩尔特萨·阿巴西 T·卡纳尔 N·K·彦杜鲁 于 2020-08-28 设计创作，主要内容包括：本公开涉及一种集成式TRX开关。该集成式TRX开关包括收发器电路、串联电容器和并联开关。收发器电路可以包括发送链和接收链,发送链包括输出匹配网络,接收链包括输入匹配网络。输出匹配网络的输出可以直接连接至收发器电路的输入/输出。串联电容器可以连接在输入匹配网络的输入与输出匹配网络的输出之间。并联开关可以连接在输入匹配网络的输入与收发器电路的电路接地电位之间。(The present disclosure relates to an integrated TRX switch. The integrated TRX switch includes a transceiver circuit, a series capacitor, and a parallel switch. The transceiver circuit may include a transmit chain including an output matching network and a receive chain including an input matching network. The output of the output matching network may be directly connected to the input/output of the transceiver circuit. The series capacitor may be connected between an input of the input matching network and an output of the output matching network. The parallel switch may be connected between an input of the input matching network and a circuit ground potential of the transceiver circuit.)

1. An apparatus, comprising:

a transceiver circuit;

a series capacitor; and

a parallel switch, wherein (i) the transceiver circuit comprises a transmit chain comprising an output matching network and a receive chain comprising an input matching network, (ii) an output of the output matching network is directly connected to an input/output of the transceiver circuit, (iii) the series capacitor is connected between an input of the input matching network and the output of the output matching network, and (iv) the parallel switch is connected between the input of the input matching network and a circuit ground potential of the transceiver circuit.

2. The apparatus of claim 1, wherein the output matching network comprises a first transformer and the input matching network comprises a second transformer.

3. The apparatus of claim 1, wherein the output matching network comprises a first radio frequency choke/inductor and the input matching network comprises a second radio frequency choke/inductor.

4. The apparatus of claim 1, wherein the input/output of the transceiver circuit is connected to at least one of an antenna element and a transmission line.

5. The apparatus of claim 4, wherein the antenna element is one of a plurality of antenna elements that make up a phased array antenna.

6. The apparatus of claim 5, wherein the transceiver circuit, the series capacitor, and the parallel switch are part of a beamformer integrated circuit.

7. The apparatus of claim 6, wherein the beamformer integrated circuit comprises a plurality of transceiver circuits, each transceiver circuit comprising a respective series capacitor and a respective parallel switch.

8. The apparatus of claim 1, further comprising a shunt capacitor connected in parallel with the shunt switch.

9. The apparatus of claim 8, wherein the transceiver circuit, the series capacitor, the parallel capacitor, and the parallel switch are part of an integrated circuit.

10. The apparatus of claim 1, wherein the parallel switch comprises one or more transistors.

11. The apparatus of claim 10, wherein the parallel switch comprises stacked transistor devices.

12. The apparatus of claim 10, wherein the transistor is implemented using at least one of the following technologies: complementary Metal Oxide Semiconductor (CMOS) technology, High Electron Mobility Transistor (HEMT) technology, pseudomorphic high electron mobility transistor (pHEMT) technology, and silicon-on-insulator technology.

13. The apparatus of claim 10, wherein the transistor is a low voltage sub-micron transistor technology with a low breakdown voltage.

14. The apparatus of claim 1, wherein the series capacitor and the parallel switch are implemented within a footprint of the input matching network and the output matching network of the transceiver circuit.

15. The apparatus of claim 1, wherein the transceiver circuit, the series capacitor, and the parallel switch are implemented on at least one of an integrated circuit and a printed circuit board.

16. The apparatus of claim 1, wherein:

each of the matching networks includes at least one of: inductors, RF chokes, transformers, planar spiral transmission lines, and planar coupled spiral transmission lines; and is

The series capacitor includes at least one of a metal-insulator-metal capacitor, a finger capacitor, and a ceramic capacitor.

17. A method for switching a transmission medium between a transmitter channel and a receiver channel of a transceiver, the method comprising the steps of:

connecting an output of an output matching network of a transmit chain of the transceiver directly to an input/output of the transceiver;

connecting a series capacitor between an input of an input matching network and the output of the output matching network of a receive chain of the transceiver; and

connecting a parallel switch between the input of the input matching network and a circuit ground potential of the transceiver.

18. The method of claim 17, further comprising connecting a parallel capacitor in parallel with the parallel switch.

19. The method of claim 18, wherein a value of the parallel capacitor is selected to adjust an impedance presented to an input of the receive chain to improve noise behavior.

20. The method of claim 19, wherein the value of the parallel capacitor is selected taking into account a parasitic capacitance of the parallel switch.

Technical Field

The present invention relates generally to transceiver circuits, and more particularly, to methods and/or apparatus for implementing an integrated transmit-receive (TRX) switch.

Background

The implementation of a conventional high isolation transmit-receive (TRX) switch increases chip area and increases: (i) loss at the output of the transmit chain (i.e., return loss, insertion loss, or power loss); and (ii) losses at the input of the receive chain (i.e., noise figure, additional losses, and noise). Conventional high isolation TRX switches require active technology capable of withstanding high voltages, which limits the linearity of the transmit chain.

It is desirable to implement an integrated transmit-receive (TRX) switch without affecting the performance of the transmit and receive chains.

Disclosure of Invention

The invention relates to an arrangement comprising a transceiver circuit, a series capacitor and a parallel switch. The transceiver circuit may include a transmit chain including an output matching network and a receive chain including an input matching network. The output of the output matching network may be directly connected to the input/output of the transceiver circuit. The series capacitor may be connected between an input of the input matching network and an output of the output matching network. The parallel switch may be connected between an input of the input matching network and a circuit ground potential of the transceiver circuit.

Drawings

Embodiments of the invention will become apparent from the following detailed description, the appended claims and the accompanying drawings,

wherein:

fig. 1 is a transceiver circuit diagram illustrating in an exemplary context of the invention.

Fig. 2 is a diagram of a phased array antenna system illustrating another exemplary context of the present invention.

Fig. 3 is a diagram illustrating an example implementation of a single-polarized phased array antenna panel according to an example embodiment of the invention.

Fig. 4 is a diagram illustrating an example implementation of a dual polarized phased array antenna panel according to an example embodiment of the invention.

Fig. 5 is a circuit diagram of a single-polarized beamformer according to an exemplary embodiment of the present invention.

Fig. 6 is a circuit diagram of a dual polarization beamformer according to an exemplary embodiment of the present invention.

Fig. 7 is a block diagram illustrating an example implementation of the transceiver circuit in fig. 5 and 6.

Fig. 8 is a diagram illustrating an example implementation of a transmit-receive (TRX) switch topology according to a differential embodiment.

Fig. 9 is a diagram illustrating another example implementation of a TRX switch topology according to a single-ended embodiment.

Fig. 10 is a diagram illustrating yet another example implementation of a TRX switch topology according to a single-ended embodiment.

Fig. 11 is a diagram illustrating yet another example implementation of a TRX switch topology according to a differential embodiment.

Fig. 12 is a simulated voltage waveform diagram illustrating the TRX switch topology in fig. 11.

Detailed Description

Embodiments of the invention include providing an integrated transmit-receive (TRX) switch that may: (i) combining the output and input impedance matching networks of the transceiver circuit with additional series and parallel capacitors to achieve a high isolation switch; (ii) is used in differential applications; (iii) is used for single-ended applications; (iv) eliminating the need for high breakdown devices in the TRX switch; (v) is suitable for being realized in advanced low-voltage submicron transistor technology; (vi) an impedance matching element incorporated into the power amplifier and/or the low noise amplifier; (vii) the chip area is reduced; (viii) used in transformer-based transmitter and receiver implementations; (ix) suitable for implementation in short channel body or silicon-on-insulator (SOI) CMOS technology with low breakdown voltage; (x) Providing high isolation between Transmit (TX) and Receive (RX) circuitry; (xi) Designed independently of TX and RX circuitry; (xii) Can be incorporated into a corresponding impedance matching network at any stage of development without the need for co-design or co-optimization; and/or (xiii) to any transceiver that must operate in transmit and receive modes at different times and that requires isolation between the two.

Referring to fig. 1, there is shown a block diagram of a circuit 10 illustrating an exemplary context in which a transmit-receive (TRX) switch according to an exemplary embodiment of the present invention may be implemented. In an example embodiment, the circuit 10 may implement a transceiver circuit. The transceiver is generally capable of transmitting and receiving signals of a communication channel. In various embodiments, circuitry 10 may be capable of transmitting and receiving Radio Frequency (RF), microwave, and/or millimeter wave signals. In various embodiments, circuit 10 may represent a transceiver circuit utilized in applications including, but not limited to: cellular base stations (e.g., 2G, 3G, 4G, 5G, etc.), wireless communication systems, Wireless Local Area Networks (WLANs), wireless backhaul channels, broadband repeaters, Community Antenna Television (CATV) networks, macrocells, microcells, picocells, femtocells, Mobile Devices (MDs), and/or portable handheld devices (UEs). In some embodiments, circuit 10 may represent a radar application including, but not limited to, target detection, ranging, and/or through-wall imaging.

In an example, the transceiver circuit 10 generally includes a transmit chain and a receive chain. Both the transmit chain and the receive chain may include Radio Frequency (RF) amplifiers. In an example, the transmit chain may include an input amplifier 12, a variable phase shifter 14, a variable attenuator 16, and one or more output amplifier stages 18. In an example, the input amplifier 12 may be implemented as a low noise amplifier (LMA). The output amplifier stage 18 may include a driver, a preamplifier, and/or a power amplifier. In an example, the receive chain may include an input amplifier 20, a variable phase shifter 22, and a variable attenuator 24. Input amplifier 20 may be implemented as a Low Noise Amplifier (LNA). In an example, the output of a transmit chain and the input of a receive chain may be coupled to a transmission line or an antenna by an integrated transmit-receive (TRX) switch 100 implemented according to an embodiment of the invention. In various embodiments, the integrated TRX switch 100 may combine the output and input impedance matching networks of the transceiver circuit with additional series and parallel capacitors to achieve high isolation switching. The topology of the integrated TRX switch 100 can be applied to both differential and single-ended applications. The integrated TRX switch 100 generally eliminates the need for high breakdown devices in high isolation TRX switches. The integrated TRX switch 100 is generally applicable to any transceiver that must operate in transmit and receive modes at different times and require isolation between the two.

Referring to FIG. 2, a block diagram of a system 80 is shown that illustrates another example context of the invention. System (or module or circuit or device) 80 may implement a Radio Frequency (RF) transceiver system in accordance with an example embodiment of the present invention. The RF transceiver system 80 may be configured to operate at common radio frequencies, millimeter wave frequencies, and/or microwave frequencies. In an example, the RF transceiver system 80 may be configured to facilitate communication with and/or between a plurality of communication devices (or terminals) 90a-90 n. In an example, the communication devices 90a-90n may include, but are not limited to: cellular phones, mobile devices, tablets, internet of things (IoT) devices, and the like. In various embodiments, the RF transceiver system 80 and the communication devices 90a-90n may be coupled using at least one phased array antenna panel 92. The phased array antenna panel 92 may include a plurality of antenna elements and a plurality of beamformer circuits (or chips), which are described below in connection with fig. 3-7. According to an example embodiment of the invention, the beamformer circuit may include an integrated transmit-receive (TRX) switch 100.

In an example, the RF transceiver system 80 may form part of a communication link. In some embodiments, the communication link may be part of a fifth generation (5G) wireless communication system (e.g., for which the next generation mobile Network (NGMM) consortium is currently developing standards). In other embodiments, the communication link may be part of a system including, but not limited to: fourth generation (4G) wireless communication systems (e.g., international mobile telecommunications advanced (IMT-a) standards promulgated by the international telecommunication union radio communication sector (ITU-R)), satellite communication (SATCOM) systems, and point-to-point communication systems such as the Common Data Link (CDL). However, other communication standards may be implemented to meet the design criteria of a particular application.

In an example, the RF transceiver system 80 may include a block (or circuit) 82, a block (or circuit) 84, a block (or circuit) 86, and a block (or circuit) 88. In various embodiments, blocks 82-88 may be implemented using hardware, a combination of hardware and software, and/or simulated using software. Signals (e.g., IF) may be exchanged between circuitry 82 and circuitry 84. The signal IF may implement an intermediate frequency signal. In an example, the signal IF may be configured (e.g., using various modulation schemes) to carry information to be transmitted from the RF transceiver system 80 and/or received by the RF transceiver system 80. In an example, a signal (e.g., LO) may be presented to circuitry 84. The signal LO may implement a local oscillator signal. Signals (e.g., RF) may be exchanged between the circuitry 84 and the phased array antenna panel 92. The signal RF, which may be a radio frequency, millimeter wave frequency or microwave frequency signal, conveys information that is also found in the intermediate frequency signal IF.

In transmit mode, radio frequency signals RF may convey information to be broadcast from the phased array antenna panel 92 to the devices 90a-90 n. In the receive mode, radio frequency signals RF may communicate information received from devices 90a-90n via phased array antenna panel 92. Signals (e.g., FSW) and one or more signals (e.g., CTRL) may be exchanged between circuitry 86 and phased array antenna panel 92. Signal FSW may switch phased array antenna panel 92 between transmit and receive modes. Signal CTRL may convey data, timing, and control elements. In an example, signals FSW and CTRL may be part of a digital interface of phased array antenna panel 92. In an example, the signal CTRL may be implemented as a serial link that conveys information for configuring and/or determining phase and/or gain settings for the antenna elements of the phased array antenna panel 92. In an example, the signal(s) CTRL may conform to one or more serial communication protocols or interfaces (e.g., Serial Peripheral Interface (SPI), inter-integrated circuit communication (I2C), daisy-chain, etc.). One or more signals (e.g., PG) may be transmitted from circuitry 88 to circuitry 86. In an example, signal(s) PG may communicate phase information and gain information used by circuitry 86 to implement (control) beam steering using phased array antenna panel 92. In an example, signal PG may convey a plurality of phase and gain values that may be programmed into a plurality of beamformer circuits of the phased array antenna panel 92 via signal(s) CTRL.

The phased array antenna panel 92 typically implements a hardwired address scheme. A hardwired address scheme may be used to uniquely identify serial communications intended for elements (e.g., beamformer circuits) of the phased array antenna panel 92. In various embodiments, multiple phased array antenna panels 92 may be combined to form a larger antenna array, which may provide more transmission channels. The multiple phased array antenna panels 92 may share a serial communication channel, link, or bus. Each phased array antenna panel 92 comprising a larger antenna array may be uniquely addressed using a corresponding hard-wired address.

The phased array antenna panel 92 may generate one or more fields (or beams) 102a-102 n. Fields 102a-102n may represent field patterns (or radio frequency beam patterns) created by the beamformer circuits of phased array antenna panel 92 based on the phase and gain information (values) received via signal(s) CTRL. The phased array antenna panel 92 may be configured to generate directional beams 102a-102n for communicating with the communication devices 90a-90 n. In an example, the beamformer circuits of the phased array antenna panel 92 may be controlled to control the beams 102a-102n to track movement of the communication devices 90a-90n and/or to switch between the communication devices 90a-90n based on phase and gain information received via the signal(s) CTRL.

Circuitry 82 may implement baseband processor circuitry. The circuit 82 may be operable to process information transmitted by and/or received in the intermediate frequency signal IF. Circuitry 82 may process information within RF transceiver system 80. The processing may include, but is not limited to: modulate/demodulate signals containing information, and manage simultaneous communications between the RF transceiver system 80 and multiple remote terminals 90a-90 n.

The circuit 84 may implement one or more mixer circuits. Circuitry 84 is generally operable to frequency convert (e.g., upconvert, downconvert, etc.) between an intermediate frequency used for signal IF and a radio, millimeter-wave, or microwave frequency used for signal RF. The frequency conversion may be based on one or more local oscillator frequencies provided by signal LO. In various embodiments, the radio frequency signal RF may be in a frequency range centered about a center frequency of 28 gigahertz (GHz) or 39GHz (e.g., 24GHz to 30GHz or 37GHz to 44 GHz). In embodiments implementing multiple intermediate frequencies, each intermediate frequency may cover a frequency band from about 2GHz to about 6GHz (e.g., about 4GHz bandwidth). In an example, when signal RF is approximately centered at 28GHz, each local oscillator frequency may range from approximately 22GHz to 26 GHz. In another example, when signal RF is centered at about 39GHz, each local oscillator frequency may range from about 33GHz to 37 GHz. However, other frequency ranges may also be implemented to meet the design criteria of a particular application.

The circuit 86 may implement a control circuit. In various embodiments, circuitry 86 may be implemented using one or more of the following: an Application Specific Integrated Circuit (ASIC), a controller, a microprocessor, or a correspondingly configured circuitry. The circuit 86 is generally operable to control the operation of the phased array antenna panel 92. In some embodiments, circuitry 86 may determine settings used in each transceiver channel within the beamformer circuits of phased array antenna panel 92. The settings may establish the geometry of the field(s) or beam(s) 102a-102 n. In various embodiments, circuitry 86 may be implemented as one or more integrated circuits.

In an example, the circuit 88 may implement a table of values (e.g., contained in a memory circuit). In an example, a value table included in circuitry 88 may be configured to store a plurality of gain (G) values and a plurality of phase (P) values. The phase values and gain values may be used by transceiver channels in the beamformer circuits of the phased array antenna panel 92 to establish the fields 102a-102 b. The phase and gain values may be obtained from circuitry 88 via signal PG and programmed by circuitry 86 into buffers associated with the beamformer circuits of phased array antenna panel 92. In various embodiments, circuits 86 and 88 may be implemented on the same integrated circuit or on different (separate) integrated circuits.

In an example, the phased array antenna panel 92 may be implemented to include single polarized (or monopole) antenna elements or dual polarized (or dipole) antenna elements. The phased array antenna panel 92 may be operable to transmit and receive wireless signals to and from the devices (or terminals) 90a-90 n. The devices (or terminals) 90a-90n may be located remotely from the RF transceiver system 80. The sensitivity to wireless signals may be determined by the fields 102a-102n created by the phased array antenna panel 92. The phased array antenna panel 92 may include a plurality of antenna elements and a plurality of beamformer circuits. Each beamformer circuit may implement multiple transceiver channels. Each transceiver channel typically includes a transmit channel (or chain) and a receive channel (or chain). According to embodiments of the present invention, transceiver channels may be coupled to antenna elements through respective matching networks and integrated TRX switches for exchanging corresponding bi-directional radio frequency signals. The transceiver channels and antenna elements typically form a two-dimensional antenna network.

Referring to fig. 3, a diagram illustrating an example implementation of a single polarized version of a phased array antenna panel 92 according to an embodiment of the present invention is shown. In an example, the phased array antenna panel 92 may include a plurality of antenna elements 110, a plurality of beamformer circuits 112a-112m, and a plurality of blocks (or circuits) 114a-114 k. In embodiments implementing a single-polarized phased array antenna panel, the antenna elements 110 are typically implemented as single-polarized (or monopole) antenna elements. Each of the circuits 112a-112m may implement a single polarized beamformer circuit. Each of the circuits 114a-114k may implement a combiner/divider circuit. The circuits 112a-112m and 114a-114k may be implemented using hardware, a combination of hardware and software, and/or simulated using software. In an example, the signal RF may be exchanged with one of the circuits 114a-114 k. Signals FSW and CTRL may be exchanged with circuits 112a-112 m.

The antenna elements 110 in the phased array antenna panel 92 may be used for both transmission and reception. The physical positioning of the antenna elements 110 generally provides two-dimensional (e.g., horizontal and vertical) control of the fields 102a-102 n. In an example, the antenna elements 110 may be arranged in a two-dimensional (e.g., N × M) grid pattern, where N is an integer value divisible by 2. However, other dimensions of the grid pattern may be implemented accordingly to meet the design criteria of a particular implementation. The circuits 112a-112m are generally operable to multiplex/demultiplex the signal RF with the plurality of antenna elements 110. In various embodiments, each of the circuits 112a-112m may be mounted on a substrate of the phased array antenna panel 92 adjacent to (e.g., centered on) a plurality (or set) of antenna elements 110. In an example, each circuit 112a-112m generally includes a plurality of transceiver channels coupled to a respective antenna element 110. In an example, each circuit 112a-112m may be coupled to four adjacent antenna elements 110 (e.g., arranged in a 2 x 2 grid around each circuit 112a-112 m). However, other numbers of adjacent antenna elements 110 (e.g., 1, 2, 4, 18, etc.) may also be implemented to meet the design criteria of a particular implementation.

The circuits 112a-112m may be configured to switch between transmit and receive modes in response to the signal FSW. In the transmit mode, the circuits 112a-112m may be operable to quickly change the settings (e.g., phase values, gain values, etc.) used by the transceiver channels in order to control the beams (or fields) 102a-102n and/or 104a-104n formed by the phased array antenna panel 92. In various embodiments, each of the circuits 112a-112m may include a memory, register storage, and/or a look-up table (LUT) that may be used to store a plurality of phase and gain values for each channel of the circuits 112a-112m, the plurality of phase and gain values corresponding to a plurality of beams in a predetermined beam space. In an example, a plurality of phase and gain values for each channel may be associated with an index corresponding to each beam of the beam space. In various embodiments, each of the circuits 112a-112m may be implemented as one or more integrated circuits (e.g., in a package or multi-chip module (MCM)).

In various embodiments, each of the circuits 114a-114k may be implemented as a combiner/divider circuit. In an example, the circuits 114a-114k may be implemented as Wilkinson combiner/splitters. In various embodiments, the circuits 114a-114k may be coupled together to form a network that couples the circuits 112a-112m to an input/output of the phased array antenna panel 92, the phased array antenna panel 92 being configured to present/receive signals RF. In the transmit mode, the circuits 114a-114k are generally operable to distribute power in the signal RF among the circuits 112a-112 m. In a receive mode, the circuits 114a-114k may be operable to combine power received in signals from the circuits 112a-112m into a signal RF. The circuits 112a-112n and 114a-114k are generally configured to provide substantially equal path lengths between the RF input/output of the phased array antenna panel 92 and each of the circuits 112a-112 m.

Referring to fig. 4, a diagram illustrating an example implementation of a dual polarized phased array antenna panel 94 in accordance with another example embodiment of the present invention is shown. In embodiments implementing dual polarized transceiver channels, phased array antenna panel 94 may be used in place of phased array antenna panel 92 in fig. 1. In an example, the phased array antenna panel 94 may include a plurality of blocks (or circuits) 200a-200m, a plurality of blocks (or circuits) 210, a plurality of blocks (or circuits) 212a-212k, and a plurality of blocks (or circuits) 214a-214 k. In embodiments implementing dual polarized phased array antenna panels, the frame 210 is typically implemented as dual polarized (or dipole) antenna elements. Each of the circuits 200a-200m may implement a dual-polarized beamformer circuit. Each of circuits 212a-212k and 214a-214k may implement a combiner/divider circuit. The circuits 200a-200m, 212a-212k, and 214a-214k may be implemented using hardware, a combination of hardware and software, and/or simulated using software. In embodiments implementing a dual polarized phased array antenna panel 94, the signal RF may include a vertically polarized component (e.g., RFV) and a horizontally polarized component (e.g., RFH). In an example, signal RFV may be exchanged with one of circuits 212a-212k and signal RFH may be exchanged with one of circuits 214a-214 k. Signals FSW and CTRL may be exchanged with circuits 200a-200 m.

The antenna elements 210 in the phased array antenna panel 94 may be used for both transmission and reception. The physical positioning of the antenna elements 210 generally provides two-dimensional (e.g., horizontal and vertical) control of the fields 102a-102 n. In an example, the antenna elements 210 may be arranged in a two-dimensional (e.g., N × M) grid pattern, where N is an integer value that may be divisible by 2. However, other dimensions of the grid pattern may be implemented accordingly to meet the design criteria of a particular implementation.

The circuits 200a-200m are generally operable to multiplex/demultiplex the signals RFV and RFH with the plurality of antenna elements 210. In various embodiments, each of the circuits 200a-200m may be mounted on a substrate of the phased array antenna panel 94 adjacent to a plurality (or set) of antenna elements 210. Each of the circuits 200a-200m may have respective horizontal (H) and vertical (V) inputs/outputs, which may be coupled to corresponding horizontal (H) and vertical (V) inputs/outputs (or feeds) of adjacent antenna elements 210. In an example, each circuit 200a-200m generally includes a plurality of transceiver channels coupled to respective horizontal and vertical input/outputs. In an example, each circuit 200a-200m may be coupled to four adjacent antenna elements 210 (e.g., arranged in a 2 x 2 grid around each circuit 200a-200 m).

The circuits 200a-200m may be configured to switch between a transmit mode and a receive mode in response to the signal FSW. In the transmit mode, the circuits 200a-200m may be operable to quickly change the settings (e.g., phase values, gain values, etc.) used by the transceiver channels in order to control the fields 102a-102n formed by the phased array antenna panel 94. In various embodiments, each of the circuits 200a-200m may include a memory, register storage, and/or a look-up table (LUT) that may be used to store a plurality of phase and gain values for each channel of the circuits 200a-200m, the plurality of phase and gain values corresponding to a plurality of beams in a predetermined beam space. In an example, a plurality of phase and gain values for each channel may be associated with an index corresponding to each beam of the beam space. In various embodiments, each of the circuits 200a-200m may be implemented as one or more integrated circuits (e.g., in a package or a multi-chip module (MCM)). In an example, each of the circuits 200a-200m may be mounted on a substrate of the phased array antenna panel 94 adjacent (e.g., centered) to the respective antenna element 210.

In various embodiments, each of circuits 212a-212k and 214a-214k may implement a combiner/splitter circuit. In an example, each of the circuits 212a-212k and 214a-214k may be implemented as a Wilkinson combiner/splitter circuit. The circuits 212a-212k may be coupled together to form a network that couples the circuits 200a-200m to inputs/outputs of the phased array antenna panel 94, the phased array antenna panel 94 configured to present/receive the signal RFV. The circuits 214a-214k may be coupled together to form a network that couples the circuits 200a-200m to inputs/outputs of the phased array antenna panel 94, the phased array antenna panel 94 configured to present/receive the signal RFH. In the transmit mode, circuits 212a-212k and 214a-214k are generally operable to distribute power in signals RFV and RFH, respectively, between circuits 200a-200 m. In a receive mode, circuits 212a-212k and 214a-214k may be operable to combine the power received in the signals from circuits 200a-200m into signals RFV and RFH, respectively. The circuits 212a-212n, 212a-212k, and 214a-214k are generally configured to provide substantially equal path lengths between the RFV input/output and the RFH input/output of the phased array antenna panel 94 and each of the circuits 200a-200 m.

Referring to fig. 5, a diagram illustrating an example implementation of a single-polarized beamformer circuit 112i according to an example embodiment of the present invention is shown. In an example, the single-polarized beamformer circuit 112i may represent the single-polarized beamformer circuits 112a-112m in fig. 2. In an example, the single-polarized beamformer circuit 112i may have a digital interface configured to receive signal FSW and signal(s) CTRL, a common RF input/output port (RFC), and a plurality of antenna input/output ports (RF 1-RFN). In general, any number (e.g., N) of antenna input/output ports (or channels) may be implemented accordingly to meet the design criteria of a particular implementation.

In various embodiments, the signal RF may be presented/received by a common RF input/output RFC, and the antenna input/output ports RF1-RFN may be coupled to respective antenna elements 110. The single-polarized beamformer circuit 112i typically implements a number of transceiver channels corresponding to the number of antenna input/output ports RF 1-RFN. In various embodiments, each transceiver channel may include a respective transmit channel and a respective receive channel. The transceiver channel is typically configured to switch between transmitting or receiving based on the signal FSW.

The single-polarized beamformer circuit 112i typically implements a transmit mode and a receive mode. In an example, the state of signal FSW may determine whether the transmit mode is active or the receive mode is active. In the transmit mode, the single-polarized beamformer circuit 112i is typically configured to receive radio frequency signals RF at a common input/output port RFC and to present radio frequency signals at antenna input/output ports RF 1-RFN. The signals present at each of the antenna input/output ports RF1-RFN are generated by the single-polarized beamformer circuit 112i in response to the radio frequency signals RF received at the common input/output port RFC and a corresponding number of settings (e.g., gain, phase, etc.) for each transceiver channel corresponding to each of the antenna input/output ports RF 1-RFN. In the receive mode, the single-polarized beamformer circuit 112i is typically configured to combine radio frequency signals received at the antenna input/output ports RF1-RFM for presentation as signal RF at the common input/output port RFC.

The single-polarized beamformer circuit 112i may include a block (or circuit) 302, a block (or circuit) 304, a plurality of blocks (or circuits) 306a-306n, and a block (or circuit) 308. The circuit 302 may implement an interface circuit. In various embodiments, the circuit 302 may implement a digital interface. Circuitry 304 may implement a hardwired address (e.g., chip ID) for beamformer circuit 112 i. Circuits 306a-306n may implement Transceiver (TRX) channels. Circuit 308 may implement a 1-to-N combiner/splitter network.

In the example, signals FSW and CTRL are exchanged with circuit 302. In an example, the circuit 302 may include a serial interface. The circuit 302 may be configured to conform to one or more serial interface standards including, but not limited to: serial Peripheral Interface (SPI), inter-integrated circuit (I2C), daisy chain, etc. In an example, the circuit 302 may be configured to allow for programming and control of the single-polarized beamformer circuit 112i using a serial communication link (or bus). In an example, the circuit 302 may be configured to program and control the circuits 306a-306n in response to the signals CTRL and FSW. In an example, circuit 302 may control whether circuits 306a-306n operate in a transmit mode or a receive mode in response to signal FSW.

In an example, circuitry 302 may implement a 4-wire embedded SPI core. In an example, the circuit 302 may have a first pin that may receive a first signal (e.g., MOSI), a second pin that may present a second signal (e.g., MISO), a clock input pin that may receive a clock signal (e.g., SCLK), and a chip enable (or chip select) pin that may receive a signal (e.g., SS/CS). In an example, the signals MOSI, MISO, SCLK, and SS/CS may be components of the signal(s) CTRL. In an example, the circuit 302 can include a transmit/receive function switch pin that can receive the signal FSW. In an example, the signals MOSI, MISO, SCLK, and SS/CS may be configured to implement a 4-wire SPI protocol interface, as shown in table 1 below:

TABLE 1

Signal	Function(s)
		MOSI	Master-out-from-master-in
MISO	Main in and slave out
		SCLK	Serial clock
SS/CS	From selection/chip selection

In an example, the circuitry 304 may set the physical address of the beamformer circuit 112i based on hardware encoded address bits (or pins). In various embodiments, a hardwired address having multiple (e.g., X) input bits (e.g., ADD1, ADD 2. In an example, the address may be implemented to have six bits (or pins). In some embodiments, the hardwired address may be set to a predetermined logic level (e.g., 0 or 1) by coupling a plurality of address pins to a predetermined power supply voltage (e.g., GND, VSS, or VDD). In some embodiments, the hard-wired address bits may be hard-coded within the chip implementing the beamformer 112 i. In some embodiments, the hardwired address bits are programmable during manufacturing within the chip implementing the beamformer 112 i. In an example, the hardwired address bits may be programmed using fuses, antifuses, or other conventional techniques.

Referring to fig. 6, a diagram illustrating an example implementation of a dual polarized beamformer circuit 200i according to an example embodiment of the present invention is shown. In an example, dual-polarized beamformer circuit 200i may represent dual-polarized beamformer circuits 200a-200m in fig. 3. In an example, dual polarized beamformer circuit 200i may have a digital interface configured to receive signal FSW and signal(s) CTRL, a first common RF input/output port (RFVC), a second common RF input/output port (RFHC), a plurality of vertical antenna input/output ports (RFV1-RFV (n)), and a plurality of horizontal antenna input/output ports (RFH1-RFH (n)). In general, any number (e.g., N) of vertical and horizontal antenna input/output ports (or channels) may be implemented accordingly to meet the design criteria of a particular implementation.

In various embodiments, signal RFV may be presented/received by a common RF input/output RFVC, signal RFH may be presented/received by a common RF input/output RFHC, vertical antenna input/output ports RFV1-RFV (n) may be coupled to corresponding vertical inputs/outputs of respective antenna elements 210, and horizontal antenna input/output ports RFH1-RFH (n) may be coupled to corresponding horizontal inputs/outputs of respective antenna elements 210. The dual polarization beamformer circuit 200i typically implements a number (e.g., N) of transceiver channels corresponding to the number of pairs of vertical and horizontal antenna input/output ports (RFV1, RFH1), (RFV2, RFH2), … (RFV (N), RFH (N)). In various embodiments, each transceiver channel may include a respective transmit channel and a respective receive channel. The transceiver channel is typically configured to switch between transmitting or receiving based on the signal FSW.

The dual polarization beamformer circuit 200ii typically implements a transmit mode and a receive mode. In an example, the state of signal FSW may determine whether the transmit mode is active or the receive mode is active. In transmit mode, the dual polarized beamformer circuits 200i are generally configured to receive radio frequency signals at common input/output ports RFVC and RFHC and to present radio frequency signals at antenna input/output ports RFV1-RFV (N) and RFH1-RFH (N). Signals present at each of the antenna input/output ports RFV1-RFV (m) and RFH1-RFH (n) are generated by dual-polarized beamformer circuit 200i in response to radio frequency signals received at the common input/output ports RFVC and RFHC, and a corresponding number of settings (e.g., gain, phase, etc.) corresponding to each of the antenna input/output ports RFV1-RFV (m) and RFH1-RFH (n).

In an example, dual polarized beamformer circuit 200i may comprise a block (or circuit) 402, a block (or circuit) 404, a plurality of blocks (circuits) 406a-406n, and a block (or circuit) 408. The circuit 402 may implement an interface circuit. In various embodiments, the circuit 402 may implement a digital interface. The circuit 404 may implement a hardwired address (e.g., chip ID) for the beamformer circuit 200 i. The circuits 406a-406n may implement a Transceiver (TRX) channel. The circuit 408 may implement a 1-N dual channel combiner/splitter network.

In an example, signals FSW and CTRL are exchanged with circuit 402. In an example, the circuit 402 may include a serial interface. The circuit 402 may be configured to conform to one or more serial interface standards, including but not limited to: serial Peripheral Interface (SPI), inter-integrated circuit (I2C), daisy-chain, etc. In an example, the circuit 402 may be configured to allow for programming and control of the dual polarized beamformer circuit 200i using a serial communication link (or bus). In an example, the circuit 402 may be configured to program and control the circuits 406a-406n in response to the signals CTRL and FSW. In an example, the circuit 402 may control whether the circuits 406a-406n operate in a transmit mode or a receive mode in response to the signal FSW.

In an example, circuitry 402 may implement a 4-wire embedded SPI core. In an example, the circuit 402 may have a first pin that may receive a first signal (e.g., MOSI), a second pin that may present a second signal (e.g., MISO), a clock input pin that may receive a clock signal (e.g., SCLK), and a chip enable (or chip select) pin that may receive a signal (e.g., SS/CS). In an example, the signals MOSI, MISO, SCLK, and SS/CS may be components of the signal(s) CTRL. In an example, the circuit 402 can include a transmit/receive function switch pin that can receive the signal FSW. In an example, signals MOSI, MISO, SCLK, and SS/CS may be configured to implement a 4-wire SPI protocol interface, as shown above in table 1.

In an example, the circuit 404 may set the physical address of the dual polarization beamformer circuit 200i based on hardware encoded address bits (or pins). In various embodiments, a hardwired address having multiple (e.g., X) input bits (e.g., ADD1, ADD 2. In an example, the address may be implemented to have six bits (or pins). In some embodiments, the hardwired address may be set to a predetermined logic level (e.g., 0 or 1) by coupling a plurality of address pins to a predetermined power supply voltage (e.g., GND, VSS, or VDD). In some embodiments, the hard-wired address bits may be hard-coded during manufacturing, within the chip on which the beamformer 200i is implemented. In some embodiments, the hardwired address bits may be programmed within the chip implementing the beamformer 200 i. In an example, the hard-wired bits may be programmed using fuses, antifuses, or other conventional techniques.

Referring to fig. 7, a block diagram of transceiver circuitry 306i is shown illustrating an example implementation of the transceiver circuitry in fig. 5 and 6. In an example, transceiver circuit 306i may represent single-polarized beamformer transceiver circuits (or channels) 306a-306 d. In another example, transceiver circuitry 306i may represent the horizontal or vertical beamformer transceiver circuitry (or channels) in fig. 6. In an example embodiment, circuitry 306i may include a block (or circuit) 310 and a block (or circuit) 312. In an example embodiment, the circuit 310 may implement a transceiver circuit. Block 312 may implement a transmit-receive (T/R) RF switch. Transceiver circuitry is generally capable of transmitting and receiving signals of a communication channel. In various embodiments, circuitry 310 may be capable of transmitting and receiving Radio Frequency (RF), microwave, and/or millimeter wave signals.

In various embodiments, circuitry 310 may represent transceiver circuitry used in applications including, but not limited to: cellular base stations (e.g., 2G, 3G, 4G, 5G, etc.), wireless communication systems, Wireless Local Area Networks (WLANs), wireless backhaul channels, broadband repeaters, Community Antenna Television (CATV) networks, macrocells, microcells, picocells, femtocells, Mobile Devices (MDs), and/or portable handheld devices (UEs). In some embodiments, circuitry 310 may represent radar applications including, but not limited to, target detection, ranging, and/or through-wall imaging. In an example, the transceiver circuitry 310 generally includes both a transmit chain and a receive chain. Both the transmit chain and the receive chain may include Radio Frequency (RF) amplifiers.

In an example, the transmit chain may include an input amplifier 320, a variable (programmable) phase shifter 322, a variable (programmable) attenuator 324, and one or more output amplifier stages 326. The output of the transmit chain may be coupled to an input of a matching network and integrated transmit-receive (TRX) switch circuit 100 according to an embodiment of the present invention. In an example, the input amplifier 320 may be implemented as a low noise amplifier (LMA). The output amplifier stage 326 may include a driver, a preamplifier, and/or a Power Amplifier (PA). In an example, the receive chain may include a Low Noise Amplifier (LNA)330, a variable (programmable) phase shifter 332, and a variable (programmable) attenuator 334. The output of circuit 100 may be coupled to an input of a Low Noise Amplifier (LNA) 330. In various embodiments, RF switch 312, variable phase shifter 322, variable attenuator 324, variable phase shifter 332, and variable attenuator 334 may be implemented using conventional techniques.

In one example, the input of the transmit chain and the output of the receive chain may be coupled to a transmission line or RF transceiver system through an RF switch 312. In an example, an output of a transmit chain and an input of a receive chain may be coupled to a transmission line or Antenna (ANT) through circuitry 100. In various embodiments, the circuit 100 may implement an output matching network for the transmit chain, an input matching network for the receive chain, and an integrated TRX switch according to embodiments of the present invention. The integrated TRX switch of circuit 100 generally has a topology that may be incorporated into the impedance matching elements of power amplifier stage 326 and low noise amplifier 330. The integration of the TRX switching topology according to embodiments of the present invention with the impedance matching elements of the Power Amplifier (PA) stage 326 and the low noise amplifier 330 typically results in minimal signal loss (e.g., reduction of output power and PAE in the transmit chain or reduction of noise factor (MF) in the receive chain). The integration of the TRX switch topology according to embodiments of the present invention with the impedance matching elements of the power amplifier stage 326 and the low noise amplifier 330 also typically reduces chip area (compared to conventional high isolation TRX switches).

In various embodiments, TRX switching topologies according to embodiments of the present invention are particularly suitable for, but not limited to, differential or transformer based transmitter and receiver implementations. TRX switch topologies typically do not include any components between the output of the transmit chain (e.g., the output of PA 326) and the input/output of the transceiver circuitry. Thus, the TRX switching topology can be implemented without the need for specific switching components that are required to withstand high voltage swings. Because high breakdown voltage switching components are not required, TRX switching topologies according to embodiments of the present invention are particularly well suited for implementation in advanced short channel body or silicon-on-insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) technologies with low breakdown voltages (e.g., below 1 volt).

Although TRX switch topologies according to embodiments of the present invention can be implemented using a minimal apparent number of elements, TRX switch topologies typically provide a high degree of isolation between transmit and receive chain circuitry. Although the TRX switch topology according to embodiments of the present invention can be highly integrated with the transmit and receive chain circuitry, the TRX switch topology can be designed independently of the transmit and receive chain circuitry and can be incorporated into the corresponding impedance matching network at any stage of development. In general, no co-design and/or co-optimization is required.

Referring now to fig. 8, a diagram illustrating an example implementation of a TRX switch circuit 100 according to a differential embodiment is shown. In an example, the output transformer 500 and the input transformer 502 of the differential power amplifier 326 of the transmit chain and the differential low noise amplifier 330 of the receive chain, respectively, may be configured to incorporate and implement a TRX switch topology according to an embodiment of the present invention. In an example, the output of the output transformer 500 may be directly connected to an input/output (e.g., 10 or 310) of the transceiver circuit.

A series capacitor 504 may be connected between the input of the input transformer 502 and the output of the output transformer 500. The parallel switch 506 may be connected in parallel with the input winding of the input transformer 502. In an example, each transformer 500 and 502 at the output matching network of the transmitter and the input matching network of the receiver, respectively, may be implemented with a planar coupled spiral transmission line on a chip or on a printed circuit board. In an example, the capacitor 504 may be implemented as a metal-insulator-metal (MIM) capacitor or finger capacitor on a chip, or as a ceramic capacitor on a printed circuit board. Capacitor 504 may also be implemented using one or more MOS devices.

Referring to fig. 9, a diagram illustrating another example implementation of a TRX switch 100 utilizing a topology according to a single-ended embodiment of the present invention is shown. In an example, the impedance matching network and bias choke (or inductor) 510 of the power amplifier 326 of the transmit chain and the impedance matching network and bias choke (or inductor) 512 of the low noise amplifier 330 of the receive chain can be configured to incorporate and implement a TRX switch topology according to embodiments of the present invention. In an example, the output of power amplifier 326 may be directly connected to the input/output of transceiver circuit 10 or 310. A series capacitor 504 may be connected between the input of the low noise amplifier 330 and the output of the power amplifier 326. The shunt switch 506 may be connected between the input of the low noise amplifier 330 and the circuit ground potential of the transceiver circuit 310. Each bias choke (or inductor) 510 and 512 may be implemented using a planar spiral transmission line on a chip or on a printed circuit board. The capacitor 504 may be implemented as a MIM capacitor on a chip, or a finger capacitor, or as a ceramic capacitor on a printed circuit board. Capacitor 504 may also be implemented using one or more MOS devices.

Referring to fig. 10, a diagram illustrating another example implementation of a TRX switch 100 utilizing a topology according to a single-ended embodiment of the present invention is shown. In an example, a parallel capacitor 508 may be added to the implementation of fig. 9. In an example, the impedance matching network and bias choke 510 of the power amplifier 326 of the transmit chain, and the impedance matching network and bias choke 512 of the low noise amplifier 330 of the receive chain, may be configured to: a TRX switch topology according to an embodiment of the present invention is incorporated and implemented. In an example, the output of power amplifier 326 may be directly connected to the input/output of transceiver circuit 10 or 310.

In various embodiments, the series capacitor 504 may be connected between the input of the low noise amplifier 330 and the output of the power amplifier 326. The parallel switch 506 may be connected between the input of the low noise amplifier 330 and the circuit ground potential of the transceiver circuit 310. The shunt capacitor 508 may be connected between the input of the low noise amplifier 330 and the circuit ground potential of the transceiver circuit 310. Each bias choke (or inductor) 510 and 512 may be implemented using a planar spiral transmission line on a chip or printed circuit board. Capacitors 504 and 508 may be implemented as MIM capacitors on a chip, or finger capacitors, or ceramic capacitors on a printed circuit board. Capacitors 504 and 508 may also be implemented using one or more MOS devices. In some embodiments, the parasitic capacitance of the switch 506 may be used to implement all or part of the shunt capacitor 508.

Referring to fig. 11, a diagram illustrating yet another example implementation of a TRX switch 100 utilizing a topology according to a differential embodiment of the present invention is shown. In an example, a parallel capacitor 508 may be added to the implementation shown in fig. 8. The shunt capacitor 508 may be used to adjust the optimal impedance presented to the input of the receive chain to improve noise behavior. The capacitor 508 does not generally affect the performance of the transmit chain (e.g., switch 506 is closed). In an example, the output transformer 500 of the differential power amplifier 326 of the transmit chain, and the input transformer 502 of the differential low noise amplifier 330 of the receive chain, respectively, may be configured to incorporate and implement a TRX switching topology according to embodiments of the present invention.

In an example, the output of the output transformer 500 may be directly connected to the input/output of the transceiver circuit 10 or 310. A series capacitor 504 may be connected between the input of the input transformer 502 and the output of the output transformer 500. The parallel switch 506 and the parallel capacitor 508 may be connected in parallel with the input winding of the input transformer 502 and may be implemented with planar coupled spiral transmission lines on a chip or on a printed circuit board. Capacitors 504 and 508 may be implemented as MIM capacitors on a chip, or finger capacitors, or as ceramic capacitors on a printed circuit board. Capacitors 504 and 508 may also be implemented using one or more MOS devices. The parasitic capacitance of the switch 506 may be used to implement all or part of the shunt capacitor 508.

Referring to fig. 12, a diagram of a graph 800 illustrating an analog voltage waveform of the TRX switch in fig. 11 is shown. Waveform 802 illustrates the voltage level at the node formed by the connection of the output of transformer 500 to the input/output of transceiver 10 or 310. Waveform 804 illustrates the voltage level at the node formed by the connection of the input of transformer 502, series capacitor 504, parallel switch 506, and parallel capacitor 508. Generally, TRX switch topologies according to embodiments of the present invention do not introduce distortion into the output signal of a transceiver channel 10 or 310. Furthermore, the shunt switch 506 is not affected by the high voltage swing of the transmitter channel operation, and therefore can be implemented with low voltage sub-micron transistor technology (e.g., silicon-on-insulator CMOS transistors with breakdown voltages below 1 volt).

Although embodiments of the present invention have been described in the context of RF applications, the present invention is not limited to RF applications, but may also be applied in other high data rate wireless and wireline communication applications where different fast switching, multi-channel and multi-user problems may exist. The present invention addresses problems associated with high-speed wireless communications, mobile and fixed transceivers, and point-to-point links. Next generation wireless communication applications using Radio Frequency (RF), microwave and millimeter wave links can be expected to provide faster, more flexible and more interconnect and layer numbers. The present invention may also be applicable to wireless communication systems implemented in accordance with existing (legacy, 2G, 3G, 4G, 5G) specifications or future specifications.

When the terms "may" and "typically" are used in conjunction with the "tie verb" and verb, "the following intentions are intended to be conveyed: the present description is exemplary and is considered broad enough to cover both the specific examples presented in the present disclosure as well as alternative examples that may be derived based on the present disclosure. The terms "may" and "typically" as used herein should not be construed as necessarily implying a desire or possibility of omitting corresponding elements.

While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention.