阅读说明：本技术 优化发射器阵列的布局 (Optimizing the layout of an emitter array ) 是由 A.V.巴夫 B.克斯勒 M.G.彼得斯 于 2020-03-31 设计创作，主要内容包括：紧密间隔发射器阵列可以包括包含第一多个结构的第一发射器和与第一发射器相邻的包含第二多个结构的第二发射器。第一发射器和第二发射器可以被配置在紧密间隔发射器阵列中,使得第一多个结构和第二多个结构之间的不同类型结构不重叠,同时保持第一发射器和第二发射器之间的紧密间隔。(The array of closely spaced emitters may include a first emitter comprising a first plurality of structures and a second emitter comprising a second plurality of structures adjacent to the first emitter. The first and second emitters may be configured in an array of closely spaced emitters such that different types of structures between the first and second pluralities of structures do not overlap while maintaining a close spacing between the first and second emitters.)

1. A closely spaced emitter array comprising:

a first emitter comprising a first plurality of structures; and

a second emitter adjacent to the first emitter, comprising a second plurality of structures,

wherein the first emitter and the second emitter are configured in an emitter array such that different types of structures between the first plurality of structures and the second plurality of structures do not overlap while maintaining a close spacing between the first emitter and the second emitter.

2. The array of closely spaced emitters of claim 1, wherein the first emitter is rotated relative to the second emitter.

3. The closely spaced transmitter array of claim 1, wherein the first plurality of structures and the second plurality of structures share at least one of:

a p-type metal extension, or

A via hole, or

And (4) a groove.

4. The closely spaced emitter array of claim 3, wherein at least one of:

a first via included in the first plurality of structures is connected to a second via included in the second plurality of structures,

a first trench included in the first plurality of structures is connected to a second trench included in the second plurality of structures, or

A first p-type metal extension included in the first plurality of structures is connected to a second p-type metal extension included in the second plurality of structures.

5. The closely spaced emitter array of claim 1, wherein the first plurality of structures comprises at least one of a first number of different p-type metal extensions relative to a second number of p-type metal extensions included in the second plurality of structures or a first number of different trenches relative to a second number of trenches included in the second plurality of structures, such that:

the p-type metal extensions included in the first plurality of structures and the trenches included in the second plurality of structures do not overlap, and

the trenches included in the first plurality of structures and the p-type metal extensions included in the second plurality of structures do not overlap.

6. The closely spaced emitter array of claim 1, wherein the first plurality of structures comprises at least one of one or more trenches of different shapes relative to one or more trenches included in the second plurality of structures or one or more p-type metal extensions of different shapes relative to one or more p-type metal extensions included in the second plurality of structures, such that:

the one or more p-type metal extensions included in the first plurality of structures and the one or more trenches included in the second plurality of structures do not overlap, and

the one or more trenches included in the first plurality of structures and the one or more p-type metal extensions included in the second plurality of structures do not overlap.

7. The closely spaced emitter array of claim 1, wherein the first plurality of structures comprises at least one of one or more trenches of different sizes relative to one or more trenches included in the second plurality of structures or one or more p-type metal extensions of different sizes relative to one or more p-type metal extensions included in the second plurality of structures, such that:

the one or more p-type metal extensions included in the first plurality of structures and the one or more trenches included in the second plurality of structures do not overlap, and

the one or more trenches included in the first plurality of structures and the one or more p-type metal extensions included in the second plurality of structures do not overlap.

8. The closely spaced emitter array of claim 1, wherein spacing between vias and trenches included in the first plurality of structures is different relative to spacing between vias and trenches included in the second plurality of structures such that:

the p-type metal extensions included in the first plurality of structures and the trenches included in the second plurality of structures do not overlap, and

the trenches included in the first plurality of structures and the p-type metal extensions included in the second plurality of structures do not overlap.

9. The closely spaced emitter array of claim 1, wherein a spacing between a first via and a trench included in the first plurality of structures is different relative to a spacing between a second via and a trench included in the first plurality of structures such that:

the p-type metal extensions included in the first plurality of structures and the trenches included in the second plurality of structures do not overlap, and

the trenches included in the first plurality of structures and the p-type metal extensions included in the second plurality of structures do not overlap.

10. A method, comprising:

generating, by an apparatus, a layout of a closely spaced array of transmitters comprising a plurality of transmitters;

identifying, by the apparatus, an overlap of different types of structures between a first plurality of structures included in a first emitter of the plurality of emitters and a second plurality of structures included in a second emitter of the plurality of emitters; and

the layout of the array of closely spaced emitters is adjusted by the apparatus such that different types of structures between the first plurality of structures and the second plurality of structures do not overlap while maintaining close spacing between the plurality of emitters.

11. The method of claim 10, wherein adjusting the layout of the closely spaced transmitter array comprises at least one of:

adjusting the shape of one or more trenches included in the first plurality of structures,

adjusting the shape of one or more trenches included in the second plurality of structures,

adjusting a size of one or more trenches included in the first plurality of structures,

adjusting the dimensions of one or more trenches included in the second plurality of structures,

adjusting a shape of one or more p-type metal extensions included in the first plurality of structures,

adjusting the shape of one or more p-type metal extensions included in the second plurality of structures,

adjusting the dimensions of one or more p-type metal extensions included in the first plurality of structures,

adjusting the dimensions of one or more p-type metal extensions included in the second plurality of structures,

adjusting a spacing between the p-type metal extensions and the trenches included in the first plurality of structures,

adjusting a spacing between the p-type metal extensions and the trenches included in the second plurality of structures,

rotating at least one of the first emitter or the second emitter,

adjusting at least one of a number of p-type metal extensions included in the first plurality of structures or a number of p-type metal extensions included in the second plurality of structures, or

Adjusting at least one of a number of trenches included in the first plurality of structures or a number of trenches included in the second plurality of structures.

12. The method of claim 10, wherein adjusting the layout of the closely spaced transmitter array comprises:

selecting an orientation of a first emitter in a layout of a closely spaced array of emitters;

identifying a second transmitter based on determining that the second transmitter is within a threshold distance from the first transmitter; and

the orientation of a second emitter in the layout of the array of closely spaced emitters is adjusted such that a spacing between the trenches in the first plurality of structures and the trenches in the second plurality of structures satisfies a threshold distance.

13. The method of claim 10, wherein adjusting the layout of the closely spaced transmitter array comprises:

for each of a plurality of candidate combinations of the orientation of the first transmitter and the orientation of the second transmitter, determining:

a first distance between leading edges of the trenches included in the first plurality of structures and trailing edges of the trenches included in the second plurality of structures,

a second distance between a center of the trench included in the first plurality of structures and a center of the trench included in the second plurality of structures, an

A third distance between a trailing edge of a trench included in the first plurality of structures and a leading edge of a trench included in the second plurality of structures; and

selecting, for a layout of the array of closely spaced emitters and from a plurality of candidate combinations of orientations of the first emitter and the second emitter, a combination of the orientation of the first emitter and the orientation of the second emitter that minimizes the first distance, the second distance, and the third distance.

14. The method of claim 10, wherein adjusting the layout of the closely spaced transmitter array comprises:

for each of a plurality of candidate combinations of the orientation of the first transmitter and the orientation of the second transmitter, determining:

a first distance between a leading edge of a via included in the first plurality of structures and a trailing edge of a via included in the second plurality of structures,

a second distance between a center of a via included in the first plurality of structures and a center of a via included in the second plurality of structures, an

A third distance between a trailing edge of a via included in the first plurality of structures and a leading edge of a via included in the second plurality of structures; and

selecting, for a layout of the array of closely spaced emitters and from a plurality of candidate combinations of orientations of the first emitter and the second emitter, a combination of the orientation of the first emitter and the orientation of the second emitter that minimizes the first distance, the second distance, and the third distance.

15. The method of claim 10, wherein generating a layout of a closely spaced array of emitters comprises:

a random layout of the plurality of transmitters is generated.

16. The method of claim 10, wherein generating a layout of a closely spaced array of emitters comprises:

a grid layout of the plurality of emitters is generated.

17. A closely spaced emitter array comprising:

a first plurality of emitters, each comprising a respective first plurality of structures,

wherein the first plurality of emitters are configured in an array of closely spaced emitters such that different types of structures between each respective first plurality of structures do not overlap while maintaining close spacing between the first plurality of emitters; and

a second plurality of emitters, each comprising a respective second plurality of structures,

wherein the second plurality of emitters is configured in an array of closely spaced emitters such that different types of structures between each respective second plurality of structures do not overlap while maintaining close spacing between the second plurality of emitters.

18. The array of closely spaced emitters of claim 17, wherein each emitter of the first plurality of emitters is located within a threshold distance from another emitter of the first plurality of emitters; and

wherein each emitter of the first plurality of emitters is positioned farther than a threshold distance from each emitter of the second plurality of emitters.

19. The array of closely spaced emitters of claim 17, wherein each emitter of the first plurality of emitters is rotated such that p-type metal extensions included in each respective first plurality of structures and trenches included in each respective first plurality of structures do not overlap; and

wherein each emitter of the second plurality of emitters is rotated such that the p-type metal extensions included in each respective first plurality of structures and the trenches included in each respective second plurality of structures do not overlap.

20. The closely spaced emitter array of claim 17, wherein at least one of a size or a shape of the vias included in each respective first plurality of structures is arranged such that the p-type metal extensions included in each respective first plurality of structures and the trenches included in each respective first plurality of structures do not overlap; and

wherein at least one of a size or a shape of the via included in each respective second plurality of structures is arranged such that the p-type metal extension included in each respective first plurality of structures and the trench included in each respective second plurality of structures do not overlap.

Technical Field

The present disclosure relates to emitter arrays, and more particularly, to optimizing the layout of emitter arrays.

Background

The transmitter may comprise a vertical emitting device, such as a Vertical Cavity Surface Emitting Laser (VCSEL). A VCSEL is a laser in which a beam of light is emitted in a direction perpendicular to the surface of the VCSEL (e.g., perpendicularly from the surface of the VCSEL). The plurality of emitters may be in an emitter array having a common substrate.

Disclosure of Invention

According to some embodiments, a closely spaced emitter array may include a first emitter comprising a first plurality of structures; and a second emitter adjacent to the first emitter, comprising a second plurality of structures, wherein the first emitter and the second emitter are configured in an array of closely spaced emitters such that different types of structures between the first plurality of structures and the second plurality of structures do not overlap while maintaining a close spacing between the first emitter and the second emitter.

According to some embodiments, a method may comprise: generating, by an apparatus, a layout of a closely spaced array of emitters comprising a plurality of emitters; identifying, by the apparatus, an overlap of different types of structures between a first plurality of structures included in a first emitter of the plurality of emitters and a second plurality of structures included in a second emitter of the plurality of emitters; and adjusting, by the device, a layout of the array of closely spaced emitters such that different types of structures between the first plurality of structures and the second plurality of structures do not overlap while maintaining close spacing between the plurality of emitters.

According to some embodiments, the closely spaced emitter array may comprise: a first plurality of emitters, each comprising a respective first plurality of structures, wherein the first plurality of emitters are configured in an array of closely spaced emitters such that different types of structures between each respective first plurality of structures do not overlap while maintaining close spacing between the first plurality of emitters; and a second plurality of emitters, each comprising a respective second plurality of structures, wherein the second plurality of emitters are configured in an array of closely spaced emitters such that different types of structures between each respective second plurality of structures do not overlap while maintaining close spacing between the second plurality of emitters.

Drawings

Fig. 1A and 1B are a plan view showing an exemplary vertical emission device and a sectional view showing the exemplary vertical emission device, respectively.

Fig. 2A and 2B are schematic diagrams of one or more example embodiments described herein.

FIG. 3 is a diagram of example components of an apparatus.

Fig. 4-7 are flow diagrams of example processes for optimizing the layout of a closely spaced array of emitters.

Detailed Description

The following detailed description of exemplary embodiments refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements.

Emitter arrays are used in a variety of applications. For example, emitter arrays are used in three-dimensional sensing applications, such as structured light applications, time-of-flight applications, light detection and ranging (LIDAR) applications, and/or the like. The emitter array includes a plurality of emitters, such as a plurality of vertical light emitting devices formed on a chip, which in turn is formed on a wafer. Typically, the emitter comprises a mesa structure comprising an ohmic metal layer surrounding a hole of the emitter (e.g. in the shape of a ring or partial ring) and a set of vias (e.g. also in the shape of a ring or partial ring matching the shape of the ohmic metal layer) through the protective layer down to the ohmic metal layer. In addition, the emitter array includes trenches between the mesa structure of the emitter (and in some cases forming the mesa structure) and one or more other emitters of the emitter array. For example, trenches are typically formed around a respective set of vias of the ohmic metal layer and/or the emitter. This configuration of the emitters and/or emitter array (e.g., trenches formed around the ohmic metal layer and a corresponding set of vias) typically results in narrow manufacturing tolerances and/or typically requires a specific amount of chip space for each emitter of the emitter array. The closer the emitters of the emitter array are spaced, the more the overall chip size can be reduced. The small chip size allows for more chips per wafer, and smaller chips can be placed in smaller packages, thereby reducing the overall cost of the chip and package structure.

Some embodiments described herein provide various techniques and apparatuses for optimizing the layout of an array of emitters. In some implementations, the techniques, processes, and/or algorithms described herein may configure, adjust, and/or modify parameters and/or structures of emitters (e.g., vias, trenches, p-type metal extensions, and/or the like) included in an emitter array to optimize an existing layout of the emitter array, to generate parameters for a new and optimized layout of the emitter array, and/or the like. For example, the techniques, processes, and/or algorithms described herein may align similar structures of two or more adjacent emitters by rotating one or more of the adjacent emitters, with non-similar structures between the two or more adjacent emitters not overlapping. As another example, the techniques, processes, and/or algorithms described herein may adjust and/or modify the size, shape, orientation, and/or other parameters of structures included in an emitter such that the structures do not overlap with different types of structures included in one or more neighboring emitters. As another example, the techniques, processes, and/or algorithms described herein may remove structures from an emitter such that structures of different types of adjacent emitters are not overlapped by the structures. As another example, the techniques, processes, and/or algorithms described herein may connect similar structures between adjacent emitters such that adjacent emitters share the same structure, which reduces manufacturing complexity by eliminating tight manufacturing tolerances between structures if the structures are closely spaced together without connection.

As such, the techniques, processes, and/or algorithms described herein save space associated with the array of emitters and increase the emitter density per chip. Moreover, the techniques, processes, and/or algorithms described herein facilitate reducing a distance between emitters of an emitter array (e.g., an emitter array with smaller spacing between emitters), facilitate reducing an overall chip size associated with an emitter array (e.g., a smaller square area for the same number of emitters as an existing design), facilitate increasing a number of emitters that may be included on a chip of a particular size (having a particular size as compared to an existing design), and/or the like. For example, without layout optimization as described herein, the minimum distance between emitters may be limited to about 25 to 30 micrometers (μm) for a 10 μm oxide aperture. For layout optimization based on the techniques, processes, and/or algorithms described herein, the minimum distance between emitters may be reduced (e.g., to about 14 to 24 μm) for a random emitter array. The exact space savings depends on the geometry of the device (e.g., oxide and non-oxide emitters may have different tradeoffs that affect the final minimum distance between emitters).

In some applications, such as three-dimensional sensing applications, increasing the number of emitters in an emitter array on a particular size chip may improve the operation of a device using the emitter array by providing a greater number of spots for three-dimensional sensing of the device and/or by providing more power or brightness from a particular size chip. Further, reducing the size of the emitters on the chip without increasing the number of emitters on the chip provides wider manufacturing tolerances relative to the aforementioned designs of the emitter arrays, thereby facilitating faster manufacturing of the emitter arrays, reducing manufacturing costs of the emitter arrays, reducing defects during manufacturing of the emitter arrays, reducing post-manufacturing defects due to dislocation propagation (e.g., smaller emitter sizes enable greater distances between emitters while maintaining chip size, which may reduce the likelihood of dislocations intersecting the emitters), and/or the like.

Fig. 1A and 1B are schematic diagrams showing a top view of an exemplary emitter 100 and a cross-sectional view 150 of the exemplary emitter 100, respectively, along line XX. As shown in fig. 1B, the transmitter 100 may include a set of transmit layers configured in a transmitter architecture. In some embodiments, the transmitter 100 may correspond to one or more of the vertical transmission devices described herein.

As shown in fig. 1A, the emitter 100 may include an injection protection layer 102, which in this example is circular in shape. In some embodiments, the implantation protection layer 102 may have another shape, such as an oval, a polygon, and the like. The implantation protection layer 102 is defined based on a space between implantation material portions (not shown) included in the emitter 200.

As shown in the middle and dark gray colors in fig. 1A, the emitter 100 includes an ohmic metal layer 104 (e.g., a p-type ohmic metal layer or an n-type ohmic metal layer) configured in a partial annular shape (e.g., having an inner radius and an outer radius). The medium gray areas show areas of the ohmic metal layer 104 that are covered by a protective layer (e.g., a dielectric layer, a passivation layer, and/or the like) of the emitter 100, and the dark gray areas show areas of the ohmic metal layer 104 that are exposed through the vias 106, as described below. As shown, the ohmic metal layer 104 overlaps the implantation protection layer 102. This configuration may be used, for example, in the case of a P-type up/top emitting emitter 100. In the case of a bottom-emitting emitter 100, the configuration can be adjusted as desired.

Not shown in fig. 1A, the emitter 100 includes a protective layer in which the via 106 is formed (e.g., etched). The dark gray areas show the areas of the ohmic metal layer 104 exposed by the vias 106 (e.g., the shape of the dark gray areas may be the result of the shape of the vias 106), while the middle gray areas show the areas of the ohmic metal layer 104 covered by the protective layer. The protective layer may cover all emitters, not vias. As shown, the via 106 is formed in a partial ring shape (e.g., like the ohmic metal layer 104) and is formed over the ohmic metal layer 104 such that metallization on the protective layer is in contact with the ohmic metal layer 104. In some embodiments, the via 106 and/or the ohmic metal layer 104 may be formed in another shape, such as a full annular shape or a split annular shape.

As further shown, the emitter 100 includes an optical aperture 108 in a portion of the emitter 100 in an inner radius of the partial toroidal shape of the ohmic metal layer 104. The emitter 100 emits a laser beam via the aperture 108. As further shown, the emitter 100 also includes a current-limiting aperture 110 (e.g., an oxide aperture formed through an oxide layer (not shown) of the emitter 100). A current-limiting aperture 110 is formed below the optical aperture 108.

As further shown in fig. 1A, the emitter 100 includes a set of trenches 112 (e.g., oxide trenches) and is spaced apart (e.g., equidistant, non-equidistant) around the circumference of the implant protection layer 102. How close the trench 112 may be positioned relative to the aperture 108 depends on the application and is generally limited by the implantation protection layer 102, the ohmic metal layer 104, the via 106, and manufacturing tolerances.

The number and arrangement of layers shown in FIG. 1A are provided as examples. In practice, the transmitter 100 may include additional layers, fewer layers, different layers, or a different arrangement of layers than shown in fig. 1A. For example, although emitter 100 includes a set of six channels 112, in practice, other configurations are contemplated, including, for example, a compact emitter including five channels 112, seven channels 112, and/or the like. In some embodiments, the grooves 112 may surround the emitter 100 to form a mesa structure d_t. As another example, although the transmitter 100 is a circular transmitter design, in practice other designs may be used, such as a rectangular transmitter, a hexagonal transmitter, an elliptical transmitter, and so forth. Additionally or alternatively, a set of layers (e.g., one or more layers) of transmitter 100 may perform one or more functions described as being performed by another set of layers of transmitter 100, respectively.

It should be noted that although the design of the transmitter 100 is described as including a VCSEL, other embodiments are also contemplated. For example, the design of emitter 100 may be applied in the context of other types of optical devices, such as Light Emitting Diodes (LEDs) or other types of vertically emitting (e.g., top-emitting or bottom-emitting) optical devices. Additionally, the design of the transmitter 100 may be applied to transmitters having any wavelength, power level, transmission mode (emission profile), and/or the like. In other words, the transmitter 100 is not dedicated to a transmitter having a given performance characteristic.

As shown in fig. 1B, an exemplary cross-sectional view may represent a cross-section of emitter 100 through a pair of trenches 112 or between a pair of trenches 112 (e.g., as indicated by the line labeled "XX" in fig. 1A). As shown, the emitter 100 may include a backside cathode layer 128, a substrate layer 126, a bottom mirror 124, an active area 122, an oxide layer 120, a top mirror 118, an implant insulating material 116, a protective layer 114 (e.g., a dielectric passivation/mirror layer), and an ohmic metal layer 104. As shown, the emitter 100 may have a total height of about 10 μm, for example.

The backside cathode layer 128 may include a layer in electrical contact with the substrate layer 126. For example, the backside cathode layer 128 may include an annealed metallization layer, such as an AuGeNi layer, a PdGeAu layer, or the like.

The substrate layer 126 may comprise a base substrate layer on which epitaxial layers are grown. For example, the substrate layer 126 may include a semiconductor layer, such as a GaAs layer, an InP layer, and/or the like.

The bottom mirror 124 may comprise a bottom reflective layer of the emitter 100. For example, the bottom mirror 124 may include a Distributed Bragg Reflector (DBR).

The active region 122 may include a layer that confines electrons and defines the emission wavelength of the emitter 100. For example, the active layer 122 may be a quantum well.

The oxide layer 120 may include an oxide layer that provides optical and electrical confinement of the emitter 100. In some embodiments, oxide layer 120 may be formed as a result of wet oxidation of the epitaxial layer. For example, oxide layer 120 may be Al₂O₃A layer formed by oxidation of the AlAs or AlGaAs layer. The trench 112 may include an opening that allows oxygen (e.g., dry oxygen, wet oxygen) to reach the epitaxial layer from which the oxide layer 120 is formed.

The current-limiting aperture 110 may comprise a spin hole defined through an oxide layer 120. The size of the current-limiting aperture 110 may, for example, be in the range of about 4 μm to about 20 μm. In some embodiments, the size of the current-limiting aperture 110 may depend on the distance between the grooves 112 surrounding the emitter 100. For example, trenches 112 may be etched to expose an epitaxial layer from which oxide layer 120 is formed. Here, a specific distance (e.g., d in fig. 1B) toward the center of the emitter 100 may be targeted before forming (e.g., depositing) the protective layer 114_oShown) to undergo oxidation of the epitaxial layer, thereby forming an oxide layer 120 and a current-limiting aperture 110. In some embodiments, the current confined pores 110 may include oxide pores. Additionally or alternatively, the current-limiting aperture 110 may include other types of current-limiting techniques (e.g., etched boss (et)chemical mesa), areas without ion implantation, lithographically defined inner cavity mesas, and regrowth (etc.) associated holes.

The top mirror 118 may comprise a top reflective layer of the emitter 100. For example, the top mirror 118 may include a DBR.

The injected insulative material 116 may include a material that provides electrical insulation. For example, the implant insulating material 116 may include an ion implant material, such as a hydrogen/proton implant material or similar implant element, to reduce conductivity. In some embodiments, the implant insulating material 116 may define the implant protection layer 102.

The protective layer 114 may include a layer that functions as a protective passivation layer and may function as an additional DBR. For example, protective layer 114 may include one or more sub-layers (e.g., dielectric passivation and/or reflective layers, SiO) deposited (e.g., by chemical vapor deposition, atomic layer deposition, or other techniques) on one or more other layers of emitter 100₂Layer of Si₃N₄Layer of Al₂O₃Layer, or other layer).

As shown, the protective layer 114 may include one or more vias 106 that provide dielectric access to the ohmic metal layer 104. For example, the vias 106 may be formed as etched portions of the protective layer 114 or as stripped portions of the protective layer 114. The light aperture 108 may include a portion of the protective layer 114 over the current-limiting aperture 110 through which light may be emitted.

The ohmic metal layer 104 may include a layer that makes electrical contact through which current may flow. For example, the ohmic metal layer 104 may include a Ti and Au layer, a Ti and Pt layer, and/or an Au layer, etc., through which current may flow (e.g., via a bond pad (not shown) that contacts the ohmic metal layer 104 via the via 106). The ohmic metal layer 104 may be P-type, N-type, or other forms known in the art. The selection of a particular type of ohmic metal layer 104 may depend on the architecture of the emitter and is known within the knowledge of those skilled in the art. The ohmic metal layer 104 may provide an ohmic contact between the metal and the semiconductor and/or may provide a non-rectifying electrical bond and/or may provide a low resistance contact. In some embodiments, emitter 100 may be manufactured using a series of steps. For example, the bottom mirror 124, the active region 122, the oxide layer 120, and the top mirror 118 may be epitaxially grown on the substrate layer 126, after which the ohmic metal layer 104 may be deposited on the top mirror 118. Next, trench 112 may be etched to expose oxide layer 120 for oxidation. The implant insulating material 116 may be formed via ion implantation, after which the protective layer 114 may be deposited. The vias 106 may be etched in the protective layer 114 (e.g., to expose the ohmic metal layer 104 for contact). Plating, seeding, and etching may be performed, after which the substrate layer 126 may be thinned and/or overlapped (lapped) to a target thickness. Finally, a backside cathode layer 128 may be deposited on the bottom side of the substrate layer 126.

The number, arrangement, thickness, order, symmetry, etc. of the layers shown in FIG. 1B are provided as examples. In practice, the transmitter 100 may include additional layers, fewer layers, different layers, layers of different construction, or layers of different arrangement than shown in fig. 1B. Additionally or alternatively, a set of layers (e.g., one or more layers) of transmitter 100 may perform one or more functions, which are described as being performed by another set of layers of transmitter 100, and any layer may include more than one layer.

Fig. 2A and 2B are schematic diagrams of one or more exemplary embodiments described herein for optimizing the layout of an emitter array 200. In some embodiments, fig. 2A and 2B may show a complete emitter array 200. In some embodiments, fig. 2A and 2B may show a portion of the emitter array 200, and the techniques, processes, and/or algorithms associated with fig. 2A and 2B may be used to optimize the layout of the remainder of the emitter array 200.

Fig. 2A shows a non-optimized layout of an emitter array 200. As shown in fig. 2A, the emitter array 200 may include a plurality of emitters 202. In some implementations, the device can generate a non-optimized layout of the emitter array 200 to include a two-dimensional pattern (e.g., a grid pattern, a hexagonal pattern, a random pattern, an irregular pattern, etc.) or configuration of a plurality of emitters 202 on a substrate of the chip or device.

The emitter 202 may be a vertical light emitting device such as a Light Emitting Diode (LED), a Vertical Cavity Surface Emitting Laser (VCSEL), a Vertical External Cavity Surface Emitting Laser (VECSEL), or the like. As further shown in fig. 2A, the emitter 202 may include various types of structures, such as one or more trenches 204, one or more p-type metal extensions 208 (e.g., extensions extending radially outward from a p-type metal ring 206), one or more vias in the one or more p-type metal extensions 208, and/or the like.

In some embodiments, the trench 204 may include various oxide trenches, and the like. In some embodiments, the p-type metal ring 206 and the p-type metal extension 208 may be one or more layers of p-type ohmic metal. In some embodiments, one or more protective layers (e.g., dielectric layers, passivation layers, and/or other types of protective layers) included on the p-type metal ring 206 and the p-type metal extension 208 may be removed (e.g., by etching or other processes) such that the via 210 is formed through the protective layers to expose the p-type ohmic metal under the protective layers. The trench 204, the p-type metal extension 208, and the via 210 may be located around the p-type metal ring 206. Trenches 204 may be interspersed between p-type metal extensions 208/vias 210. For example, as shown in fig. 2A, trenches 204 and p-type metal extensions 208/vias 210 may alternate around the circumference of p-type metal ring 206.

As further shown in fig. 2A, the layout of the emitter array 200 may include individual emitters 202 (e.g., ungrouped emitters 202) and one or more groups 214 of emitters 202, such as group 214a, group 214b, and/or the like. Multiple transmitters 202 may be "grouped" if transmitters 202 at least partially overlap (e.g., one or more structures of a transmitter 202 at least partially overlap with one or more structures of another transmitter 202), if transmitters 202 are within a threshold distance of each other, and/or the like. That is, the group 214 of emitters 202 may include a plurality of emitters 202 that are successively overlapped.

The emitters 202 may be configured in the emitter array 200 in fig. 2A such that the direction of all emitters 202 is the same direction. As used herein, the "orientation" of the emitter 202 may refer to the location of the notch 212 in the p-type metal ring 206 of the emitter 202, and may be indicated by a line YY passing through the radius of the p-type metal ring 206 and through the notch 212. Combinations of the orientation of the emitters 202, the close spacing between the emitters 202, the shape, size, and/or other parameters of the structures included in the emitters 202 may result in a non-optimized layout of the emitter array 200.

In some cases, the layout of the emitter array 200 shown in fig. 2A may be a non-optimized layout in which there is an overlap of one or more of the regions 216 (e.g., regions 216a-216d) of dissimilar structures of two or more emitters 202 in the emitter array 200. For example, in region 216, the trenches 204 of the first emitter 202 may at least partially overlap the p-type metal extensions 208 and vias 210 of the second emitter 202, and the trenches 204 of the second emitter 202 may at least partially overlap the p-type metal extensions 208 and vias 210 of the first emitter 202. As a result, in some cases, only a minimum spacing of 25 to 30 μm between emitters 202 in emitter array 200 may be achieved.

Fig. 2B shows an example optimized layout of the emitter array 200. In some embodiments, the apparatus may adjust the layout of the emitter array 200 using one or more of the techniques, processes, and/or algorithms described herein to optimize the layout and/or layout of other emitter arrays. The layout of the emitter array 200 shown in fig. 2B may be optimized where different types of structures between the emitters 202 in the emitter array 200 do not overlap (e.g., between the trenches 204 of the emitters 202 and the p-type metal extensions 208 or vias 210 of adjacent emitters 202), which allows closer spacing between the emitters 202 in the emitter array 200 relative to a non-optimized layout. In this case, the emitter array 200 may be referred to as a closely spaced emitter array because the emitters 202 are allowed to be spaced 14-24 μm apart.

In some embodiments, optimizing the layout of the emitter array 200 may include modifying or adjusting the orientation of the emitters 202 by rotating the emitters 202 such that the notches 212 are oriented in different directions (e.g., by rotating the emitters 202 such that the notches 212 are rotated 30 degrees relative to the initial position of the notches 212). Rotating one or more adjacent emitters 202 may allow for alignment and/or overlap of trenches 204 of adjacent emitters 202, may allow for alignment and/or overlap of p-type metal extensions 208 and/or vias 210 of adjacent emitters 202, and may prevent trenches 204 from overlapping p-type metal extensions 208 and/or vias 210 of adjacent emitters 202.

In some embodiments, optimizing the layout of the emitter array 200 may include modifying or adjusting the spacing between different types of structures between adjacent emitters 202 in the emitter array 200. For example, the spacing between trenches 204 in an emitter 202 and p-type metal extensions 208 and/or vias 210 in adjacent emitters 202 may be adjusted such that trenches 204 do not overlap p-type metal extensions 208 and/or vias 210. In some embodiments, optimizing the layout of the emitter array 200 may include modifying or adjusting the spacing between different types of structures within the same emitter 202. For example, the spacing between trenches 204 in an emitter 202 and p-type metal extensions 208 and/or vias 210 in an emitter 202 may be adjusted such that trenches 204 do not overlap p-type metal extensions 208 and/or vias 210 in adjacent emitters 202.

In some embodiments, optimizing the layout of the emitter array 200 may include modifying or adjusting the size and/or shape of one or more structures of one or more adjacent emitters 202. In some implementations, modifying the shape of the structure included in the emitter 202 can include changing the shape of the structure to another shape such that the structure does not overlap with a different type of structure in an adjacent emitter 202. For example, the shape of the grooves 204 of the emitters 202 may change from circular cross-section to triangular, depending on the geometry of the emitter 202 and/or adjacent emitters 202.

In some implementations, modifying the dimensions of the structure included in the emitter 202 may include increasing or decreasing the radial width or sweep angle (sweep angle) of the structure. The radial width or sweep angle of the structure may refer to the radial distance between the leading edge 218 (e.g., a first edge of the structure circumferential along the p-type metal ring 206 in a counter-clockwise direction) and the trailing edge 220 (e.g., a second edge of the structure circumferential along the p-type metal ring 206 in a counter-clockwise direction) of the structure. The radial width or sweep angle of the structure may be modified or adjusted by increasing or decreasing the distance between the leading edge 218 and the trailing edge 220, by modifying or adjusting the position of the leading edge 218 and/or the trailing edge 220, and/or the like.

In some embodiments, modifying the size of the structure included in emitter 202 may include increasing or decreasing the radial width of the structure. The radial width of the structure may refer to the radial distance between the p-type metal ring 206 and the outer edge 222 of the structure. This radial width of the structure may be modified or adjusted by increasing or decreasing the radial distance between the p-type metal ring 206 and the outer edge 222.

In some implementations, optimizing the layout of the emitter array 200 can include adding or removing one or more structures from the emitters 202 such that the one or more removed structures do not overlap with one or more structures in adjacent emitters 202. In this case, the emitters 202 may include a different number of particular structure types (or multiple structure types) relative to adjacent emitters 202. For example, the p-type metal extensions 208 and/or vias 210 may be removed from the emitters 202 such that the p-type metal extensions 208 and/or vias 210 and the trenches 204 of adjacent emitters 202 do not overlap.

In some implementations, optimizing the layout of the emitter array 200 can include adjusting or modifying the orientation of the emitters 202, adjusting or modifying the size and/or shape of the structures of the emitters 202, and/or the like, such that the structures of the emitters 202 can overlap with the same type of structures of adjacent emitters 202. The overlap of structures of the same type may be intentional, rather than unintentional or unintentional. An unintentional overlap may be an overlap of structures of the same type as a result of a change, such as a rotation of the transmitter 202, and/or another type of change, which provides layout optimization by eliminating overlap between structures of different types without the intent of causing an overlap of structures of the same type.

The intentional overlap may be an overlap of the same type of structures such that the overlapping structures may be connected to form a single structure shared between the emitter 202 and adjacent emitters 202. In this case, the transmitter 202 may be explicitly rotated to cause overlap of the same type of structure. As an example, the p-type metal extensions 208 and associated vias 210 of an emitter 202 may be connected to the p-type metal extensions 208 and associated vias 210, respectively, of an adjacent emitter 202, such that a single p-type metal extension 208 and a single via 210 are shared between the emitter 202 and the adjacent emitter 202. This improves the process margins for fabricating the emitter 202 and the adjacent emitters 202, allows current to flow through the single via 210 to the single p-type metal extension 208, allows current to flow through the emitter 202 and the adjacent emitters 202, and/or the like.

In some embodiments, the apparatus may optimize the layout of the emitter array 200 (e.g., increase the density of emitters 202 in the emitter array 200, reduce and/or minimize overlap of different types of structures, and/or the like) using any of the techniques described above, or a combination thereof. As an example, as shown in region 216a in fig. 2B, the dimensions of the trenches 204 in adjacent emitters 202 may be adjusted or modified (e.g., the radial width or sweep angle of the trenches 204 may be reduced) such that the trenches 204 do not overlap the p-type metal extensions 208 and vias 210 of adjacent emitters 202, as shown in the non-optimized configuration of 216a in fig. 2A.

As another example, as shown in region 216B in fig. 2B, the orientation of the emitters 202 may be modified or adjusted (e.g., the emitters 202 may be rotated) such that the grooves 204 of an emitter 202 overlap (e.g., unintentionally or intentionally) the grooves 204 of adjacent emitters 202. In this example, the rotation of emitter 202 prevents trenches 204 of emitter 202 from overlapping p-type metal extensions 208 and vias 210 of adjacent emitters 202, and prevents trenches 204 of adjacent emitters 202 from overlapping p-type metal extensions 208 and vias 210 of emitters 202, as shown in the non-optimized configuration of 216b in fig. 2A. Further, the rotation of the emitter 202 allows the p-type metal extensions 208 and associated vias 210 to overlap and connect with the p-type metal extensions 208 and associated vias 210 of adjacent vias 210, such that a single p-type metal extension 208 and associated via 210 is formed and shared between the emitter 202 and the adjacent emitter 202. Rotation of the emitter 202 further allows the trenches 204 to overlap and connect with the trenches 204 of adjacent vias 210 such that a single trench 204 is formed and shared between the emitter 202 and adjacent emitters 202.

As another example, as shown in region 216c in fig. 2B, the orientation of the emitter 202 and the adjacent emitter 202 may be modified or adjusted (e.g., the emitter 202 and the adjacent emitter 202 may each be rotated) such that each of the plurality of grooves 204 of the emitter 202 overlaps (e.g., unintentionally or intentionally) with a corresponding groove 204 of the adjacent emitter 202. Further, the rotation of the emitter 202 and the adjacent emitter 202 allows the p-type metal extensions 208 and associated vias 210 to intentionally overlap and connect with the p-type metal extensions 208 and associated vias 210 of the adjacent vias 210, such that a single p-type metal extension 208 and associated via 210 is formed and shared between the emitter 202 and the adjacent emitter 202.

In some implementations, various combinations of structures can be connected between the emitter 202 and an adjacent emitter 202, e.g., one or more p-type metal extensions 208 and associated vias 210 (e.g., as shown in region 216B of fig. 2B, a single p-type metal extension 208 and associated via 210, and/or the like) between the emitter 202 and an adjacent emitter 202, one or more trenches 204 (e.g., as shown in regions 216B and 216c of fig. 2B) between the emitter 202 and an adjacent emitter 202, the p-type metal extensions 208 (but not the associated vias 210) can be connected between the emitter 202 and an adjacent emitter 202, the p-type metal extensions 208 and/or associated vias 210 (but not the trenches 204) can be connected between the emitter 202 and an adjacent emitter 202, and the trenches 204 (but not the p-type metal extensions 208 and/or associated vias 210) can be connected between the emitter 202 and an adjacent emitter 202 Transmitters 202, and/or other combinations.

As another example, as shown in region 216d in fig. 2B, the dimensions of the first trenches 204 in the emitters 202 may be adjusted or modified (e.g., the radial width of the trenches 204 may be reduced) such that the first trenches 204 do not overlap with the p-type metal extensions 208 and associated vias 210 of neighboring emitters 202, as shown in the non-optimized configuration 216d in fig. 2A. Further, the second trenches 204 of the emitters 202 may be removed such that the second trenches 204 do not overlap with the p-type metal extensions 208 and associated vias 210 of neighboring emitters 202.

In some implementations, the apparatus can optimize the layout of the emitter array 200 (e.g., increase the density of the emitters 202 in the emitter array 200, reduce and/or minimize different types of overlapping structures, etc.) using any of the techniques described above and/or other techniques, or combinations thereof, in a process (e.g., iterative or non-iterative), an algorithm (e.g., iterative or non-iterative), and/or the like. For example, the apparatus may optimize the layout of the transmitter array 200 using any of the techniques described above and/or other techniques, or combinations thereof, in the process 400 of fig. 4, the process 500 of fig. 5, the process 600 of fig. 6, the process 700 of fig. 7, and/or the like.

In this manner, the techniques, processes, and/or algorithms described herein may be used to optimize the layout of the emitter array 200 and/or other emitter arrays to save space associated with the emitter arrays and increase the emitter density per chip. Moreover, the techniques, processes, and/or algorithms described herein facilitate reducing a distance between emitters of an array of emitters (e.g., an array of emitters having a smaller spacing between emitters), facilitate reducing an overall chip size associated with an array of emitters (e.g., an area smaller for the same number of emitters as an existing design), facilitate increasing a number of emitters that may be included on a chip of a particular size (having a particular size as compared to an existing design), and/or the like.

As described above, fig. 2A and 2B are provided as one or more examples. Other examples may be different than that described with respect to fig. 2A and 2B.

Fig. 3 is a diagram of example components of an apparatus 300. The apparatus 300 may comprise a computing apparatus, such as a laptop computer, a tablet computer, a handheld computer, a desktop computer, a server computer, a workstation computer, a virtual machine provided in a cloud computing environment, one or more apparatuses in a distributed computing network, and/or the like. In some implementations, a laptop computer, a tablet computer, a handheld computer, a desktop computer, a server computer, a workstation computer, a virtual machine provided in a cloud computing environment, one or more devices in a distributed computing network, and/or the like may include one or more devices 300 and/or one or more components of device 300. As shown in fig. 3, apparatus 300 may include a bus 310, a processor 320, a memory 330, a storage component 340, an input component 350, an output component 360, and a communication interface 370.

Bus 310 includes components that allow communication among the components of device 300. Processor 320 is implemented in hardware, firmware, or a combination of hardware and software. Processor 320 takes the form of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Accelerated Processing Unit (APU), microprocessor, microcontroller, Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), or other type of processing component. In some implementations, the processor 320 includes one or more processors that can be programmed to perform functions. Memory 330 includes a Random Access Memory (RAM), a Read Only Memory (ROM), and/or another type of dynamic or static storage device (e.g., flash memory, magnetic memory, and/or optical memory) that stores information and/or instructions for use by processor 320.

The memory component 340 stores information and/or software related to the operation and use of the device 300. For example, storage 340 may include a hard disk (e.g., a magnetic disk, an optical disk, a magneto-optical disk, and/or a solid state disk), a Compact Disc (CD), a Digital Versatile Disc (DVD), a floppy disk, a cassette tape, a magnetic tape, and/or another type of non-transitory computer-readable medium, and a corresponding drive.

Input component 350 includes components that allow device 300 to receive information, such as through user input (e.g., a touch screen display, keyboard, keypad, mouse, buttons, switches, and/or microphone). Additionally or alternatively, input component 350 may include sensors for sensing information (e.g., Global Positioning System (GPS) components, accelerometers, gyroscopes, and/or actuators). Output component 360 includes components that provide output information from device 300 (e.g., a display, a speaker, and/or one or more Light Emitting Diodes (LEDs)).

Communication interface 370 includes transceiver-like components (e.g., a transceiver and/or separate receiver and transmitter) that enable device 300 to communicate with other devices, e.g., via a wired connection, a wireless connection, or a combination of wired and wireless connections. Communication interface 370 may allow device 300 to receive information from another device and/or provide information to another device. For example, communication interface 370 may include an ethernet interface, an optical interface, a coaxial interface, an infrared interface, a radio frequency interface (RF), a universal serial bus interface (USB), a Wi-Fi interface, a cellular network interface, and so forth.

Apparatus 300 may perform one or more processes described herein. Apparatus 300 may perform these processes based on processor 320 executing software instructions stored by a non-transitory computer-readable medium, such as memory 330 and/or storage 340. A computer-readable medium is defined herein as a non-transitory storage device. The storage device comprises storage space within a single physical storage device or storage space distributed over multiple physical storage devices.

The software instructions may be read into memory 330 and/or storage component 340 from another computer-readable medium or from another device via communication interface 370. When executed, software instructions stored in memory 330 and/or storage 340 may cause processor 320 to perform one or more processes described herein. Additionally, or alternatively, hardwired circuitry may be used in place of or in combination with software instructions to implement one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown in fig. 3 are provided as an example. In practice, the apparatus 300 may include more components, fewer components, different components, or a different arrangement of components than those shown in FIG. 3. Additionally or alternatively, a set of components (e.g., one or more components) of apparatus 300 may perform one or more functions described as being performed by another set of components of apparatus 300.

Fig. 4 is a flow diagram of an example process 400 for optimizing the layout of a closely spaced array of emitters. For example, fig. 4 illustrates an example process 400 for optimizing the layout of the transmitter array 200 described above. It is worthy to note that although the example process 400 is described in the context of optimizing the layout of the emitter array 200, the embodiments described with respect to the process 400 are equally applicable to other types of closely spaced emitter arrays. In some implementations, process 400 may be performed by an apparatus (e.g., apparatus 300 and/or another apparatus).

As shown in fig. 4, process 400 may include generating a layout of a closely spaced array of emitters including a plurality of emitters (block 410). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may generate a layout of a closely-spaced array of transmitters (e.g., array of transmitters 200) including a plurality of transmitters (e.g., transmitter 202). In some embodiments, the layout of the array of closely spaced emitters may include a two-dimensional pattern (e.g., a grid pattern, a hexagonal pattern, a random pattern, an irregular pattern, etc.) or configuration of multiple emitters on a substrate of a device or chip.

As further shown in fig. 4, process 400 may include identifying an overlap of different types of structures between a first plurality of structures included in a first transmitter of the plurality of transmitters and a second plurality of structures included in a second transmitter of the plurality of transmitters (block 420). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may identify an overlap of different types of structures between a first plurality of structures included in a first one of the plurality of transmitters and a second plurality of structures included in a second one of the plurality of transmitters. For example, the apparatus may identify an overlap between a trench (e.g., trench 204) of the first emitter and a p-type metal extension (e.g., p-type metal extension 208) and/or via (e.g., via 210) of the second emitter.

As further shown in fig. 4, process 400 may include adjusting a layout of an array of closely spaced emitters such that different types of structures between the first plurality of structures and the second plurality of structures do not overlap while maintaining close spacing between the plurality of emitters (block 430). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may adjust the layout of the array of closely spaced emitters such that different types of structures between the first plurality of structures and the second plurality of structures do not overlap while maintaining close spacing between the plurality of emitters.

In some implementations, adjusting the layout of the closely spaced emitter array can include adjusting a shape of one or more trenches included in the first plurality of structures (e.g., trench 204), adjusting a shape of one or more trenches included in the second plurality of structures, adjusting a size of one or more trenches included in the first plurality of structures, adjusting a size of one or more trenches included in the second plurality of structures, adjusting a shape of one or more vias included in the first plurality of structures (e.g., via 210), adjusting a shape of one or more vias included in the second plurality of structures, adjusting a size of one or more vias included in the first plurality of structures, adjusting a size of one or more vias included in the second plurality of structures, adjusting a spacing between vias and trenches included in the first plurality of structures, adjusting a spacing between vias and trenches included in the second plurality of structures, and adjusting a spacing between vias and trenches included in the second plurality of structures, Adjusting a spacing between vias and trenches included in the second plurality of structures, rotating at least one of the first emitter or the second emitter, or adjusting at least one of a number of vias included in the first plurality of structures or a number of vias included in the second plurality of structures, or adjusting at least one of a number of trenches included in the first plurality of structures or a number of trenches included in the second plurality of structures, adjusting a size, shape, spacing, and/or number of p-type metal extensions (e.g., p-type metal extensions 208) included in the first plurality of structures and/or the second plurality of structures, and so forth.

In some implementations, adjusting the layout of the closely spaced transmitter arrays may include adjusting the layout of the closely spaced transmitter arrays based on one or more techniques, processes, and/or algorithms described with respect to process 500 of fig. 5, process 600 of fig. 6, and/or process 700 of fig. 7.

Process 400 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and/or associated with one or more other processes described elsewhere herein.

Although fig. 4 shows example blocks of the process 400, in some implementations, the process 400 may include additional blocks, fewer blocks, different blocks, or a different arrangement of blocks than those depicted in fig. 4. Additionally or alternatively, two or more blocks of process 400 may be performed in parallel.

Fig. 5 is a flow diagram of an example process 500 for optimizing the layout of a closely spaced array of emitters. For example, fig. 5 illustrates an example process 500 for optimizing the layout of the transmitter array 200 described above. It is worthy to note that although the exemplary process 500 is described in the context of optimizing the layout of the emitter array 200, the embodiments described with respect to the process 500 are equally applicable to other types of closely spaced emitter arrays. In some implementations, the process 500 may be performed by an apparatus (e.g., the apparatus 300 and/or another apparatus).

As shown in fig. 5, the process 500 may include selecting an orientation of a first emitter in a layout of a closely spaced array of emitters (block 510). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may select an orientation of a first emitter (e.g., first emitter 202) in a layout of a closely-spaced emitter array (e.g., emitter array 200). In some implementations, the process 500 may include identifying the first transmitter based on determining that the first transmitter has the smallest spacing from a threshold number (e.g., three and/or the like) of adjacent transmitters in the array of closely spaced transmitters. In some implementations, determining that the first emitter has the minimum spacing from the threshold number of adjacent emitters in the array of closely spaced emitters may include determining a trench center for each emitter in the array of closely spaced emitters and identifying the threshold number of adjacent emitters closest to the emitter from the trench centers of the emitters.

In some implementations, the orientation of the first emitter can be determined based on a location of a notch (e.g., notch 212) in a p-type metal ring (e.g., p-type metal ring 206) included in the first emitter. In some embodiments, selecting the orientation of the first emitter may include fixing the orientation of the first emitter at a particular angle of rotation in the emitter array.

As further shown in fig. 5, process 500 may include identifying a second transmitter based on determining that the second transmitter is within a threshold distance from the first transmitter (block 520). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may identify a second transmitter (e.g., second transmitter 202) based on determining that the second transmitter is within a threshold distance from the first transmitter. In some implementations, determining that the second emitter is within a threshold distance from the first emitter may include determining that the second emitter is an un-optimized emitter (e.g., not labeled as optimized) closest to the first emitter and having a minimum separation from the first emitter and/or an un-optimized emitter (e.g., not labeled as optimized) closest to other optimized emitters.

As further shown in fig. 5, the process 500 may include adjusting an orientation of a second emitter in the emitter array layout such that a spacing between the trenches in the first emitter and the trenches in the second emitter satisfies a threshold distance (block 530). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may adjust an orientation of a second emitter in the emitter array layout such that a separation between a trench in the first emitter (e.g., trench 204) and a trench in the second emitter (e.g., trench 204) satisfies a threshold distance. In some implementations, adjusting the orientation of the second emitter may include rotating the second emitter such that the adjusted orientation of the second emitter minimizes a trench-to-trench spacing between the second emitter and the first emitter (and other optimized emitters in the emitter array).

In some implementations, the process 500 can further include performing the techniques described above with respect to block 510 and 530 for other emitters in the array of emitters until the layout of the array of emitters is optimized.

Process 500 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and/or associated with one or more other processes described elsewhere herein.

Although fig. 5 shows example blocks of the process 500, in some implementations, the process 500 may include additional blocks, fewer blocks, different blocks, or a different arrangement of blocks than those shown in fig. 5. Additionally, or alternatively, two or more blocks of process 500 may be performed in parallel.

Fig. 6 is a flow diagram of an example process 600 for optimizing a transmitter array layout. For example, fig. 6 illustrates an example process 600 for optimizing the layout of the transmitter array 200 described above. It is worthy to note that although the example process 600 is described in the context of optimizing the layout of the emitter array 200, the embodiments described with respect to the process 600 are equally applicable to other types of emitter arrays. In some implementations, the process 600 may be performed by an apparatus (e.g., the apparatus 300 and/or another apparatus).

As shown in fig. 6, process 600 may include, for each of a plurality of candidate combinations of an orientation of a first emitter included in an emitter array and an orientation of a second emitter included in the emitter array, determining a first distance between a leading edge (leading edge) of a trench included in the first emitter and a trailing edge (trailing edge) of a trench included in the second emitter, a second distance between a center of a trench included in the first emitter and a center of a trench included in the second emitter, and a third distance between a trailing edge of a trench included in the first emitter and a leading edge of a trench included in the second emitter (block 610). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may determine, for each of a plurality of candidate combinations of an orientation of a first emitter (e.g., first emitter 202) included in an emitter array (e.g., emitter array 200) and an orientation of a second emitter (e.g., second emitter 202) included in the emitter array, a first distance between a leading edge (e.g., leading edge 218) of a trough (e.g., trough 204) included in the first emitter and a trailing edge (e.g., trailing edge 220) of a trough included in the second emitter, a second distance between a center of a trough included in the first emitter and a center of a trough included in the second emitter, and a third distance between a trailing edge of a trench included in the first emitter and a leading edge of a trench included in the second emitter.

In some implementations, the orientation of the first emitter can be determined based on a location of a notch (e.g., notch 212) in a p-type metal ring (e.g., p-type metal ring 206) included in the first emitter. In some implementations, the orientation of the second emitter can be determined based on a location of a notch (e.g., notch 212) in a p-type metal ring (e.g., p-type metal ring 206) included in the second emitter.

In some implementations, the process 600 can include identifying the first emitter and the second emitter by grouping the first emitter and the second emitter into a group (e.g., group 214) based on design parameters of the fabrication and/or mask layout of the array of emitters. For example, the first emitter and the second emitter may be grouped based on a proximity and/or a threshold distance between the first emitter and the second emitter. In some embodiments, the other emitters may be grouped with the first emitter and the second emitter, and the other emitter groups may be formed based on similar parameters. In some embodiments, ungrouped transmitters may be ignored.

In some implementations, process 600 may further include, for each of a plurality of candidate combinations of orientations of the first transmitter and the second transmitter, determining a first distance between a leading edge of a p-type metal extension included in the first transmitter (e.g., p-type metal extension 208) and a trailing edge of a p-type metal extension included in the second transmitter, a second distance between a center of a p-type metal extension included in the first transmitter and a center of a p-type metal extension included in the second transmitter, and a third distance between a trailing edge of a p-type metal extension included in the first transmitter and a leading edge of a p-type metal extension included in the second transmitter. In some implementations, process 600 may further include, for each of the plurality of candidate combinations of orientations of the first emitter and the second emitter, determining a first distance between a leading edge of a via included in the first emitter (e.g., via 210) and a trailing edge of a via included in the second emitter, a second distance between a center of a via included in the first emitter and a center of a via included in the second emitter, and a third distance between a trailing edge of a via included in the first emitter and a leading edge of a via included in the second emitter.

As further shown in fig. 6, process 600 may include, for a layout of an array of emitters and from a plurality of candidate combinations of orientations of first emitters and orientations of second emitters, selecting a combination of orientations of the first emitters and orientations of the second emitters that minimizes the first distance, the second distance, and the third distance (block 620). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may select a combination of the orientation of the first emitter and the orientation of the second emitter that minimizes the first distance, the second distance, and the third distance for the layout of the array of emitters and from a plurality of candidate combinations of the orientation of the first emitter and the orientation of the second emitter.

Process 600 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and/or in conjunction with one or more other processes described elsewhere herein.

In some implementations, the process 600 may further include selecting the first transmitter as a seed (seed) in a group of transmitters, and determining the first distance, the second distance, and the third distance for each of a plurality of candidate combinations of orientations of the first transmitter and the second transmitter and with the orientation of the first transmitter in the plurality of candidate combinations fixed. In some implementations, the second emitter may be selected based on the second emitter being the closest un-optimized emitter to the first emitter. In some implementations, the process 600 may further include marking the orientation of the second emitter as optimized based on selecting a combination of the orientation of the first emitter and the orientation of the second emitter that minimizes the first distance, the second distance, and the third distance.

In some implementations, the process 600 may further include performing the techniques described above in connection with block 610 and 620 for other emitters in the group until the orientations of all emitters in the group are marked as optimized. In some embodiments, process 600 may further include, once all transmitters in the group are marked as optimized, determining a sum of all minimized first, second, and third distances for all transmitter combinations in the group.

In some implementations, the process 600 may further include, after determining the sum of all minimized first, second, and third distances for all combinations of transmitters in the group, rotating the first transmitter (e.g., the seed) and marking the orientation of the first transmitter as optimized, and repeating the techniques described above for blocks 610 and 620 for all transmitters in the group of transmitters until all transmitters are marked as optimized based on the modified orientation of the first transmitter. In some implementations, the process 600 may further include, once all emitters in the group are marked as optimized for the modified orientation of the first emitter, determining a sum of all minimized first, second, and third distances for all emitter combinations in the group. In some embodiments, the orientation (or rotation angle) of the first emitter resulting in the combination of the minimum or lowest first distance, second distance, and third distance may be an orientation optimization of the best case of the group of emitters. In some implementations, the process 600 may further include performing the techniques described above with respect to fig. 6 for other groups of transmitters in the array of transmitters.

In some embodiments, other figures of merit (figures of merit) may be used in addition to and/or in the alternative to the distance between the leading and trailing edges, such as radial width, shape, spacing, and/or other figures of merit.

Although fig. 6 shows example blocks of the process 600, in some implementations, the process 600 may include additional blocks, fewer blocks, different blocks, or a different arrangement of blocks than those depicted in fig. 6. Additionally, or alternatively, two or more blocks of process 600 may be performed in parallel.

Fig. 7 is a flow diagram of an example process 700 for optimizing a transmitter array layout. For example, fig. 7 illustrates an example process 700 for optimizing the layout of the transmitter array 200 described above. It is worthy to note that although the example process 700 is described in the context of optimizing the layout of the transmitter array 200, the implementations described with respect to the process 700 are equally applicable to other types of transmitter arrays. In some implementations, process 700 may be performed by an apparatus (e.g., apparatus 300 and/or another apparatus).

As shown in fig. 7, process 700 may include selecting a figure of merit associated with design parameters of an emitter array (block 710). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may select a figure of merit associated with a design parameter of an emitter array (e.g., emitter array 200). In some embodiments, the design parameters may include minimizing and/or eliminating overlap between different structure types between adjacent emitters (e.g., emitters 202) in the emitter array.

In some implementations, the figure of merit can include an area of overlap between structures of the same type in adjacent emitters of the array of emitters, such as trenches (e.g., trenches 204) in adjacent emitters, p-type metal extensions (e.g., p-type metal extensions 208) in adjacent emitters, vias (e.g., vias 210) in adjacent emitters, and so forth. In some implementations, the figure of merit can include a cost function associated with overlap between a trench of an emitter and a p-type metal extension and/or via of an adjacent emitter. In some implementations, the process 700 may include selecting a plurality of figures of merit for an array of emitters. In some embodiments, other figure of merit(s) may be used for trenches, p-type metal extensions and/or vias of adjacent emitters.

As further shown in fig. 7, the process 700 may include parameterizing the figure of merit as a function of one or more parameters of the transmitters included in the array of transmitters (block 720). For example, the apparatus (e.g., using processor 320, memory 330, storage 340, input 350, output 360, communication interface 370, and/or the like) may parameterize the figure of merit as a function of one or more parameters of the transmitters included in the array of transmitters. For example, the figure of merit may be parameterized as a function of the orientation (e.g., rotation angle) of the emitters in the emitter array (e.g., figure of merit (FoM) ═ f (θ)₁,θ₂,..θ_n) Wherein theta_iIs the orientation of the ith emitter). As another example, the figure of merit may be parameterized as a function of the size, shape, configuration, number, spacing, and/or the like of structures (e.g., trenches, p-type metal extensions, vias, and/or the like) in the emitter. In some embodiments, the figure of merit may be parameterized as a function of a plurality of parameters of the emitters included in the array of emitters.

As further shown in fig. 7, the process 700 may include solving an n-dimensional minimization function based on the parameterized figure of merit (block 730). For example, the apparatus (e.g., using the processor 320, the memory 330, the storage component 340, the input component 350, the output component 360, the communication interface 370, and/or the like) may solve the n-dimensional minimization function based on the parameterized figure of merit. In some embodiments, the n-dimensional minimization function may be an optimization function for the transmitter array layout. The n-dimension may correspond to the number of emitters included in the array of emitters. In some implementations, the n-dimensional minimization function can be a function of a parameterized figure of merit. In this case, solving the n-dimensional minimization function may include determining one or more parameters of the emitters included in the array of emitters that minimize a figure of merit (e.g., minimize overlap between different structure types in adjacent emitters and/or the like).

Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and/or in conjunction with one or more other processes described elsewhere herein.

Although fig. 7 shows example blocks of the process 700, in some implementations, the process 700 may include additional blocks, fewer blocks, different blocks, or a different arrangement of blocks than those shown in fig. 7. Additionally or alternatively, two or more blocks of process 700 may be performed in parallel.

The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementations to the precise form disclosed. Modifications and variations are possible in light of the above disclosure or may be acquired from practice of the implementations.

As used herein, the term "layer" is intended to be construed broadly as one or more layers and includes layers that are oriented horizontally, vertically, or at other angles.

Even if specific combinations of features are set forth in the claims and/or disclosed in the specification, these combinations are not intended to limit the disclosure of the various embodiments. In fact, many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various implementations includes a combination of each dependent claim with every other claim in the claim set.

No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more," and further, as used herein, the articles "the" are intended to include one or more items related to the article "the" and may be used interchangeably with "one or more," and further, as used herein, the term "combination" is intended to include one or more items (e.g., related items, unrelated items, combinations of related and unrelated items, etc.) and may be used interchangeably with "one or more. If only one item is intended, the phrase "only one" or similar language is used. Furthermore, as used herein, the terms "having" and the like are intended to be open-ended terms. Further, the phrase "based on" is intended to mean "based, at least in part, on" unless explicitly stated otherwise. Further, as used herein, the term "or" when used in a series is intended to be inclusive and may be used interchangeably with "and/or" unless specifically stated otherwise (e.g., if used in conjunction with "either" or "only one of").

Related applications

This application claims priority from U.S. provisional patent application No.62/831,513 entitled "optiming applicant opportunity tofaximize EMITTER DENSITY opportunity" filed on 9.4.2019 and U.S. provisional patent application No.62/835,791 entitled "optiming applicant lay WITHIN AN ARRAY FOR DENSELYPACKET ARRAY DESIGN" filed on 18.4.2019, and is a partial continuation of U.S. patent application No.16/383,753 entitled "EMITTER ARRAY WITH SHARED VIA TO AN am mic METAL SHARED twoeynad opportunity issues" filed on 25.3.2019, which claims priority from U.S. provisional patent application No.62/649,366 entitled "INTERSTITIAL VIAFOR HIGH DENSITY VERTICAL CAVITY rfa rf accettting LASER (VCSEL) opportunity" filed on 28.3.2018.3.28, all of which are incorporated herein by reference in their entirety.