阅读说明：本技术 衬底、半导体器件及半导体器件的制作方法 (Substrate, semiconductor device and manufacturing method of semiconductor device ) 是由 杨国文 赵勇明 杨皓宇 赵卫东 于 2020-06-30 设计创作，主要内容包括：本申请公开了一种衬底、半导体器件及半导体器件的制作方法,涉及半导体的技术领域。本申请的衬底的材料为In<Sub>x</Sub>Ga<Sub>1-x</Sub>As,其中0<x<1。故本申请通过在衬底内加入In元素,不仅改善了衬底的机械强度,而且从衬底上将晶格常数接近有源区的量子阱内的InGaAs材料,降低了有源区与衬底的晶格失配率,可以有效的降低外延片的应力,从而提高了半导体器件的质量,提高了半导体器件性能及可靠性。(The application discloses a substrate, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors. The material of the substrate of the present application is In x Ga 1‑x As, wherein 0<x<1. Therefore, the In element is added into the substrate, so that the mechanical strength of the substrate is improved, the lattice constant of the InGaAs material In the quantum well close to the active region on the substrate is reduced, the lattice mismatch rate of the active region and the substrate is reduced, the stress of an epitaxial wafer can be effectively reduced, the quality of a semiconductor device is improved, and the performance and the reliability of the semiconductor device are improved.)

1. A substrate applied to a semiconductor laser is characterized In that the substrate is made of In_xGa_1-xAs, wherein, 0<x<1。

2. A semiconductor device comprising the substrate of claim 1, and an epitaxial layer disposed on the substrate, the epitaxial layer comprising an active region having a quantum well material of InGaAs.

3. The semiconductor device according to claim 2, wherein the epitaxial layer comprises a first confinement layer, a first waveguide layer, the active region, a second waveguide layer, a second confinement layer, and an ohmic contact layer, which are sequentially stacked.

4. The semiconductor device according to claim 3, wherein the material of the ohmic contact layer is InGaAs; the material of the first limiting layer is (InAl) GaAs or (Al) GaInP; the material of the second limiting layer is (InAl) GaAs or (Al) GaInP; the first waveguide layer is made of (Al) GaAs, and the second waveguide layer is made of (Al) GaAs.

5. The semiconductor device according to claim 4, wherein In is a material of the substrate_xGa_1-xIn As, 0<x<0.4；

The material of the ohmic contact layer is In_mGa_1-mAs, wherein 0<m<0.4；

The material of the first limiting layer is In_aAl_bGa_1-a-bAs or Al_cGa_dIn_1-c-dP, wherein 0<a<1，0<b<1，0<c<1，0<d<1；

The material of the second limiting layer is In_eAl_fGa_1-e-fAs or Al_gGa_hIn_1-g-hP, wherein 0<e<1，0<f<1，0<g<1，0<h<1；

The first waveguide layer is made of Al_nGa_1-nAs, wherein 0<n<0.4；

The second waveguide layer is made of Al_kGa_1-kAs, wherein 0<k<0.4。

6. A method for manufacturing a semiconductor device, comprising:

providing a substrate;

growing an epitaxial layer on the substrate;

wherein the substrate is made of In_xGa_1-xAs, wherein, 0<x<1。

7. The method for manufacturing a semiconductor device according to claim 6, wherein the epitaxial layer comprises a first confinement layer, a first waveguide layer, an active region, a second waveguide layer, a second confinement layer, and an ohmic contact layer;

the growing an epitaxial layer on the substrate comprises:

placing the substrate in a reaction apparatus;

the reaction equipment is in a preset temperature and a preset pressure;

and sequentially growing the first limiting layer, the first waveguide layer, the active region, the second waveguide layer, the second limiting layer and the ohmic contact layer on the substrate.

8. The method of claim 7, wherein the quantum well material of the active region is InGaAs.

9. The method for manufacturing a semiconductor device according to claim 7, wherein the material of the ohmic contact layer is InGaAs; the material of the first limiting layer is (InAl) GaAs or (Al) GaInP; the material of the second limiting layer is (InAl) GaAs or (Al) GaInP; the first waveguide layer is made of (Al) GaAs, and the second waveguide layer is made of (Al) GaAs.

10. The method for manufacturing a semiconductor device according to claim 9, wherein In is a material of the substrate_xGa_1-xIn As, 0<x<0.4；

The material of the ohmic contact layer is In_mGa_1-mAs, wherein 0<m<0.4；

The material of the first limiting layer is In_aAl_bGa_1-a-bAs or Al_cGa_dIn_1-c-dP, wherein 0<a<1，0<b<1，0<c<1，0<d<1；

The material of the second limiting layer is In_eAl_fGa_1-e-fAs or Al_gGa_hIn_1-g-hP, wherein 0<e<1，0<f<1，0<g<1，0<h<1；

The first waveguide layer is made of Al_nGa_1-nAs, wherein 0<n<0.4；

The second waveguide layer is made of Al_kGa_1-kAs, wherein 0<k<0.4。

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a substrate, a semiconductor device, and a method for manufacturing a semiconductor device.

Background

Laser with 1064nm waveband is widely applied to military fields such as ranging, guidance and interference, and high-tech fields such as coherent communication, atmospheric research, medical instruments, optical image processing, laser printers and the like. The InGaAs/GaAs strained quantum well laser with the lasing wavelength of 1064nm can be used as a more appropriate laser source instead of the original solid laser due to its advantages of small size, high photoelectric conversion efficiency, convenient modulation, low price and the like.

Disclosure of Invention

The invention aims to provide a substrate, a semiconductor device and a manufacturing method of the semiconductor device, which can reduce stress, improve the quality of the semiconductor device and enable the performance and the reliability of the semiconductor device to be better.

The embodiment of the application is realized as follows:

a substrate is applied to a semiconductor laser, and the substrate is made of InGaAs.

In one embodiment, the substrate is made of In_xGa_1-xAs, wherein 0<x<1。

In one embodiment, the substrate is made of In_xGa_1-xAs, wherein 0<x<0.4。

A semiconductor device comprising a substrate as described above, and an epitaxial layer disposed on the substrate, the epitaxial layer comprising an active region having a quantum well material of InGaAs.

In an embodiment, the epitaxial layer includes a first confinement layer, a first waveguide layer, the active region, a second waveguide layer, a second confinement layer, and an ohmic contact layer, which are sequentially stacked.

In one embodiment, the ohmic contact layer is made of InGaAs; the material of the first limiting layer is (InAl) GaAs or (Al) GaInP; the material of the second limiting layer is (InAl) GaAs or (Al) GaInP; the first waveguide layer is made of (Al) GaAs, and the second waveguide layer is made of (Al) GaAs.

In one embodiment, the substrate is made of In_xGa_1-xAs, wherein 0<x<0.4。

In one embodiment, the ohmic contact layer is made of In_mGa_1-mAs, wherein 0<m<0.4。

In one embodiment, the first confinement layer is made of In_aAl_bGa_1-a-bAs or Al_cGa_dIn_1-c-dP, wherein 0<a<1，0<b<1，0<c<1，0<d<1。

In one embodiment, the second confinement layer is made of In_eAl_fGa_1-e-fAs or Al_gGa_hIn_1-g-hP, wherein 0<e<1，0<f<1，0<g<1，0<h<1。

In an embodiment, the first waveguide layer is made of Al_nGa_1-nAs, wherein 0<n<0.4。

In an embodiment, the second waveguide layer is made of Al_kGa_1-kAs, wherein 0<k<0.4。

Wherein x, m, n and k may be equal or different. a. b, c, d, e, f, g and h may or may not be equal.

A method for manufacturing a semiconductor device includes:

providing a substrate;

growing an epitaxial layer on the substrate;

wherein the substrate is made of In_xGa_1-xAs, wherein 0<x<1。

In one embodiment, the epitaxial layer includes a first confinement layer, a first waveguide layer, an active region, a second waveguide layer, a second confinement layer, and an ohmic contact layer.

In one embodiment, the growing an epitaxial layer on the substrate includes:

placing the substrate in a reaction apparatus;

the reaction equipment is in a preset temperature and a preset pressure;

and sequentially growing the first limiting layer, the first waveguide layer, the active region, the second waveguide layer, the second limiting layer and the ohmic contact layer on the substrate.

In one embodiment, the quantum well material of the active region is InGaAs.

In one embodiment, the ohmic contact layer is made of InGaAs; the material of the first limiting layer is (InAl) GaAs or (Al) GaInP; the material of the second limiting layer is (InAl) GaAs or (Al) GaInP; the first waveguide layer is made of (Al) GaAs, and the second waveguide layer is made of (Al) GaAs.

In one embodiment, the substrate is made of In_xGa_1-xAs, wherein 0<x<0.4。

In one embodiment, the ohmic contact layer is made of In_mGa_1-mAs, wherein 0<m<0.4。

In one embodiment, the first confinement layer is made of In_aAl_bGa_1-a-bAs or Al_cGa_dIn_1-c-dP, wherein 0<a<1，0<b<1，0<c<1，0<d<1。

In one embodiment, the second confinement layer is made of In_eAl_fGa_1-e-fAs or Al_gGa_hIn_1-g-hP, wherein 0<e<1，0<f<1，0<g<1，0<h<1。

In an embodiment, the first waveguide layer is made of Al_nGa_1-nAs, wherein 0<n<0.4。

In an embodiment, the second waveguide layer is made of Al_kGa_1-kAs, wherein 0<k<0.4。

Wherein x, m, n and k may be equal or different. a. b, c, d, e, f, g and h may or may not be equal.

Compared with the prior art, the beneficial effect of this application is:

by adding In element into the substrate, the mechanical strength of the substrate is improved, the lattice constant of the InGaAs material In the quantum well close to the active region on the substrate is reduced, the lattice mismatch rate of the active region and the substrate is reduced, the stress of an epitaxial wafer can be effectively reduced, the quality of a semiconductor device is improved, and the performance and the reliability of the semiconductor device are improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

fig. 3 is a line graph illustrating lattice mismatch ratios for different substrate materials according to an embodiment of the present application.

Fig. 4 is a schematic flow chart illustrating a method for fabricating a semiconductor device according to an embodiment of the present application;

fig. 5 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present application.

Icon: 100-a semiconductor device; 110-a substrate; 120-an epitaxial layer; 121-a first confinement layer; 122 — a first waveguide layer; 123-an active region; 124-a second waveguide layer; 125-a second confinement layer; 126-ohmic contact layer.

Detailed Description

The terms "first," "second," "third," and the like are used for descriptive purposes only and not for purposes of indicating or implying relative importance, and do not denote any order or order.

Furthermore, the terms "horizontal", "vertical", "overhang" and the like do not imply that the components are required to be absolutely horizontal or overhang, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.

In the description of the present application, it should be noted that the terms "inside", "outside", "left", "right", "upper", "lower", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that are conventionally arranged when products of the application are used, and are used only for convenience in describing the application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the application.

In the description of the present application, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements.

The technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a semiconductor device 100 according to an embodiment of the present disclosure. A semiconductor device 100 includes a substrate 110 and an epitaxial layer 120 disposed on the substrate 110, wherein the semiconductor device 100 may be a semiconductor chip or a long-wavelength band laser having a lasing wavelength greater than 1000nm or more. In one embodiment, the semiconductor device 100 is a 1064nm laser.

Fig. 2 is a schematic structural diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The epitaxial layer 120 includes a first confinement layer 121, a first waveguide layer 122, an active region 123, a second waveguide layer 124, a second confinement layer 125, and an ohmic contact layer 126, which are sequentially stacked.

The material of the substrate 110 is InGaAs. The quantum well material of the active region 123 is InGaAs, and the ohmic contact layer 126 is InGaAs; the material of the first confinement layer 121 is (InAl) GaAs or (Al) GaInP; the material of the second confinement layer 125 is (InAl) GaAs or (Al) GaInP; the material of the first waveguide layer 122 and the material of the second waveguide layer 124 are both (Al) GaAs.

In the embodiment, the In element is added to the substrate 110, so that not only is the mechanical strength of the substrate 110 improved, but also the lattice mismatch ratio between the active region 123 and the substrate 110 is reduced by using the InGaAs material In the quantum well with the lattice constant close to the active region 123 on the substrate 110, and the stress of the epitaxial wafer can be effectively reduced, so that the quality of the semiconductor device 100 is improved, and the performance and the reliability of the semiconductor device 100 are improved.

Compared with the prior art that a large-strain quantum well material is obtained by a cooling growth mode or a strain compensation mode is adopted, the embodiment is easy to produce and manufacture, low in cost, capable of reducing the influence of strain on a material system in the semiconductor device 100, reducing the crystal defect rate of the semiconductor device 100, avoiding the influence on the migration of electrons and the service life of the device, even capable of expanding the wavelength of a laser, capable of relieving the problems of narrow growth window, high development difficulty of a growth process, difficult material growth, dislocation and various defects caused by stress release, device degradation and the like, and capable of reducing the negative influence on the luminous efficiency of the quantum well.

The thickness of the active region 123 and the thickness of the substrate 110 have no correlation, and in this embodiment, the thickness of the active region 123 is 0-100 nm, and the thickness of the substrate 110 is 350-600 μm.

The material of the substrate 110 is In_xGa_1-xAs, material of the substrate 110The In component content and the Ga component content In the material are related, and the proportion of the component content is x/(1-x), wherein 0<x<1, in this example, 0<x<0.4。

The material of the ohmic contact layer 126 is In_mGa_1-mAs, wherein 0<m<0.4. There is a relationship between the contents of the components in the material of the ohmic contact layer 126.

The material of the first confinement layer 121 is In_aAl_bGa_1-a-bAs or Al_cGa_dIn_1-c-dP, wherein 0<a<1，0<b<1，0<c<1，0<d<1. There is a relationship between the contents of the components in the material of the first confinement layer 121.

The material of the second confinement layer 125 is In_eAl_fGa_1-e-fAs or Al_gGa_hIn_1-g-hP, wherein 0<e<1，0<f<1，0<g<1，0<h<1. There is a relationship between the content of each component in the material of the second restriction layer 125.

The first waveguide layer 122 is made of Al_nGa_1-nAs, wherein 0<n<0.4. There is a relationship between the content of the components in the material of first waveguide layer 122.

The second waveguide layer 124 is made of Al_kGa_1-kAs, wherein 0<k<0.4. There is a relationship between the amounts of the components in the material of second waveguide layer 124.

Wherein x, m, n and k may be equal or different. a. b, c, d, e, f, g and h may or may not be equal. In one embodiment, the materials of the layers in the epitaxial layer 120 may be equal or different.

In one embodiment, x, m, n, and k are 0.1, 0.15, 0.2, 0.25, 0.3, or 0.35, etc. a. b, c, d, e, f, g, and h are 0.1, 0.15, 0.2, 0.25, 0.3, or 0.35, etc.

Fig. 3 is a line graph illustrating lattice mismatch ratios corresponding to different substrate 110 materials according to an embodiment of the present application. The stress of GaAs is regarded as the stress in the epitaxial layer 120 on the substrate 110 to be a certain value, so that the lattice mismatch ratio can be determined from x, resulting in a line graph.

Wherein x is In as the material of the substrate 110_xGa_1-xX, Mismatch to GaAs in As is the lattice Mismatch in PPm (parts per million) and is used to represent the effect of strain on the material system in semiconductor device 100.

The table below is a table of data corresponding to the line graphs (0< x < 1).

As shown In the above table and FIG. 3, the material In of the substrate 110_xGa_1-xThe relationship between the value of x in As and the lattice mismatch ratio remains substantially linear, with the value of x increasing As x increasesLarge, i.e., the more the In element is added, the lower the lattice mismatch ratio.

When the substrate 110 is applied to the laser device corresponding to fig. 2, when the materials of the layers in the epitaxial layer 120 are determined, the stress in the epitaxial layer 120 can be obtained, and the range of x can be set to be 0 to 0.4 in order to obtain a more appropriate lattice mismatch range according to the stress in the epitaxial layer 120.

Fig. 4 is a flowchart illustrating a method for manufacturing the semiconductor device 100 according to an embodiment of the present disclosure. The method may be used to fabricate a semiconductor device 100 as shown in fig. 1 or fig. 2. The method of manufacturing the semiconductor device 100 may include the steps of:

step 201: a substrate 110 is provided.

The material of the substrate 110 In this step is In_xGa_1-xAs, wherein 0<x<0.4。

Step 202: an epitaxial layer 120 is grown on the substrate 110.

This step epitaxially grows an epitaxial layer 120 on the substrate 110. The substrate 110 is doped N-type or P-type, and the epitaxial layer 120 is doped N-type or P-type.

Fig. 5 is a flowchart illustrating a method for manufacturing the semiconductor device 100 according to an embodiment of the present disclosure. The method may be used to fabricate a semiconductor device 100 as shown in fig. 1 or fig. 2. The method of manufacturing the semiconductor device 100 may include the steps of:

step 301: a substrate 110 is provided.

The substrate 110 in this step may be directly obtained as a finished product or may be prepared. When the substrate 110 is prepared, an In element may be first doped In a GaAs solution In a certain amount In proportion to form an InGaAs alloy solution, and the InGaAs single crystal substrate 110 may be pulled through a single crystal furnace. Compared with the GaAs substrate in the prior art, the InGaAs single crystal substrate 110 not only improves the mechanical strength, but also is a substrate material with small mismatch with the quantum well InGaAs material of the active region 123, improves the material quality of the epitaxial growth strain InGaAs quantum well, improves the gain characteristic of the quantum well, and improves the performance of the semiconductor device.

Lining in this stepThe material of the bottom 110 is In_xGa_1-xAs, wherein 0<x<0.4。

Step 302: the substrate 110 is placed in a reaction apparatus.

The reaction apparatus in this step may be an MOCVD (Metal-organic Chemical Vapor Deposition) apparatus.

Step 303: the reaction apparatus is brought to a preset temperature and a preset pressure.

The preset pressure in the step is 50-100 mbar (millibar), and the preset temperature is 500-800 ℃. Controlling the temperature of the reaction equipment within a preset temperature range, controlling the pressure within a preset pressure range, and preparing for epitaxial growth.

Step 304: a first confinement layer 121, a first waveguide layer 122, an active region 123, a second waveguide layer 124, a second confinement layer 125, and an ohmic contact layer 126 are sequentially grown on the substrate 110.

In this step, the quantum well material of the active region 123 is InGaAs, and the material of the first confinement layer 121 is (InAl) GaAs or (Al) GaInP. The material of the second confinement layer 125 is (InAl) GaAs or (Al) GaInP. The material of the first waveguide layer 122 and the material of the second waveguide layer 124 are both (Al) GaAs.

In this step, the material of the ohmic contact layer 126 is In_mGa_1-mAs, wherein 0<m<0.4。

After the epitaxial growth is finished, a non-conductive film is grown through a CVD (Chemical vapor deposition) device at a temperature of about 200-400 ℃, a functional pattern is formed on the non-conductive film to form an electrical injection window, a P-type metal electrode is formed on the electrical injection window, the P-type metal electrode can be thickened through an electroplating (plating) electrochemical method, the back surface (the surface without the epitaxial layer 120) of the substrate 110 is thinned to a certain thickness by using a grinding and polishing technology, back surface metal preparation is performed through an evaporation or sputtering method to form a metal layer on the back surface of the substrate 110, and finally, the semiconductor device 100 is prepared through rapid annealing (RTA) annealing.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.