阅读说明：本技术 光学芯片 (Optical chip ) 是由 沈志强 于 2020-05-06 设计创作，主要内容包括：本申请公开了一种光学芯片,包括基底,所述基底上形成有第一外延结构层,所述第一外延结构层包括第一区域和第二区域,所述第一区域用于形成第一光学元件,所述第二区域上形成有刻蚀阻挡层,所述刻蚀阻挡层上形成有第二外延结构层,所述第二外延结构层用于形成第二光学元件,所述第一光学元件与所述第二光学元件电气隔离,所述第一光学元件和所述第二光学元件中的其中一个为垂直腔面发射激光器,另一个为光探测器。上述方案,在同一基底上集成了垂直腔面发射激光器和光探测器,提高了集成化,有利于使用其的系统做到更进一步的小型化。(The application discloses optical chip, including the basement, be formed with first epitaxial structure layer on the basement, first epitaxial structure layer includes first region and second region, first region is used for forming first optical element, be formed with the etching barrier layer on the second region, be formed with second epitaxial structure layer on the etching barrier layer, second epitaxial structure layer is used for forming second optical element, first optical element with second optical element electrical isolation, first optical element with one of them is vertical cavity surface emitting laser in the second optical element, and another is photodetector. According to the scheme, the vertical cavity surface emitting laser and the optical detector are integrated on the same substrate, so that the integration is improved, and the system using the vertical cavity surface emitting laser and the optical detector is further miniaturized.)

1. An optical chip is characterized by comprising a substrate, wherein a first epitaxial structure layer is formed on the substrate and comprises a first region and a second region, the first region is used for forming a first optical element, an etching barrier layer is formed on the second region, a second epitaxial structure layer is formed on the etching barrier layer and is used for forming a second optical element, the first optical element is electrically isolated from the second optical element, one of the first optical element and the second optical element is a vertical cavity surface emitting laser, and the other one of the first optical element and the second optical element is a photodetector.

2. The optical chip according to claim 1, wherein the material of the etch stop layer comprises at least any one of gallium indium phosphide, indium gallium arsenic phosphide and aluminum gallium indium phosphide.

3. The optical chip according to claim 1 or 2, wherein the etch stop layer has a thickness greater than 1-1000 nm.

4. An optical chip according to claim 1 or 2, wherein the first region and the second region are provided adjacent to a trench or an ion implantation region extending to the substrate.

5. The optical chip according to claim 1 or 2, wherein the VCSEL includes a first reflector layer, a light emitting layer, and a second reflector layer arranged in a stack;

one of the first reflector layer and the second reflector layer is an N-type reflector layer, and the other is a P-type reflector layer.

6. The optical chip of claim 5, wherein the first reflector layer and the second reflector layer are at least one of Bragg reflector layers and high contrast grating layers.

7. The optical chip of claim 5, wherein the light emitting layer comprises an active layer and an oxide layer disposed in a stack, one of the active layer and the oxide layer being connected to the N-type reflector layer and the other being connected to the P-type reflector layer;

the oxide layer comprises an unoxidized region and an oxidized region disposed around the unoxidized region, the unoxidized region being used to define a laser exit window.

8. The optical chip of claim 5, wherein the light emitting layer comprises an active layer and two oxide layers stacked on top of each other, the active layer being located between the two oxide layers, one of the oxide layers being connected to the N-type reflector layer and the other of the oxide layers being connected to the P-type reflector layer;

each of the oxide layers includes an unoxidized region and an oxidized region disposed around the unoxidized region, the unoxidized region being for defining a laser exit window.

9. The optical chip according to claim 1 or 2, wherein the photodetector comprises a first doped layer, an absorption layer and a second doped layer arranged in a stack;

one of the first doped layer and the second doped layer is a P doped layer, and the other is an N doped layer.

10. The optical chip of claim 9, wherein the P-doped layer is a P-doped gaas layer or a P-doped Al layer_xGaAs layer, N-doped layer is N-type doped GaAs layer or N-type doped Al_xA GaAs layer, the absorption layer is intrinsic Al_xGa_1-xAn As layer, wherein x is 0-0.3.

Technical Field

The invention relates to the technical field of lasers, in particular to an optical chip.

Background

A Vertical-Cavity Surface-Emitting Laser (VCSEL) is a semiconductor Laser with a novel structure that emits Laser light from a Surface perpendicular to a substrate. The vertical cavity surface emitting laser may be used in cooperation with a photodetector, the vertical cavity surface emitting laser, and the photodetector sensing laser light emitted from the vertical cavity surface emitting laser. At present, the vertical cavity surface emitting laser and the optical detector are independent from each other, which is not beneficial to the integration and further miniaturization of the system.

Disclosure of Invention

It is desirable to provide an optical chip for improving integration and miniaturization.

The invention provides an optical chip which comprises a substrate, wherein a first epitaxial structure layer is formed on the substrate and comprises a first area and a second area, the first area is used for forming a first optical element, an etching barrier layer is formed on the second area, a second epitaxial structure layer is formed on the etching barrier layer and used for forming a second optical element, the first optical element is electrically isolated from the second optical element, one of the first optical element and the second optical element is a vertical cavity surface emitting laser, and the other one of the first optical element and the second optical element is a photodetector.

As an implementable manner, the material of the etching barrier layer includes at least any one of gallium indium phosphide, indium gallium arsenic phosphide and aluminum gallium indium phosphide.

As a practical matter, the etch stop layer has a thickness greater than 20 nm.

As an implementable manner, the first region and the second region are provided adjacent to a trench or ion implantation region extending to the substrate.

In an implementable manner, the vertical cavity surface emitting laser includes a first reflector layer, a light emitting layer, and a second reflector layer which are stacked;

one of the first reflector layer and the second reflector layer is an N-type reflector layer, and the other is a P-type reflector layer.

As an implementation, the first reflector layer and the second reflector layer are at least one of bragg reflector layers and high-contrast grating layers.

As an implementable manner, the light emitting layer includes an active layer and an oxide layer which are arranged in a stack, one of the active layer and the oxide layer is connected with the N-type reflector layer, and the other is connected with the P-type reflector layer;

the oxide layer comprises an unoxidized region and an oxidized region disposed around the unoxidized region, the unoxidized region being used to define a laser exit window.

In an implementation manner, the light emitting layer comprises an active layer and two oxide layers which are stacked, the active layer is located between the two oxide layers, one of the oxide layers is connected with the N-type reflector layer, and the other oxide layer is connected with the P-type reflector layer;

each of the oxide layers includes an unoxidized region and an oxidized region disposed around the unoxidized region, the unoxidized region being for defining a laser exit window.

As an implementation manner, the light detector comprises a first doping layer, an absorption layer and a second doping layer which are stacked;

one of the first doped layer and the second doped layer is a P doped layer, and the other is an N doped layer.

The P-doped layer is a P-type doped gallium arsenide layer or a P-type doped Al layer_xGaAs layer, N-doped layer is N-type doped GaAs layer or N-type doped Al_xA GaAs layer, the absorption layer is intrinsic Al_xGa_1-xAn As layer, wherein x is 0-0.3.

According to the scheme, the vertical cavity surface emitting laser and the optical detector are integrated on the same substrate, so that the integration is improved, and the system using the vertical cavity surface emitting laser and the optical detector is further miniaturized.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1-7 are schematic diagrams illustrating a manufacturing process of an optical chip according to an embodiment of the invention;

FIG. 8 is a schematic diagram of another optical chip according to an embodiment of the present invention,

FIGS. 9-15 are schematic diagrams illustrating a process for fabricating another optical chip according to an embodiment of the present invention;

FIG. 16 is a schematic diagram illustrating a structure of another optical chip according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of another optical chip according to an embodiment of the present invention.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

As shown in fig. 1 to 7, an embodiment of the present invention provides an optical chip, which includes a substrate 1, wherein a first epitaxial structure layer is formed on the substrate 1, the first epitaxial structure layer includes a first region a and a second region B, the first region a is used for forming a first optical element, an etching stop layer is formed on the second region B, a second epitaxial structure layer is formed on the etching stop layer, the second epitaxial structure layer is used for forming a second optical element, the first optical element is electrically isolated from the second optical element, one of the first optical element and the second optical element is a vertical cavity surface emitting laser 22, and the other is a photodetector 23.

The material of the substrate 1 is, for example, but not limited to, a GaAs substrate 1.

Here, the etching barrier layer is formed on the second region B, the etching barrier film 7 outside the second region B may be removed on the first epitaxial structure layer by depositing the etching barrier film 7, and the etching barrier film 7 in the second region B is only remained by etching and other processes, so that the etching barrier film 7 in the second region B is the etching barrier layer.

And a second epitaxial structure layer is formed on the etching barrier layer, a second epitaxial structure film can grow on the etching barrier film 7, the second epitaxial structure film completely covers the etching barrier film 7, the second epitaxial structure film outside the second area B is removed through an etching process, only the second epitaxial structure film in the second area B is reserved, and the second epitaxial structure film in the second area B is the second epitaxial structure layer. By arranging the etching barrier film 7, when the second epitaxial structure film outside the second region B is removed by etching, the first epitaxial structure layer is prevented from being etched accidentally, and in addition, the second epitaxial structure film can also be used as the substrate 1 for growing the second epitaxial structure film.

In the above-described scheme, the vertical cavity surface emitting laser 22 and the photodetector 23 are integrated on the same substrate 1, so that the integration is improved, and further miniaturization of a system using the same is facilitated.

In a preferred implementation, the first optical element is a VCSEL 22 and the second optical element is a photodetector 23, and this arrangement can effectively reduce the overall height of the optical chip (i.e., the top-bottom direction in FIG. 1).

Of course, in another implementation, as shown in fig. 17, the first optical element is a photodetector 23 and the second optical element is a vertical cavity surface emitting laser 22.

As a practical way, the material of the etching barrier layer includes at least any one of InGaP, InGaAsP and AlGaInP, which can prevent the first epitaxial structure film from being etched accidentally when the second epitaxial structure film outside the second region B is etched.

As a practical way, the thickness of the etching barrier layer is larger than 20nm, which can prevent the first epitaxial structure film from being etched accidentally when the second epitaxial structure film outside the second region B is etched.

As an implementable manner, the first region a and the second region B are provided adjacent to a trench or ion implantation region extending to the substrate 1, by which provision of the trench or ion implantation region an electrical isolation of the first optical element from the second optical element is achieved.

As an implementable manner, the vertical cavity surface emitting laser 22 includes a first reflector layer, a light emitting layer, and a second reflector layer which are stacked; one of the first reflector layer and the second reflector layer is an N-type reflector layer, and the other is a P-type reflector layer.

In this example, the N-type reflector layer is located above, i.e., on the light-emitting side of the laser, and the quality of the laser beam can be improved due to the low resistance of the N-type reflector layer.

In an implementation manner, the first Reflector layer and the second Reflector layer are at least one of a bragg Reflector (DBR) and a High Contrast Grating (HCG). That is, the first reflector layer and the second reflector layer are both bragg reflectors, or the first reflector layer and the second reflector layer are both high-contrast gratings, or one of the first reflector layer and the second reflector layer is a high-contrast grating and the other is a bragg reflector.

As an realizable mode, the light-emitting layer comprises an active layer and an oxidation layer which are arranged in a stacked mode, one of the active layer and the oxidation layer is connected with the N-type reflector layer, and the other one of the active layer and the oxidation layer is connected with the P-type reflector layer; the oxide layer comprises an unoxidized area 25 and an oxidized area 24 arranged around the unoxidized area 25, the unoxidized area 25 being used to define the laser exit window. The oxidized region 24 is an insulating region for isolating current, and the unoxidized region 25 is a conductive region through which current is conducted after voltage is applied to electrodes at both ends of the vcsel thin film chip. The active layer is a Multiple Quantum Well (MQW) layer that emits light when energized. Of course, in some examples, the active layer may also be a single quantum well layer.

As an implementation mode, the light emitting layer comprises an active layer and two oxide layers which are arranged in a laminated mode, wherein the active layer is located between the two oxide layers, one oxide layer is connected with the N-type reflector layer, and the other oxide layer is connected with the P-type reflector layer; each oxide layer comprises an unoxidized area 25 and an oxidized area 24 arranged around the unoxidized area 25, the unoxidized area 25 being used to define the laser exit window.

In an implementation manner, the photodetector 23 includes a first doped layer, an absorption layer, and a second doped layer stacked in layers; one of the first doped layer and the second doped layer is a P doped layer, and the other is an N doped layer.

The P-doped layer is a P-type doped gallium arsenide layer or a P-type doped Al layer_xGaAs layer, N-doped layer is N-type doped GaAs layer or N-type doped Al_xGaAs layer and intrinsic Al as absorption layer_xGa_1-xAn As layer, wherein x is 0-0.3.

The following describes a method for manufacturing one of the optical chips by using one example. The "patterning process" described in the embodiments of the present invention includes processes of depositing a film, coating a photoresist, mask exposure, development, etching, and stripping a photoresist, and is a well-established manufacturing process in the related art. The "photolithography process" referred to in this embodiment includes coating film coating, mask exposure, and development, and is a well-established production process in the related art. The deposition may be performed by known processes such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by known coating processes, the etching may be performed by known methods, and the growth epitaxy may be performed by known methods, which are not particularly limited herein.

In the description of the present embodiment, it is to be understood that "thin film" refers to a layer of a material that is deposited, coated or grown on the substrate 1. The "thin film" may also be referred to as a "layer" if it does not require a patterning process or a photolithography process throughout the fabrication process. If a patterning process or a photolithography process is required for the "thin film" in the entire manufacturing process, the "thin film" is referred to as a "thin film" before the patterning process, and the "layer" after the patterning process. The "layer" after the patterning process or the photolithography process includes at least one "pattern".

S1: as shown in fig. 1, a substrate 1 is provided, and the material of the substrate 1 is, for example, but not limited to, a GaAs substrate 1.

And growing a first epitaxial structure layer film on the substrate 1, wherein the first epitaxial structure layer film comprises a plurality of layers of films. For example, the first epitaxial structure layer film includes a first DBR film 2, an active layer film 3, an oxide layer film 4, and a second DBR film 5 which are stacked. Each of the first DBR film 2 and the second DBR film 5 may be formed by stacking two materials having different refractive indexes of AlGaAs and GaAs, and the first DBR film 2 is N-type and the second DBR film 5 is P-type. The active layer film 3 at least comprises a multi-quantum well film which is stacked and is made of GaAs and AlGaAs, GaAsP, and InGaAs materials are stacked and arranged, and the active layer film 3 converts electric energy into optical energy. Of course, a single quantum well layer may also be employed in place of the multiple quantum well layer in some examples. The material of the oxide layer film 4 may be, but is not limited to, Al_xGa_1-xAs(x>0.9)。

And depositing an etching barrier film 7 on the first epitaxial structure layer film, wherein the material of the etching barrier film 7 can be gallium indium phosphide, and the thickness of the etching barrier film is more than 20 nm.

In some examples, between the first epitaxial structure layer film and the etching stopper film 7, a current spreading layer film 6 is also formed. The material of the current spreading layer film 6 is, for example, but not limited to, GaAs. The current spreading layer film 6 spreads the current flowing through the electrodes to the current spreading layer to improve the laser quality and performance of the VCSEL 22.

The growth of the second epitaxial structure layer film is performed on the etching stopper film 7. The second epitaxial structure layer film comprises a first doped layer film 8, an absorption layer film 9 and a second doped layer film 10 which are stacked. The material of the first doped layer film 8 can be a P-type doped gallium arsenide layer, the material of the second doped layer film 10 can be an N-type doped gallium arsenide layer, and the material of the absorption layer film 9 can be an intrinsic gallium arsenide layer.

S2: as shown in fig. 2, the etching barrier film 7 and the second epitaxial structure layer film above the first epitaxial structure layer film in the first region a are removed by a patterning process. Firstly, a protective layer is formed on a second epitaxial structure layer film, the protective layer is photoetched to form a patterned protective layer, the patterned protective layer exposes the second epitaxial structure layer film of a first area A, the second epitaxial structure layer film of the first area A is etched until the etching barrier film 7 is etched, then etching liquid is replaced to etch the etching barrier film 7 of the first area A, when the second epitaxial structure layer film is etched, the adopted etching liquid is ineffective to etch the etching barrier film 7, namely the etching barrier film 7 can not be etched, and similarly, the etching liquid for etching the etching barrier film 7 is ineffective to etch the first epitaxial structure layer film. The etching barrier layer and the second epitaxial structure layer are formed through the process.

S3: as shown in fig. 3, the N electrode contact layer 11 of the photodetector 23 is formed through a patterning process. A protective layer may be formed over the structure formed in the previous step by chemical vapor deposition, electroplating, sputtering, evaporation, etc., and the protective layer may be made of a material such as, but not limited to, silicon nitride, silicon dioxide, etc. And photoetching the protective layer to form a patterned protective layer, etching the second epitaxial structure layer of the hollowed-out part of the patterned protective layer, and etching the first doping layer on the second epitaxial structure layer to form a groove, wherein the groove is, for example, but not limited to, a circular ring shape. The N electrode contact layer 11 of the photodetector 23 is formed at the bottom of the trench, and the first doping layer of the corresponding N electrode contact layer may form an ohmic contact by means of high temperature annealing.

S4: as shown in fig. 4, the P electrode contact layers 12, 13 of the vertical cavity surface emitting laser 22 and the photodetector 23 are formed by a patterning process. Forming a protective layer, which may be formed by chemical vapor deposition, electroplating, sputtering, evaporation, etc., and the material of the protective layer is, for example, but not limited to, silicon nitride, silicon dioxide, etc. And photoetching the protective layer to form a patterned protective layer, forming P electrode contact layers 12 and 13 at hollow parts in the patterned protective layer, enabling the P electrode contact layer 13 of the vertical cavity surface emitting laser 22 to be in ohmic contact with the current spreading layer in a high-temperature annealing mode, and enabling the P electrode contact layer 12 of the photodetector 23 to be in ohmic contact with the second doped layer.

S5: as shown in fig. 5, the N electrode contact layer 14 of the vertical cavity surface emitting laser 22 is formed through a patterning process. Forming a protective layer, which may be formed by chemical vapor deposition, electroplating, sputtering, evaporation, etc., and the material of the protective layer is, for example, but not limited to, silicon nitride, silicon dioxide, etc. Forming photoresist on the protective layer, carrying out exposure and development to form a photoresist pattern, etching the protective layer of the hollow part in the photoresist pattern, and then etching the first epitaxial structure to form a two-step structure on the first reflector layer, the active layer and the second reflector layer, wherein the first reflector layer forms a first step, and at least the active layer and the second reflector layer form a second step; it is understood that the size of the first reflector layer is larger than the size of the active layer and the second reflector layer, and the size of the active layer and the second reflector layer are the same. The N electrode contact layer 14 of the vcsel 22 is formed at the step of the first reflector layer, and the N electrode contact layer 14 and the first reflector layer may form an ohmic contact by high temperature annealing.

S6: as shown in fig. 6, the recess formed in the two-step structure formed by etching may be used as an oxidation trench, and an oxidation region 24 surrounding an unoxidized region 25 is formed in the oxidation trench from the oxidation trench by a wet oxidation process. The wet oxidation process, for example, 2L/min of nitrogen gas carrying water vapor at a certain temperature at 430 ℃ is used for selective wet oxidation, and the oxidation depth, i.e., the extension depth in the left-right direction in the figure, is controlled by time so as to form an oxidized region 24 on the oxidized layer, and the oxidized region 24 surrounds an unoxidized region 25 in the oxidized layer.

S7: as shown in FIG. 7, an insulating layer 18 is formed by a patterning process, the insulating layer 18 being made of a material such as, but not limited to, SiN, BCB, Al₂O₃ The insulating layer 18 is provided with openings for exposing the P-electrode contact layer and the N-electrode contact layer, and electrodes having corresponding patterns are formed in the openings. The P electrode contact layer corresponds to the P electrodes 17, 19, and the N electrode contact layer corresponds to the N electrodes 15, 16.

A trench 20 is formed between the vcsel 22 and the photodetector 23 to electrically isolate the vcsel 22 from the photodetector 23. Forming a protective layer, which may be formed by chemical vapor deposition, electroplating, sputtering, evaporation, etc., and the material of the protective layer is, for example, but not limited to, silicon nitride, silicon dioxide, etc. And photoetching the protective layer to form a patterned protective layer, and etching the hollow part in the patterned protective layer until the substrate 1 is etched.

Finally, the substrate 1 may be ground and polished.

In addition, each of the protective layers may be partially removed or completely removed according to the process requirements.

As another implementation, as shown in fig. 8, the main difference between the above implementations is that a proton implantation region 21 is formed on the first reflector layer between the vertical cavity surface emitting laser 22 and the photodetector 23 by means of proton implantation instead of the above trench to electrically isolate the vertical cavity surface emitting laser 22 from the photodetector 23.

As yet another implementation:

s21: as shown in fig. 9, a substrate 1 is provided, and the material of the substrate 1 is, for example, but not limited to, a GaAs substrate 1.

And growing a first epitaxial structure layer film on the substrate 1, wherein the first epitaxial structure layer film comprises a plurality of layers of films. For example, the first epitaxial structure layer film includes a first DBR film 2, an active layer film 3, an oxide layer film 4, and a second DBR film 5 which are stacked. Each of the first DBR film 2 and the second DBR film 5 may be composed of a stack of two materials of AlGaAs and GaAs, which have different refractive indices. The active layer film 3 includes at least a multi-quantum well film stacked and arranged, the multi-quantum well film is formed by stacking and arranging GaAs, AlGaAs, GaAsP and InGaAs materials, and the active layer film 3 is used for converting electric energy into optical energy. Of course, a single quantum well layer may also be employed in place of the multiple quantum well layer in some examples. The material of the oxide layer film 4 may be, but is not limited to, Al_xGa_1-xAs(x>0.9)。

And depositing an etching barrier film 7 on the first epitaxial structure layer film, wherein the material of the etching barrier film 7 can be gallium indium phosphide, and the thickness of the etching barrier film is more than 20 nm.

In some examples, between the first epitaxial structure layer film and the etching stopper film 7, a current spreading layer is also formed. The material of the current spreading layer is, for example, but not limited to, GaAs. The current spreading layer spreads the current flowing through the electrodes to the current spreading layer to improve the laser quality and performance of the VCSEL 22.

The growth of the second epitaxial structure layer film is performed on the etching stopper film 7. The second epitaxial structure layer film comprises a first doped layer film 8, an absorption layer film 9 and a second doped layer film 10 which are stacked. The material of the first doped layer film 8 can be a P-type doped gallium arsenide layer, the material of the second doped layer film 10 can be an N-type doped gallium arsenide layer, and the material of the absorption layer film 9 can be an intrinsic gallium arsenide layer.

S22: as shown in fig. 10, the etching barrier film 7 and the second epitaxial structure layer film above the first epitaxial structure layer film in the first region a are removed by a patterning process. Firstly, forming a protective layer on a second epitaxial structure layer film, photoetching the protective layer to form a patterned protective layer, exposing the second epitaxial structure layer film of a first area A by the patterned protective layer, etching the second epitaxial structure layer film of the first area A until the etching barrier film 7 is etched, then replacing etching liquid to etch the etching barrier film 7 of the first area A, and when etching the second epitaxial structure layer film, adopting the etching liquid to be ineffective for etching the etching barrier film 7, namely, not being capable of etching the etching barrier film 7, and also being ineffective for etching the first epitaxial structure layer film by the etching liquid for etching the etching barrier film 7. The etching barrier layer and the second epitaxial structure layer are formed through the process.

S23: as shown in fig. 11, an N electrode contact layer of the photodetector 23 is formed through a patterning process. A protective layer may be formed over the structure formed in the previous step by chemical vapor deposition, electroplating, sputtering, evaporation, etc., and the protective layer may be made of a material such as, but not limited to, silicon nitride, silicon dioxide, etc. And photoetching the protective layer to form a patterned protective layer, etching the second epitaxial structure layer of the hollowed-out part of the patterned protective layer, and etching the first doping layer on the second epitaxial structure layer to form a groove, wherein the groove is, for example, but not limited to, a circular ring shape. An N electrode contact layer of the photodetector 23 is formed at the bottom of the trench, and the first doping layer of the corresponding N electrode contact layer may form an ohmic contact by high temperature annealing.

S24: as shown in fig. 12, the P electrode contact layers of the vertical cavity surface emitting laser 22 and the photodetector 23 are formed by a patterning process. Forming a protective layer, which may be formed by chemical vapor deposition, electroplating, sputtering, evaporation, etc., and the material of the protective layer is, for example, but not limited to, silicon nitride, silicon dioxide, etc. And photoetching the protective layer to form a patterned protective layer, forming a P electrode contact layer at the hollow part in the patterned protective layer, enabling the P electrode contact layer of the vertical cavity surface emitting laser 22 to be in ohmic contact with the current spreading layer in a high-temperature annealing mode, and enabling the P electrode contact layer of the optical detector 23 to be in ohmic contact with the second doped layer.

S25: as shown in fig. 13, an oxide trench is formed and an oxide region 24 surrounding an unoxidized region 25 is formed inward from the oxide trench by a wet oxidation process within the oxide trench. The wet oxidation process, for example, 2L/min of nitrogen gas carrying water vapor at a certain temperature at 430 ℃ is used for selective wet oxidation, and the oxidation depth, i.e., the extension depth in the left-right direction in the figure, is controlled by time so as to form an oxidized region 24 on the oxidized layer, and the oxidized region 24 surrounds an unoxidized region 25 in the oxidized layer.

S26: as shown in FIG. 14, an insulating layer 18 is formed by a patterning process, the insulating layer 18 being made of a material such as, but not limited to, SiN, BCB, Al₂O₃ The insulating layer 18 is provided with openings for exposing the P-electrode contact layer and the N-electrode contact layer, and electrodes having corresponding patterns are formed in the openings. The P electrode contact layer corresponds to the P electrodes 17 and 19, and the N electrode contact layer corresponds to the N electrode 15.

As shown in FIG. 15, a trench 20 is formed between the VCSEL 22 and the photodetector 23 to achieve electrical isolation of the VCSEL 22 from the photodetector 23. Forming a protective layer, which may be formed by chemical vapor deposition, electroplating, sputtering, evaporation, etc., and the material of the protective layer is, for example, but not limited to, silicon nitride, silicon dioxide, etc. And photoetching the protective layer to form a patterned protective layer, and etching the hollow part in the patterned protective layer until the substrate 1 is etched.

And grinding and polishing the side of the substrate 1, which is far away from the first epitaxial structure layer, and forming an N electrode on the side, for example, forming a metal layer on the side serving as the N electrode 16 of the vertical cavity surface emitting laser 22 by metal evaporation, and forming ohmic contact between the N electrode 16 and the substrate 1 by high-temperature annealing.

Of course, as another embodiment, as shown in fig. 16, the main difference between the embodiments is that a proton implantation region 21 is formed on the epitaxial structure layer between the vertical cavity surface emitting laser 22 and the photodetector 23 by proton implantation instead of the trench described above to electrically isolate the vertical cavity surface emitting laser 22 and the photodetector 23.

It will be understood that any orientation or positional relationship indicated above with respect to the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," etc., is based on the orientation or positional relationship shown in the drawings and is for convenience in describing and simplifying the invention, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be considered limiting of the invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention herein disclosed is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.