阅读说明：本技术 一种基于电容阵列充放电的驱动系统 (Driving system based on capacitor array charging and discharging ) 是由 冯永茂 吴金祥 孙哲 徐秀知 王奕如 于 2019-01-10 设计创作，主要内容包括：本公开揭示了一种基于电容阵列充放电的驱动系统,包括：输入端充电功率变换模块、电容阵列、输出端放电功率变换模块、PWM模块和MCU主控模块。本公开克服了现有驱动系统中存在的输出电压、电流可调范围小、参数设置不灵活以及驱动电流的上升下降沿的波形线性度不够而导致系统有功功率下降的问题,通过利用电容阵列的高效率、快速充放电的特性灵活的匹配输入输出电压、电流,以实现输入电压、输出电压自适应和高峰值脉冲输出,满足大功率半导体激光器的驱动要求。(The present disclosure discloses a drive system based on capacitor array charge-discharge, including: the device comprises an input end charging power conversion module, a capacitor array, an output end discharging power conversion module, a PWM module and an MCU main control module. The method solves the problems that the active power of the system is reduced due to small adjustable range of output voltage and current, inflexible parameter setting and insufficient waveform linearity of rising and falling edges of driving current in the existing driving system, and realizes self-adaptation of input voltage and output voltage and high-peak pulse output by flexibly matching input and output voltage and current by utilizing the characteristics of high efficiency and rapid charge and discharge of a capacitor array so as to meet the driving requirement of a high-power semiconductor laser.)

1. A capacitive array charge-discharge based drive system, comprising: the charging power conversion module at the input end, the capacitor array, the discharging power conversion module at the output end, the PWM module and the MCU main control module;

the input end charging power conversion module comprises a system power supply and a charging power conversion principle circuit, wherein the charging power conversion principle circuit is used for carrying out voltage regulation processing on electric energy of the system power supply and converting the electric energy into electric energy suitable for being stored by the capacitor array;

the capacitor array comprises a plurality of capacitors connected in parallel and is used for storing the electric energy of the system power supply converted by the charging power conversion principle circuit;

the output end discharge power conversion module comprises a discharge power conversion principle circuit and a pulse driving load, wherein the discharge power conversion principle circuit is used for carrying out voltage regulation processing on the electric energy stored in the capacitor array and transmitting the electric energy to the pulse driving load;

the PWM module can generate a PWM modulation signal for driving the charging power conversion principle circuit and the discharging power conversion principle circuit;

the MCU master control module is used for collecting voltage and current signals of the input end charging power conversion module and the output end discharging power conversion module and outputting control signals for controlling the PWM module.

2. The driving system according to claim 1, wherein preferably, the charging power conversion principle circuit comprises a first MOSFET driving circuit and a first topology circuit; wherein the content of the first and second substances,

the input end of the first MOSFET driving circuit is electrically connected with the output end of the PWM module and the MCU main control module, and the output end of the first MOSFET driving circuit is electrically connected with the grids of the MOSFET transistors Q3 and Q4 and the first topology circuit and is used for receiving PWM signals output by the PWM module to drive the MOSFET transistors Q3 and Q4 to be switched on or switched off;

the first topology circuit comprises a Buck topology mode and a Boost topology mode.

3. The driving system of claim 1, wherein the output discharge power conversion principle circuit comprises a second MOSFET driving circuit and a second topology circuit; wherein the content of the first and second substances,

the input end of the second MOSFET driving circuit is electrically connected with the output end of the PWM module and the MCU main control module, and the output end of the second MOSFET driving circuit is electrically connected with the grids of the MOSFET tubes Q5, Q6, Q7 and Q8 and the first topology circuit and is used for receiving PWM signals output by the PWM module to drive the MOSFET tubes Q5, Q6, Q7 and Q8 to be switched on or switched off;

the second topology circuit comprises a Buck topology mode and a Boost topology mode.

4. The drive system of claim 1, wherein the PWM module comprises: the device comprises a sawtooth wave generating circuit, a signal modulating circuit and a comparing circuit; wherein the content of the first and second substances,

the output end of the sawtooth wave generating circuit is connected with the input end of the comparison circuit and can generate a sawtooth wave signal as an input signal for generating a PWM (pulse width modulation) signal;

the output end of the signal modulation circuit is connected with the input end of the comparison circuit and is used for outputting an error amplification signal;

and the comparison circuit is used for comparing the sawtooth wave signal with the error amplification signal to generate two paths of PWM (pulse width modulation) signals with the same frequency and the wrong phase.

5. The drive system according to claim 4, wherein the sawtooth wave generation circuit includes a first sawtooth wave generation unit and a second sawtooth wave generation unit; the first sawtooth wave generation unit comprises resistors R1, R2, R3, a capacitor C1 and a triode QW1, wherein a resistor R1 is connected with the base electrode of the triode QW1, the emitter electrode of the QW1 is connected with a VCC power supply after being connected with the resistor R2 and the resistor R3 in series, and the collector electrode of the QW1 is connected with the capacitor C1 and grounded together; the second sawtooth wave generating unit comprises resistors R4, R5, R6, a capacitor C2 and a triode QW2, wherein a resistor R4 is connected with the base of the triode QW2, the emitter of the QW2 is connected with the resistor R5 and the resistor R6 in series and then connected with a VCC power supply, and the collector of the QW2 is connected with the capacitor C2 and grounded together.

6. The drive system according to claim 4, wherein the signal modulation circuit includes a proportional amplification circuit and an error amplification circuit; the proportional amplifying circuit comprises an anti-phase proportional amplifying circuit and an in-phase proportional amplifying circuit, wherein the anti-phase proportional amplifying circuit is used for detecting and amplifying a current signal of a system power supply, and the in-phase proportional amplifying circuit is used for detecting and amplifying a current signal of a pulse driving load; the error amplifying circuit is electrically connected with the proportional amplifying circuit, and can compare an input signal preprocessed by the proportional amplifying circuit with an MCU reference signal and generate an error amplifying signal for correcting the duty ratio of the control pulse.

7. The driving system according to claim 6, wherein the inverting proportional amplifying circuit comprises resistors R1, R2, R3, R4, R5, R6, capacitors C1, C2, C3 and an operational amplifier OP 1; wherein, the non-inverting input terminal of the operational amplifier OP1 is respectively connected in series with the resistors R1, R2 and the capacitor C1, and the inverting input terminal is connected in series with the resistor R4; a resistance-capacitance network formed by a resistor R5 and a capacitor C2 is connected in series between the inverting input end and the output end of the operational amplifier OP 1; the output end of the operational amplifier OP1 is connected in series with the resistor R6 and the capacitor C3 through the resistor R3, respectively.

8. The driving system according to claim 6, wherein the in-phase proportional amplifying circuit comprises resistors R1, R2, R3, R4, R5, R6, capacitors C1, C2, C3 and an operational amplifier OP 2; the non-inverting input end of the operational amplifier OP2 is connected in series with the resistors R1 and R2 and the capacitor C1, and the inverting input end of the operational amplifier OP2 is connected in series with the resistor R4; the inverting input end and the output end of the operational amplifier OP2 are connected in series with a resistance-capacitance network formed by a resistor R5 and a capacitor C2; the output end of the operational amplifier OP2 is respectively connected in series with the resistor R6 and the capacitor C3 through the resistor R3.

9. The drive system according to claim 6, wherein the error amplification circuit includes resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, capacitors C1, C2, C3, and an operational amplifier OP 3; the non-inverting input end of the operational amplifier OP3 is respectively connected in series with the resistors R1 and R2, the inverting input end of the operational amplifier is sequentially connected in series with the resistors R3 and R5 and then grounded, and the resistor R4 is positioned between the resistors R3 and R5; a resistance-capacitance network formed by resistors R6 and R7 and capacitors C1 and C2 is connected in series between the inverting input end and the output end of the operational amplifier OP 3; the output end of the operational amplifier OP3 is connected in series with the resistor R9 and the capacitor C3 through the resistor R8, respectively.

10. The drive system according to claim 4, wherein the comparison circuit includes resistors R7, R8, R9, R10, and operational amplifiers OP4, OP 5; the non-inverting input ends of the operational amplifiers OP4 and OP5 are connected with the sawtooth wave generating circuit, and the inverting input ends are connected with the signal modulating circuit; the output end of the operational amplifier OP4 is connected in series with the resistors R7 and R8; the output end of the operational amplifier OP5 is connected in series with the resistors R9 and R10.

11. The driving system according to claim 1, wherein the energy conversion of the driving system comprises the following four modes according to the relationship between the rated voltage of the capacitor array and the system power voltage and the load driving voltage: KK. KT, TK and TT modes; and the K mode represents that the topological circuit is in a Buck mode, and the T mode represents that the topological circuit is in a Boost mode.

12. The driving system according to claim 1, further comprising any one of a hardware PWM module, a DCO-based PWM synthesis module, and a DCO-based PWM synthesis module, configured to detect voltage and current parameters of the input-side charging power conversion module, the capacitor array, and the output-side discharging power conversion module and output a PWM modulation signal when the MCU master control module cannot control the PWM module to output the PWM modulation signal.

Technical Field

The invention relates to a driving technology, in particular to a driving system based on capacitor array charging and discharging.

Background

The semiconductor laser has the characteristics of high photoelectric conversion efficiency, small volume, light weight, wide wavelength range, long service life, easiness in modulation and the like, and has wide application prospects in the fields of national defense, industry, biology, medicine, communication and the like. However, the conventional semiconductor laser driving device has a series of disadvantages: firstly, the adjustable output voltage and current change range is not large, and the parameter setting is not flexible enough; secondly, in a large-current pulse working mode, the waveform linearity of the rising and falling edges of the driving current is not enough, the effective working time of the laser within one pulse time is reduced, and the useful power of the whole system is reduced; thirdly, the large-power system is too large in size and high in cost due to the fact that a large-power switching power supply system needs to be selected and matched, difficulty in system integration is increased, and application scenarios of the large-power system are limited.

In addition to semiconductor lasers, there are many devices or apparatuses that require intermittent pulsed operation, and a small, high-performance, cost-controllable driving apparatus is required. The conventional driving method is to stabilize the output current by using a power MOSFET as a current control element and applying a negative feedback principle, but the conventional driving method is large in size, high in cost and low in system efficiency. Therefore, a driving device is needed, which can distribute power to a system according to average power under safe conditions, and realize pulse output or pulse current output through flexible configuration parameters, so that the system has the characteristics of miniaturization, low cost and high performance.

Disclosure of Invention

The invention aims to provide a capacitor array charge-discharge-based driving system, which can flexibly match input and output voltages and currents by utilizing the characteristics of high efficiency and quick charge-discharge of a capacitor array, realize the self-adaptation of the input voltage and the output voltage and the high-peak pulse output, output in a constant current mode, meet the driving requirement of a high-power semiconductor laser and output in a pulse mode, and meet other load requirements.

To achieve the above object, the technical solution of the present invention is described as follows:

a capacitive array charge-discharge based drive system, comprising: the charging power conversion module at the input end, the capacitor array, the discharging power conversion module at the output end, the PWM module and the MCU main control module;

the input end charging power conversion module comprises a system power supply and a charging power conversion principle circuit, wherein the charging power conversion principle circuit is used for carrying out voltage regulation processing on electric energy of the system power supply and converting the electric energy into electric energy suitable for being stored by the capacitor array;

the capacitor array comprises a plurality of capacitors connected in parallel and is used for storing the electric energy of the system power supply converted by the charging power conversion principle circuit;

the output end discharge power conversion module comprises a discharge power conversion principle circuit and a pulse driving load, wherein the discharge power conversion principle circuit is used for carrying out voltage regulation processing on the electric energy stored in the capacitor array and transmitting the electric energy to the pulse driving load;

the PWM module can generate a PWM modulation signal for driving the charging power conversion principle circuit and the discharging power conversion principle circuit;

the MCU master control module is used for collecting voltage and current signals of the input end charging power conversion module and the output end discharging power conversion module and outputting control signals for controlling the PWM module.

Preferably, the charging power conversion principle circuit comprises a first MOSFET driving circuit and a first topology circuit; wherein the content of the first and second substances,

the input end of the first MOSFET driving circuit is electrically connected with the output end of the PWM module and the MCU main control module, and the output end of the first MOSFET driving circuit is electrically connected with the grids of the MOSFET transistors Q3 and Q4 and the first topology circuit and is used for receiving PWM signals output by the PWM module to drive the MOSFET transistors Q3 and Q4 to be switched on or switched off;

the first topology circuit comprises a Buck topology mode and a Boost topology mode.

Preferably, the output end discharge power conversion principle circuit comprises a second MOSFET driving circuit and a second topology circuit; wherein the content of the first and second substances,

the input end of the second MOSFET driving circuit is electrically connected with the output end of the PWM module and the MCU main control module, and the output end of the second MOSFET driving circuit is electrically connected with the gates of the MOSFET tubes Q5, Q6, Q7 and Q8 and the second topology circuit and is used for receiving PWM signals output by the PWM module to drive the MOSFET tubes Q5, Q6, Q7 and Q8 to be switched on or switched off;

the second topology circuit comprises a Buck topology mode and a Boost topology mode.

Preferably, the PWM module includes: the device comprises a sawtooth wave generating circuit, a signal modulating circuit and a comparing circuit; wherein the content of the first and second substances,

the output end of the sawtooth wave generating circuit is connected with the input end of the comparison circuit and can generate a sawtooth wave signal as an input signal for generating a PWM (pulse width modulation) signal;

the output end of the signal modulation circuit is connected with the input end of the comparison circuit and is used for outputting an error amplification signal;

and the comparison circuit is used for comparing the sawtooth wave signal with the error amplification signal to generate two paths of PWM (pulse width modulation) signals with the same frequency and the wrong phase.

Preferably, the sawtooth wave generating circuit includes a first sawtooth wave generating unit and a second sawtooth wave generating unit; the first sawtooth wave generation unit comprises resistors R1, R2, R3, a capacitor C1 and a triode QW1, wherein a resistor R1 is connected with the base electrode of the triode QW1, the emitter electrode of the QW1 is connected with a VCC power supply after being connected with the resistor R2 and the resistor R3 in series, and the collector electrode of the QW1 is connected with the capacitor C1 and grounded together; the second sawtooth wave generating unit comprises resistors R4, R5, R6, a capacitor C2 and a triode QW2, wherein a resistor R4 is connected with the base of the triode QW2, the emitter of the QW2 is connected with the resistor R5 and the resistor R6 in series and then connected with a VCC power supply, and the collector of the QW2 is connected with the capacitor C2 and grounded together.

Preferably, the signal modulation circuit includes a proportional amplification circuit and an error amplification circuit; the proportional amplifying circuit comprises an anti-phase proportional amplifying circuit and an in-phase proportional amplifying circuit, wherein the anti-phase proportional amplifying circuit is used for detecting and amplifying a current signal of a system power supply, and the in-phase proportional amplifying circuit is used for detecting and amplifying a current signal of a pulse driving load; the error amplifying circuit is electrically connected with the proportional amplifying circuit, and can compare a current signal detected in the proportional amplifying circuit with an MCU given signal and generate an error amplifying signal for correcting the duty ratio of the control pulse.

Preferably, the inverting proportional amplifying circuit comprises resistors R1, R2, R3, R4, R5, R6, capacitors C1, C2, C3 and an operational amplifier OP 1; wherein, the non-inverting input terminal of the operational amplifier OP1 is respectively connected in series with the resistors R1, R2 and the capacitor C1, and the inverting input terminal is connected in series with the resistor R4; a resistance-capacitance network formed by a resistor R5 and a capacitor C2 is connected in series between the inverting input end and the output end of the operational amplifier OP 1; the output end of the operational amplifier OP1 is connected in series with the resistor R6 and the capacitor C3 through the resistor R3, respectively.

Preferably, the in-phase proportional amplifying circuit comprises resistors R1, R2, R3, R4, R5 and R6, capacitors C1, C2 and C3, and an operational amplifier OP 2; the non-inverting input end of the operational amplifier OP2 is connected in series with the resistors R1 and R2 and the capacitor C1, and the inverting input end of the operational amplifier OP2 is connected in series with the resistor R4; the inverting input end and the output end of the operational amplifier OP2 are connected in series with a resistance-capacitance network formed by a resistor R5 and a capacitor C2; the output end of the operational amplifier OP2 is respectively connected in series with the resistor R6 and the capacitor C3 through the resistor R3.

Preferably, the error amplifying circuit comprises resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, capacitors C1, C2, C3 and an operational amplifier OP 3; the non-inverting input end of the operational amplifier OP3 is respectively connected in series with the resistors R1 and R2, the inverting input end of the operational amplifier is sequentially connected in series with the resistors R3 and R5 and then grounded, and the resistor R4 is positioned between the resistors R3 and R5; a resistance-capacitance network formed by resistors R6 and R7 and capacitors C1 and C2 is connected in series between the inverting input end and the output end of the operational amplifier OP 3; the output end of the operational amplifier OP3 is connected in series with the resistor R9 and the capacitor C3 through the resistor R8, respectively.

Preferably, the comparison circuit includes resistors R7, R8, R9, R10 and operational amplifiers OP4, OP 5; the non-inverting input ends of the operational amplifiers OP4 and OP5 are connected with the sawtooth wave generating circuit, and the inverting input ends are connected with the signal modulating circuit; the output end of the operational amplifier OP4 is connected in series with the resistors R7 and R8; the output end of the operational amplifier OP5 is connected in series with the resistors R9 and R10.

Preferably, according to the relationship between the rated voltage of the capacitor array and the system power voltage and the load driving voltage, the energy conversion of the driving system includes the following four modes: KK. KT, TK and TT modes; and the K mode represents that the topological circuit is in a Buck mode, and the T mode represents that the topological circuit is in a Boost mode.

Preferably, the driving system further includes any one of a hardware PWM module, a digitally controlled oscillator application module, and a DCO-based PWM synthesis module, and is configured to detect voltage and current parameters of the input-side charging power conversion module, the capacitor array, and the output-side discharging power conversion module and output a PWM modulation signal when the MCU main control module cannot control the PWM module to output the PWM modulation signal.

Compared with the prior art, the beneficial effect that this disclosure brought does:

1. the self-adaption high-peak pulse output circuit utilizes the characteristics of high efficiency and quick charge and discharge of the capacitor array to flexibly match input and output voltages and currents, and realizes self-adaption of the input voltage and the output voltage and high-peak pulse output;

2. the output of the constant current mode and the pulse mode can be realized.

Drawings

Fig. 1 is a schematic structural diagram of a driving device based on charging and discharging of a capacitor array according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a general power conversion module according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an input terminal charging power variation module according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an output-side discharging power conversion module according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a PWM module according to an embodiment of the present invention;

FIG. 6 is a circuit diagram illustrating a sawtooth wave generation circuit according to an embodiment of the present invention;

FIG. 7 is a circuit diagram showing an inverse scale up circuit according to an embodiment of the present invention;

FIG. 8 is an in-phase scaling circuit diagram of an embodiment of the present invention;

FIG. 9 is a diagram of an error amplification circuit according to an embodiment of the present invention;

FIG. 10 is a circuit diagram of a comparison unit according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a general structure for charging and discharging based on a capacitor array according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a hardware PWM module according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a DCO application module according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of a DCO-based PWM synthesis module according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to fig. 1 to 14, which are only some embodiments and are not to be construed as limiting the present invention.

As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This specification and claims do not intend to distinguish between components that differ in name but not function. The description which follows is a preferred embodiment of the present application, but is made for the purpose of illustrating the general principles of the application and not for the purpose of limiting the scope of the application. The protection scope of the present application shall be subject to the definitions of the appended claims.

Aiming at the problems that the waveform linearity of the rising and falling edges of the driving current is not enough and the output voltage and current parameter setting are not flexible in the prior art, the driving system based on capacitor array charging and discharging is disclosed by the disclosure through double-gradient voltage regulation, the self-adaption of the input voltage and the output voltage and the high-peak pulse output can be realized, and the driving system can work in a constant-current output mode and a pulse output mode.

As shown in fig. 1, a driving system based on charging and discharging of a capacitor array includes: the charging power conversion module at the input end, the capacitor array, the discharging power conversion module at the output end, the PWM module and the MCU main control module;

the input end charging power conversion module comprises a system power supply and a charging power conversion principle circuit, wherein the charging power conversion principle circuit is used for carrying out voltage regulation processing on electric energy of the system power supply and converting the electric energy into electric energy suitable for being stored by the capacitor array;

the capacitor array comprises a plurality of capacitors connected in parallel and is used for storing the electric energy of the system power supply converted by the charging power conversion principle circuit;

the output end discharge power conversion module comprises a discharge power conversion principle circuit and a pulse driving load, wherein the discharge power conversion principle circuit is used for carrying out voltage regulation processing on the electric energy stored in the capacitor array and transmitting the electric energy to the pulse driving load;

the PWM module can generate a PWM modulation signal for driving the charging power conversion principle circuit and the discharging power conversion principle circuit;

the MCU master control module is used for collecting voltage and current signals of the input end charging power conversion module and the output end discharging power conversion module and outputting control signals for controlling the PWM module.

The above embodiments form a complete technical solution of the present disclosure, and the charging and discharging power conversion module is connected to the capacitor array, so as to implement dual-gradient voltage regulation, input voltage and output voltage adaptation, and high-peak pulse output, and can well solve the problems existing in the prior art that the waveform linearity of the rising and falling edges of the driving current is not sufficient, and the output voltage and current parameters are not flexible.

In another embodiment, as shown in fig. 2, fig. 2 is a general power conversion module, which includes a MOSFET driving circuit, a topology circuit and a switch selection circuit, the MOSFET driving circuit, the topology circuit and the switch selection circuit are sequentially electrically connected, an input end of the MOSFET driving circuit is electrically connected to an output end of a PWM module, an SP1 end of the switch selection circuit with a switch S1 is electrically connected to an input voltage, and an SP2 end is electrically connected to an output voltage, a drain of a MOSFET Q1 in the topology circuit is divided into two branches, one branch is connected in series with a capacitor C1 and then grounded, a VH end of the other branch is electrically connected to a 1 st end of the switch selection circuit with a switch S1, a source of Q1 and a drain of Q2 are electrically connected to a 1 end of an inductor L, a source of Q2 is grounded, a 2 end of an inductor L is divided into two branches, a branch is connected in series with a capacitor C2 and then grounded, and a V L end of the other branch is electrically connected to a 2 nd end of the switch selection circuit with a switch S1.

The universal power conversion module comprises two modes of a Buck topology and a Boost topology. The two modes in the above embodiment are described in detail below.

1. When the switch S1 is in the SP1 gear, the topology circuit is in the Buck topology mode, in which the input voltage is electrically connected to the VH terminal and the output voltage is electrically connected to the V L terminal, when the PWM is in the high level, the Q1 is turned on and the Q2 is turned off, the VH terminal voltage is directly applied to the 1 terminal of the inductor L, the V L0 is directly applied to the 2 terminal of the inductor L, because of the voltage difference between the terminals, a current is generated in the inductor L (the current in the inductor is proportional to the integral of the voltage at the terminals with respect to time), the current flows through the inductor L to charge the capacitor C L via the inductor L), when the PWM is in the low level, the Q L is turned off and the Q L is turned on, the 1 terminal of the inductor L is grounded, the 2 terminal of the inductor L is electrically connected to the V L terminal, because the current in the inductor L cannot change abruptly, the current direction still flows from the 1 terminal to the 2 terminal, the voltage at the inductor 3681 is merely reversed, the voltage at the inductor L is gradually reduced, the voltage at a frequency corresponding to the voltage of the inductor L, the V L, the ideal voltage at which the V L, the ideal voltage is generally reduced by changing the voltage of the V L, the equivalent of the V L, when the voltage at the ideal frequency of the V L, the ideal voltage is generally changing the equivalent frequency of the V L, the equivalent to the equivalent of the equivalent to the equivalent voltage of the equivalent to.

2. When the switch S1 is in the SP2 position, the topology circuit is in the Boost topology mode, the input voltage is electrically connected to the terminal V L, the output voltage is electrically connected to the terminal VH, during the low level period of the PWM signal, the Q1 is turned off, the Q2 is turned on, the voltage of V L is fully loaded to both terminals of the inductor L, and a current is generated in the inductor L1 (the current in the inductor is proportional to the time integral of the voltage across the inductor), during the high level period of the PWM signal, the Q1 is turned on, the Q2 is turned off, and since the current in the inductor cannot suddenly change, the current direction still flows from the terminal 2 to the terminal 1, but the voltage across the inductor L is reversed, the current in the inductor L is gradually reduced, the capacitor C1 is continuously charged, the process is repeated during each PWM high level period, the capacitor C1 9 is charged, the voltage across the capacitor C632 is gradually increased, the current in the inductor 638 is not reduced to the high level period, so that the inductor is continuously discharged, and the charging process of the inductor V L is continuously changed, and the charging process is changed to the VH V68692.

In another embodiment, as shown in fig. 3, the input charging power conversion module includes a system power supply and a charging power conversion principle circuit, wherein the charging power conversion principle circuit includes a first MOSFET driving circuit and a first topology circuit; the input end of the first MOSFET driving circuit is electrically connected with the output end of the PWM module and the MCU main control module, and the output end of the first MOSFET driving circuit is electrically connected with the gates of the MOSFET transistors Q3 and Q4 and the first topology circuit; the first topology circuit comprises a Buck topology mode and a Boost topology mode.

In this embodiment, the charging power conversion principle circuit is a simplified Buck topology when the switch S1 is electrically connected with the SP1 gear in the general power conversion module shown in fig. 2, a system power supply is connected to the VH side of the input-end charging power conversion module, and the capacitor array is connected to the V L side of the input-end charging power conversion module, so that the first gradient voltage regulation is realized.

It should be noted that the first MOSFET driver circuit employs a MOSFET driver MDR having a programmable dead time. The output end CMD-PWM of the PWM module is connected with a resistor R2 in series and then is electrically connected with Pin8 of the MDR; the output end CMD-EN of the MCU is connected in series with the resistor R3 and then is electrically connected with Pin 7 of the MDR; the Pin 6 of the MDR is connected with the resistor R4 in series and then grounded, and the size of the resistor R4 can determine the dead time of the output PWM; the VCC power supply is connected with a resistor R1 in series and then is divided into three branches, the first branch is connected with a parallel capacitor C1 and a capacitor C2 and then is grounded for filtering power supply ripples, the second branch is electrically connected with Pin 1 of the MDR, and the third branch is electrically connected with the anode of a diode D1; the Pin 2 of the MDR is connected with the cathode of the diode D1, and meanwhile, the Pin 2 is connected with the Pin4 after being connected with the capacitor C3; a resistor R6 is connected between Pin3 and Pin4 of the MDR in series; the Pin3 of the MDR is connected with the resistor R5 and then is connected with the gate of the Q3; the Pin 10 of the MDR is connected with the resistor R8 in series and then grounded, and the Pin 10 is connected with the resistor R7 and then connected with the gate of the Q4; both Pin 5 and Pin 9 of the MDR are grounded; the phase difference of the output signals of Pin3 and Pin 10 of the MDR is 180 degrees, so that the Q3 and the Q4 can be prevented from being simultaneously conducted, the power supply is prevented from being connected with the ground, and the instantaneous current is too large to burn out the circuit.

In another embodiment, as shown in fig. 4, the output end discharge power conversion module includes an output end discharge power conversion principle circuit and a pulse driving load; the output end discharge power conversion principle circuit comprises a second MOSFET driving circuit and a second topology circuit; the input end of the second MOSFET driving circuit is electrically connected with the output end of the PWM module and the MCU main control module, and the output end of the second MOSFET driving circuit is electrically connected with the gates of the MOSFET transistors Q5, Q6, Q7 and Q8 and the second topology circuit.

In this embodiment, the output end discharge power conversion principle circuit is a simplified Buck topology when a switch S1 in the general power conversion module shown in fig. 2 is electrically connected with a SP1 gear, a capacitor array is connected to a VH side of the input end charge power conversion module, and a pulse drive load is connected to a V L side of the capacitor array, so as to realize second gradient voltage regulation.

It should be understood that, like the first MOSFET driver circuit in the charging power conversion principle circuit, the second MOSFET driver circuit in this embodiment also employs a MOSFET driver MDR with a programmable dead time.

Specifically, the output end DRM-PWM of the PWM module is connected with a resistor R10 in series and then is electrically connected with Pin8 of the MDR; the output end DRM-EN of the MCU is connected with a resistor R11 in series and then is electrically connected with Pin 7 of the MDR; the Pin 6 of the MDR is connected with the resistor R12 in series and then grounded, and the size of the resistor R12 can determine the dead time of the output PWM; the VCC power supply is connected with a resistor R9 in series and then is divided into three branches, the first branch is connected with a parallel capacitor C6 and a capacitor C7 and then is grounded for filtering power supply ripples, the second branch is electrically connected with Pin 1 of the MDR, and the third branch is electrically connected with the anode of a diode D2; the Pin 2 of the MDR is connected with the cathode of the diode D2, and the Pin 2 is connected with the Pin4 after being connected with the capacitor C8; the Pin3 of the MDR is divided into three branches, the first branch is connected with the gate of the Q5 after being connected with a resistor R14, the second branch is connected with the gate of the Q7 after being connected with a resistor R13, and the third branch is connected with the Pin4 after being connected with a resistor R15; the Pin 10 of the MDR is divided into three branches, the first branch is connected with the gate of the Q6 after being connected with a resistor R17, the second branch is connected with the gate of the Q8 after being connected with a resistor R16, and the third branch is connected with the ground after being connected with a resistor R18; both Pin 5 and Pin 9 of the MDR are grounded; the phase difference of the output signals of Pin3 and Pin 10 of the MDR is 180 degrees, and the Q5 and Q7 can be prevented from being conducted with Q6 and Q8 at the same time, so that the situation that the power supply is connected with the ground and the instantaneous current is too large to burn out the circuit is avoided.

In another embodiment, as shown in fig. 5, the PWM module includes: the device comprises a sawtooth wave generating circuit, a signal modulating circuit and a comparing circuit; wherein the content of the first and second substances,

the output end of the sawtooth wave generating circuit is connected with the input end of the comparison circuit and can generate a sawtooth wave signal as an input signal for generating a PWM (pulse width modulation) signal;

the output end of the signal modulation circuit is connected with the input end of the comparison circuit and is used for outputting an error amplification signal;

and the comparison circuit is used for comparing the sawtooth wave signal with the error amplification signal to generate two paths of PWM (pulse width modulation) signals with the same frequency and the wrong phase.

In this embodiment, the comparison circuit receives the sawtooth wave signals output by the error amplification circuit and the sawtooth wave generation circuit, and outputs PWM modulation signals with the same frequency and the same phase by comparison. When the sawtooth wave signal and the reference signal of the MCU main control module are determined, the PWM modulation signal only changes along with the change of the input signal. When the system is just powered on, no input signal exists, the error amplification signal is the largest, so that the duty ratio of PWM is the smallest, the input signal is gradually increased, the error signal is gradually reduced, the duty ratio of PWM is also gradually increased by controlling the on-off time of the MOSFET, and finally the input signal is the same as the reference signal of the MCU main control module.

In another embodiment, as shown in fig. 6, the sawtooth wave generating circuit includes a first sawtooth wave generating unit and a second sawtooth wave generating unit; the first sawtooth wave generation unit comprises resistors R1, R2, R3, a capacitor C1 and a triode QW1, wherein a resistor R1 is connected with the base electrode of the triode QW1, the emitter electrode of the QW1 is connected with a VCC power supply after being connected with the resistor R2 and the resistor R3 in series, and the collector electrode of the QW1 is connected with the capacitor C1 and grounded together; the second sawtooth wave generating unit comprises resistors R4, R5, R6, a capacitor C2 and a triode QW2, wherein a resistor R4 is connected with the base of the triode QW2, the emitter of the QW2 is connected with the resistor R5 and the resistor R6 in series and then connected with a VCC power supply, and the collector of the QW2 is connected with the capacitor C2 and grounded together.

In this embodiment, the sawtooth wave generating circuit receives input Pulse signals CMD-Pulse and DRM-Pulse of the MCU main control module, and the phases of the two signals are 180 °. The CMD-Pulse signal is connected to the first sawtooth wave generating unit, and the DRM-Pulse signal is connected to the second sawtooth wave generating unit. During the low level period of the CMD-Pulse signal, the triode QW1 is turned off, VCC charges the capacitor C1 through the resistor R3, during the high level period of the CMD-Pulse signal, the triode QW1 is turned on, the capacitor C1 discharges through the resistor R2, and the charging time constant is larger than the discharging time constant through reasonably setting parameters (C1, R2 and R3), thereby synthesizing a first path of sawtooth wave; during the low level period of the DRM-Pulse signal, the transistor QW2 is turned off, and VCC charges the capacitor C2 through the resistor R6; during the high level period of the DRM-Pulse signal, the triode QW2 is conducted, the capacitor C2 discharges through the resistor R5, and the charging time constant is larger than the discharging time constant through reasonably setting parameters (C2, R5 and R6), so that a second path of sawtooth wave is synthesized.

In another embodiment, the signal modulation circuit includes: a proportional amplifier circuit and an error amplifier circuit; the proportional amplifying circuit comprises an anti-phase proportional amplifying circuit and an in-phase proportional amplifying circuit, wherein the anti-phase proportional amplifying circuit is used for detecting and amplifying a current signal of a system power supply, and the in-phase proportional amplifying circuit is used for detecting and amplifying a current signal of a pulse driving load; the error amplifying circuit is electrically connected with the proportional amplifying circuit, and can compare a current signal detected in the proportional amplifying circuit with an MCU given signal and generate an error amplifying signal for correcting the duty ratio of the control pulse.

In the embodiment, the signal modulation circuit is divided into two parts, wherein the first part comprises an inverse proportion amplification circuit connected with an error amplification circuit and used for carrying out signal modulation on the input end charging power conversion module; the second part comprises an in-phase proportion amplifying circuit connected with another error amplifying circuit and used for carrying out signal modulation on the output end discharge power conversion module. The first part is to generate a system power supply current signal and an error amplification signal of a reference signal input by the MCU main control module, form a PWM signal through a comparison unit, finally send the signal to the input end charging power conversion module, reduce the error amplification signal and finally enable the system power supply current signal to be the same as the reference signal; the second part is to generate a pulse driving load current signal and an error amplification signal of a reference signal input by the MCU main control module, form a PWM signal through the comparison unit, finally send the signal to the output end discharge power conversion module, reduce the error amplification signal, and finally enable the current signal of the pulse driving load to be the same as the reference signal.

In another embodiment, as shown in fig. 7, the inverting proportional amplifying circuit includes resistors R1, R2, R3, R4, R5, R6, capacitors C1, C2, C3, and an operational amplifier OP 1; wherein, the non-inverting input terminal of the operational amplifier OP1 is respectively connected in series with the resistors R1, R2 and the capacitor C1, and the inverting input terminal is connected in series with the resistor R4; a resistance-capacitance network formed by a resistor R5 and a capacitor C2 is connected in series between the inverting input end and the output end of the operational amplifier OP 1; the output end of the operational amplifier OP1 is connected in series with the resistor R6 and the capacitor C3 through the resistor R3, respectively.

In this embodiment, the inverse proportion amplifying circuit is used for detecting a current signal of the system power supply and performing accurate amplification, and can convert the detected current signal into an actual voltage signal and indirectly realize current detection by detecting voltage. It should be noted that, because the inverse proportion amplifying circuit adopts a differential structure, not only the voltage signal is accurately amplified, but also the common mode interference signal is suppressed.

In another embodiment, as shown in fig. 8, the in-phase proportional amplifying circuit includes resistors R1, R2, R3, R4, R5, R6, capacitors C1, C2, C3, and an operational amplifier OP 2; the non-inverting input end of the operational amplifier OP2 is connected in series with the resistors R1 and R2 and the capacitor C1, and the inverting input end of the operational amplifier OP2 is connected in series with the resistor R4; the inverting input end and the output end of the operational amplifier OP2 are connected in series with a resistance-capacitance network formed by a resistor R5 and a capacitor C2; the output end of the operational amplifier OP2 is respectively connected in series with the resistor R6 and the capacitor C3 through the resistor R3.

In this embodiment, the in-phase proportional amplifying circuit is configured to detect a current signal of the pulse-driven load and perform accurate amplification, convert the detected current signal into an actual voltage signal, and indirectly detect the current by detecting the voltage. It should be noted that, because the in-phase proportional amplifying circuit adopts a differential structure, not only the voltage signal is accurately amplified, but also the common-mode interference signal is suppressed.

In another embodiment, as shown in fig. 9, the error amplifying circuit includes resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, capacitors C1, C2, C3, and an operational amplifier OP 3; the non-inverting input end of the operational amplifier OP3 is respectively connected in series with the resistors R1 and R2, the inverting input end of the operational amplifier is sequentially connected in series with the resistors R3 and R5 and then grounded, and the resistor R4 is positioned between the resistors R3 and R5; a resistance-capacitance network formed by resistors R6 and R7 and capacitors C1 and C2 is connected in series between the inverting input end and the output end of the operational amplifier OP 3; the output end of the operational amplifier OP3 is connected in series with the resistor R9 and the capacitor C3 through the resistor R8, respectively.

In this embodiment, when the error amplifying circuit has no signal input and the MCU main control module has no reference signal, the input voltage at the non-inverting input terminal of the error amplifying circuit is very low, the input at the inverting input terminal is grounded, and the output of the error amplifying circuit is at a high level. When the MCU master control module adds a reference signal suddenly, the error signal is maximum, the output of the error amplifying circuit is rapidly reduced, the duty ratio of the PWM signal is increased, the preprocessed input signal is rapidly increased, and the preprocessed input signal is finally the same as the reference signal according to the rapid dynamic characteristic of a resistance-capacitance network formed by resistors R6 and R7 and capacitors C1 and C2. The dynamic characteristics can be changed by changing the parameters of (C1, C2, R7).

In another embodiment, as shown in fig. 10, the comparison circuit includes resistors R7, R8, R9, R10, operational amplifiers OP4, OP 5; the non-inverting input ends of the operational amplifiers OP4 and OP5 are connected with the sawtooth wave generating circuit, and the inverting input ends are connected with the signal modulating circuit; the output end of the operational amplifier OP4 is connected in series with the resistors R7 and R8; the output end of the operational amplifier OP5 is connected in series with the resistors R9 and R10.

In this embodiment, the two PWM modulation signals PWM-C (CMD-PWM) and PWM-D (DRM-PWM) output by the comparison circuit have a phase difference of 180 °, the duty ratio thereof changes with the error signal output by the signal modulation circuit, the change trend thereof is opposite to that of the input signal, a negative feedback structure is formed, and finally the feedback signal of the circuit is equal to the respective reference signal, thereby achieving a balanced state.

In another embodiment, fig. 11 is a schematic diagram of a general structure based on charging and discharging of a capacitor array. As shown in fig. 11, the SP5 terminal of the switch selection circuit with the switch S3 is electrically connected to the system power supply, the SP6 terminal is electrically connected to the capacitor array, the 1 st terminal is electrically connected to the SP1 terminal, and the 2 nd terminal is electrically connected to the SP2 terminal; the SP7 terminal of the switch selection circuit with the switch of S4 is electrically connected with the pulse driving load, the SP8 terminal is electrically connected with the capacitor array, the 1 st terminal is electrically connected with the SP3 terminal, and the 2 nd terminal is electrically connected with the SP4 terminal. The Buck mode of the schematic structure diagram of the general power conversion module shown in fig. 2 is defined as a K mode, and the Boost mode is defined as a T mode. The principle structure diagram (charging) of the universal power conversion module can be switched between a K mode and a T mode according to the relation between the withstand voltage value of the capacitor array and the system power supply voltage; the principle structure diagram (discharge) of the universal power conversion module can be switched between K and T modes according to the relation between the rated voltage of the capacitor array and the load driving voltage. Therefore, the energy conversion process of the whole system can be divided into four combined modes, namely KK, KT, TK and TT modes. The system power supply voltage is greater than the withstand voltage of the capacitor array in the input-side charging power conversion module shown in fig. 3, and the rated voltage of the capacitor array is greater than the load driving voltage in the output-side discharging power conversion module shown in fig. 4, so the combination mode adopted in this embodiment is the KK mode.

The four modes in the above embodiment will be described in detail below.

1. When the withstand voltage of the capacitor array is smaller than the system power supply voltage and the load driving voltage is smaller than the rated voltage of the capacitor array, the system is in a KK mode, when the K mode is charged, the switch S1 is in a SP1 gear, the switch S3 is in a SP5 gear, the positive electrode of the system power supply is electrically connected with the VH end of the principle structure diagram (charging) of the general power conversion module, the input end of the capacitor array is electrically connected with the V L end of the principle structure diagram (charging) of the general power conversion module, when the K mode is discharged, the S2 is in a SP3 gear, the S4 is in a SP8 gear, the output end of the capacitor array is electrically connected with the VH end of the principle structure diagram (discharging) of the general power conversion module, and the input end of the pulse driving load is electrically connected with the V L end of the.

2. When the withstand voltage of the capacitor array is smaller than the system power supply voltage and the load driving voltage is larger than the rated voltage of the capacitor array, the system is in a KT mode, when the K mode is charged, S1 is in an SP1 gear, S3 is in an SP5 gear, the positive electrode of a system power supply is electrically connected with a VH end of a principle structure diagram (charging) of the general power conversion module, the input end of the capacitor array is electrically connected with a V L end of the principle structure diagram (charging) of the general power conversion module, when the T mode is discharged, S2 is in an SP3 gear, S4 is in an SP7 gear, the output end of the capacitor array is electrically connected with a V L end of the principle structure diagram (discharging) of the general power conversion module, and the input end of the pulse driving load is electrically connected with a VH end of the principle structure diagram.

3. When the withstand voltage of the capacitor array is greater than the system power supply voltage, and the load driving voltage is less than the rated voltage of the capacitor array, the system is in a TK mode, when the T mode is charged, S1 is in an SP2 gear, S3 is in an SP5 gear, the positive electrode of a system power supply is electrically connected with the V L end of the principle structure diagram (charging) of the general power conversion module, the input end of the capacitor array is electrically connected with the VH end of the principle structure diagram (charging) of the general power conversion module, when the K mode is discharged, S2 is in an SP3 gear, S4 is in an SP8 gear, the output end of the capacitor array is electrically connected with the VH end of the principle structure diagram (discharging) of the general power conversion module, and the input end of the pulse driving load is electrically connected with the V L end of the principle (.

4. When the withstand voltage of the capacitor array is greater than the system power supply voltage, and the load driving voltage is greater than the rated voltage of the capacitor array, the system is in a TT mode, when the T mode is charged, S1 is in an SP2 gear, S3 is in an SP5 gear, the positive electrode of a system power supply is electrically connected with a V L end of a principle structure diagram (charging) of the general power conversion module, the input end of the capacitor array is electrically connected with a VH end of the principle structure diagram (charging) of the general power conversion module, when the T mode is discharged, S2 is in an SP3 gear, S4 is in an SP7 gear, the output end of the capacitor array is electrically connected with a V L end of the principle structure diagram (discharging) of the general power conversion module, and the input end of the pulse driving load is electrically connected with a VH end of the principle structure diagram.

It should be further noted that the charging of the capacitor array by the system power supply is controlled by PWM-C (CMD-PWM), the charging of the capacitor array is stopped when the charging voltage reaches a preset value, and the MCU main control module may select a constant voltage mode or a constant current mode to charge the capacitor array according to the current hardware configuration. The pulse voltage or the pulse current loaded on the load can be changed by adjusting PWM-D (DRM-PWM), and the MCU main control module can realize pulse voltage driving or pulse constant current mode driving aiming at the load according to the monitoring data of the voltage and current sensors.

Since the energy output by the system can be designed to be large, the system must be safe and reliable. When the MCU master control module has the phenomena of software abnormity and the like and can not implement the control function, the system automatically utilizes the PWM modulation signal output by the hardware PWM module to ensure the safe work of the system to the greatest extent. The hardware PWM module is composed of pure analog hardware, can detect voltage and current parameters of the input end charging power conversion module, the capacitor array and the output end discharging power conversion module, works according to safety parameters designed and established by different specifications, and synthesizes PWM pulse signals necessary for the working of the charging and discharging power conversion modules.

In another embodiment, fig. 12 is a hardware PWM module provided by the present disclosure. As shown in fig. 12, the input terminal of the schmitt-not gate U1 is connected in series with the capacitor C1 and then grounded, the resistor R1 is connected in parallel between the input terminal and the output terminal of the schmitt-not gate U1, and the schmitt-not gate U1, the resistor R1, and the capacitor C1 form a square-wave oscillator for synthesizing a square wave with D equal to 50% (duty ratio of 50%). The output end of the Schmidt NOT gate U1 is electrically connected with the input end of the Schmidt NOT gate U2, and after the original square wave is inverted by the Schmidt NOT gate U2, the inverted square wave is compared with the output of the U1 to form two paths of PWM signals with the same frequency and 180-degree phase difference. The output end of the Schmitt NOT gate U2 is serially connected with a capacitor C2 and a resistor R2 and then grounded, a freewheeling diode D1 is parallelly connected to two ends of the resistor R2, and the capacitor C2 and the resistor R2 form a first path of differential circuit which is used for extracting the rising edge pulse of the first path of PWM to form narrow pulse. The freewheeling diode D1 plays a role in clamping the level when the PWM signal becomes low, preventing the post-stage circuit from being damaged; the output end of the Schmitt NOT gate U1 is serially connected with a capacitor C3 and a resistor R3 and then grounded, a freewheeling diode D2 is parallelly connected with two ends of the resistor R3, and the capacitor C3 and the resistor R3 form a second path of differential circuit for extracting the rising edge pulse of the second path of PWM to form a narrow pulse. The freewheeling diode D2 plays a role in clamping the level when the PWM signal becomes low level, so that the post-stage circuit is prevented from being damaged, and the phase difference of two narrow pulses formed is 180 degrees. The signal line led out from the middle of the capacitor C2 and the resistor R2 is electrically connected with the input end of the Schmidt NOT gate U3, and the output end of the Schmidt NOT gate U3 is electrically connected with the base stage of the triode QW1 after being connected with the resistor R4 in series. A capacitor C4 is connected between the collector and the emitter of the transistor QW1 in series, the emitter of the transistor QW1 is divided into two branches, one branch is electrically connected with the collector of the transistor QW3, the other branch is electrically connected with the inverting input end of the operational amplifier OP6, a resistor R6 and a resistor R7 are connected between a power supply and the ground in series, outgoing lines between the resistor R6 and the resistor R7 are electrically connected with the base level of the transistor QW3, and the emitter of the transistor QW3 is electrically connected with the power supply. The signal line led out from the middle of the capacitor C3 and the resistor R3 is electrically connected with the input end of the Schmidt NOT gate U4, and the output end of the Schmidt NOT gate U4 is electrically connected with the base stage of the triode QW2 after being connected with the resistor R5 in series. A capacitor C5 is connected between the collector and the emitter of the transistor QW2 in series, the emitter of the transistor QW2 is divided into two branches, one branch is electrically connected with the collector of the transistor QW4, the other branch is electrically connected with the inverting input end of the operational amplifier OP7, a resistor R8 and a resistor R9 are connected between a power supply and the ground in series, outgoing lines between the resistor R8 and the resistor R9 are electrically connected with the base level of the transistor QW4, and the emitter of the transistor QW4 is electrically connected with the power supply. After a trigger pulse arrives, the transistor QW1 and the transistor QW2 are conducted to complete discharging of the capacitor C4 and the capacitor C5, the trigger pulse is short, then the transistor QW1 and the transistor QW2 are cut off, and the capacitor C4 and the capacitor C5 are charged through a constant current source formed by the transistor QW3 and the transistor QW 4; the steps are repeated in this way, so that two paths of same-frequency sawtooth waves with the phase difference of 180 degrees are obtained.

It should be noted that, as shown in fig. 5, the hardware PWM module and the PWM module share the signal modulation circuit, and both the hardware PWM module and the PWM module can implement that the sawtooth wave enters the comparison unit and is compared with the output signal of the signal modulation circuit, so as to form two paths of PWM modulation signals with the same frequency and the wrong phase. The duty ratio of the PWM modulation signals with the same frequency and the same phase output by the hardware PWM module changes along with the amplitude of the error signal, the change trend of the duty ratio is opposite to that of the input signal, so that a negative feedback structure is formed, and finally after the circuit is stabilized, the reference signal is equal to the feedback signal.

In the above embodiment, when the MCU main control module is normal, the switch selection circuit S5 connects the MCU-PWM-C and MCU-PWM-D channels with the PWM-C (CMD-PWM) and PWM-D (DRM-PWM) and outputs the PWM signal to the MOSFET driving circuit, and the MCU main control module outputs the PWM signal. When the MCU master control module is abnormal, in order to ensure that the system safely runs, the PWM signals synthesized by hardware can be switched, a circuit formed by pure hardware can ensure that the circuit is not associated with a processor and can independently run under most conditions, two paths of phase-staggered PWM signals are respectively connected with PWM-C (CMD-PWM) and PWM-D (DRM-PWM) after passing through a switch selection circuit S5, and due to phase-staggering, the capacitor array cannot be discharged while being charged, so that the safe input of a system power supply is protected, the MOSFET (metal oxide semiconductor field effect transistor) is prevented from being simultaneously switched on, the direct communication between the system power supply and a load is avoided, and the safety and the reliability of the system are improved.

In another embodiment, since the parameters (amplitude, frequency) of the sawtooth wave generated by the hardware PWM module cannot be changed, the later debugging and upgrading are difficult unless circuit components are replaced. Therefore, as shown in fig. 13, the present disclosure provides a DCO application circuit, which can change the frequency of the square wave output by the D flip-flop by changing the duty ratio of the input PWM signal, thereby indirectly changing the frequency and amplitude of the sawtooth wave, and the sawtooth wave passes through the comparison unit and then is synthesized into the PWM signal with the same frequency and the same phase. When the frequency of the sawtooth wave changes slightly, the amplitude changes slightly (within the allowable range of the error amplifying circuit), and the hardware PWM module can still work normally, but when the amplitude changes greatly, the system cannot work normally. After the DCO is adopted, the frequency and the amplitude of the sawtooth waves become adjustable, and the anti-interference capacity of the system is improved.

In this embodiment, the input signal is a PWM signal, the resistor R1 and the capacitor C1 are connected in series between the input terminal and the power supply VDD, and the resistor R1 and the capacitor C1 are used to filter harmonic components of PWM. A signal wire led out from the middle of the resistor R1 and the capacitor C1 is connected with the resistor R3 in series and then is electrically connected with the base electrode of the triode QW1, and a resistor R2 is connected between the base electrode and the emitting electrode of the triode QW1 in parallel. The PWM input signal can enable the emitter current of the triode QW1 to change along with the change of the duty ratio of the input PWM through a resistance-capacitance network formed by resistors R1, R2, R3 and a capacitor C1 (the larger the duty ratio of the PWM is, the smaller the emitter current of the triode QW1 is, and the smaller the duty ratio of the PWM is, the larger the emitter current of the triode QW1 is). The collector of the transistor QW1 is connected in series with the capacitor C2 and then grounded, and the transistor QW1 charges the capacitor C2 with constant current. The collector of the transistor QW1 is electrically connected with the inverting input end of the operational amplifier OP8, and the collector of the transistor QW1 and the output end of the operational amplifier OP8 are connected in series with a diode D1 to provide a discharge loop for the capacitor C2. The resistor R4 and the resistor R5 are connected between the power supply VDD and the ground in series, the non-inverting input end of the operational amplifier OP8 is electrically connected with the middle ends of the resistor R4 and the resistor R5, and different sawtooth peak voltages can be set by configuring the resistance values of the resistor R4 and the resistor R5. The output end of the operational amplifier OP8 is connected in series with a resistor R6 between a power supply VDD and is electrically connected with the CP end of the D trigger, the D end of the D trigger is electrically connected with the Q non-end, and the Q end and the Q non-end output square waves with 180-degree phase dislocation. The Q end of the D trigger is connected with a resistor R7 in series and then is electrically connected with the base stage of the transistor QW 2. A capacitor C3 is connected in parallel between the collector and the emitter of the transistor QW2, the emitter of the transistor QW2 is divided into two branches, one branch is electrically connected with the collector of the transistor QW4, the other branch is electrically connected with the inverting input end of the operational amplifier OP9, a resistor R9 and a resistor R10 are connected in series between a power supply and the ground, an outgoing line between the resistor R9 and the resistor R10 is electrically connected with the base level of the transistor QW4, and the emitter of the transistor QW4 is electrically connected with a power supply VDD. The Q non-end of the D trigger is connected with a resistor R8 in series and then is electrically connected with the base stage of a triode QW 3. A capacitor C4 is connected in parallel between the collector and the emitter of the transistor QW3, the emitter of the transistor QW3 is divided into two branches, one branch is electrically connected with the collector of the transistor QW5, the other branch is electrically connected with the inverting input end of the operational amplifier OP10, a resistor R11 and a resistor R12 are connected in series between a power supply and the ground, an outgoing line between the resistor R11 and the resistor R12 is electrically connected with the base level of the transistor QW5, and the emitter of the transistor QW5 is electrically connected with the power supply. The transistor QW2 and the transistor QW3 are conducted after the square wave effective level comes, the capacitor C3 and the capacitor C4 are discharged, then the transistor QW1 and the transistor QW2 are cut off, and the capacitor C4 and the capacitor C5 are charged through a constant current source formed by the transistor QW3 and the transistor QW 4; the steps are repeated in this way, so that two paths of same-frequency sawtooth waves with the phase difference of 180 degrees are obtained.

In the above embodiment, when the MCU main control module is normal, the switch selection circuit S6 connects the MCU-PWM-C and MCU-PWM-D channels with the PWM-C (CMD-PWM) and PWM-D (DRM-PWM) and outputs the PWM signal to the MOSFET driving circuit, and the MCU main control module outputs the PWM signal. When the MCU master control module is abnormal, in order to ensure that the system safely runs, the digital control oscillator DCO application circuit can be switched to, two paths of PWM signals with the same frequency and the wrong phase synthesized by the circuit are respectively connected with PWM-C (CMD-PWM) and PWM-D (DRM-PWM) after passing through the switch selection circuit S6, and due to the phase wrong phase, the capacitor array cannot be discharged while being charged, so that the safe input of a system power supply is protected, the direct communication between the system power supply and a load due to the fact that the MOSFETs are simultaneously conducted is avoided, and the safety and the reliability of the system are improved.

In another embodiment, since the parameters (amplitude and frequency) of the sawtooth wave generated by the DCO are changed, when the amplitude of the sawtooth wave is changed greatly, a correct PWM signal cannot be generated. Ideally, the frequency of the sawtooth wave can be changed while the amplitude is unchanged. Therefore, as shown in fig. 14, a DCO-based PWM synthesis module inputs PWM signals, and can synthesize the same-frequency sawtooth wave of the reference modulation, which is staggered by 180 °, and the sawtooth wave passes through the comparison unit and then outputs the same-frequency staggered PWM signal. When the duty ratio of the PWM is changed, the frequency of the same-frequency sawtooth waves staggered by 180 degrees is changed, but the amplitude is not changed. Therefore, the spread spectrum function can be realized, and the anti-interference capability of the system is improved. Meanwhile, hardware is used for replacing software, so that the load of the MCU main control module can be reduced.

In this embodiment, the input signal is a PWM signal input, the resistor R1 and the capacitor C1 are connected in series between the input terminal and the power supply VDD, and the resistor R1 and the capacitor C1 are used to filter harmonic components of PWM. A signal line led out from the middle of the resistor R1 and the capacitor C1 is divided into two branches, one branch is connected with the resistor R3 in series and then is electrically connected with the base electrode of the triode QW1, and the other branch is connected with the resistor R8 in series and then is electrically connected with the base electrode of the triode QW 2. And a resistor R2 is connected between the base electrode and the emitter electrode of the transistor QW1 in parallel. The PWM input signal can enable the emitter current of the triode QW1 to change along with the change of the duty ratio of the input PWM through a resistance-capacitance network formed by resistors R1, R2, R3 and a capacitor C1 (the larger the duty ratio of the PWM is, the smaller the emitter current of the triode QW1 is, and the smaller the duty ratio of the PWM is, the larger the emitter current of the triode QW1 is). The collector of the transistor QW1 is connected in series with the capacitor C2 and then grounded, and the transistor QW1 charges the capacitor C2 with constant current. The collector of the transistor QW1 is electrically connected with the inverting input ends of the operational amplifier OP11 and the operational amplifier OP13, and the collector of the transistor QW1 and the output end of the operational amplifier OP11 are connected in series with a diode D1 to provide a discharge loop for the capacitor C2. The resistor R4 and the resistor R5 are connected between the power supply VDD and the ground in series, the non-inverting input end of the operational amplifier OP11 is electrically connected with the middle ends of the resistor R4 and the resistor R5, and different sawtooth peak voltages can be set by configuring the resistance values of the resistor R4 and the resistor R5. A resistor R6 is connected between the output end of the operational amplifier and the power supply VDD in series. And a resistor R7 is connected between the base electrode and the emitter electrode of the transistor QW2 in parallel. The PWM input signal can enable the emitter current of the triode QW2 to change along with the change of the duty ratio of the input PWM through a resistance-capacitance network formed by a resistor R1, a resistor R7, a resistor R8 and a capacitor C1 (the larger the duty ratio of the PWM is, the smaller the emitter current of the triode QW2 is, and the smaller the duty ratio of the PWM is, the larger the emitter current of the triode QW2 is). The collector of the triode QW2 is divided into three branches, the first branch is connected with the capacitor C3 in series and then grounded, the triode QW2 supplies constant current to charge the capacitor C3, the emitter currents of the triode QW1 and the triode QW2 are the same by adjusting the resistance values of the resistor R7 and the resistor R8, the second branch is electrically connected with the inverting input end of the operational amplifier OP14, the third branch and the collector of the triode QW3 are connected with the diode D2 in series, and a discharging loop is provided for the capacitor C3. The non-inverting input terminal of the OP-amp OP12 is electrically connected to the collector of the transistor QW 1. The resistor R9 and the resistor R10 are connected between the power supply VDD and the ground in series, the inverting input end of the operational amplifier OP12 is electrically connected with the middle end of the resistor R9 and the resistor R10, and the resistance values of the resistor R9 and the resistor R10 are configured to enable the set sawtooth wave peak voltage to be equal to half of the sawtooth wave peak voltage at the two ends of the capacitor C2. A resistor R11 is connected in series between the output end of the OP12 and the power supply VDD. The output end of the operational amplifier OP12 is serially connected with a capacitor C4 and a resistor R12 and then grounded, a freewheeling diode D3 is parallelly connected to both ends of the resistor R12, the capacitor C4 and the resistor R12 form a differential circuit, and the freewheeling diode D3 has a clamping effect of level. A signal wire led out from the middle of the capacitor C4 and the resistor R12 is electrically connected with the base electrode of the transistor QW3, and the emitter electrode of the transistor QW3 is grounded. The output signals on the capacitor C2 and the capacitor C3 are the same-frequency sawtooth waves which are staggered by 180 degrees.

In the above embodiment, when the MCU main control module is normal, the switch selection circuit S7 connects the MCU-PWM-C and MCU-PWM-D channels with the PWM-C (CMD-PWM) and PWM-D (DRM-PWM) and outputs the PWM signal to the MOSFET driving circuit, and the MCU main control module outputs the PWM signal. When the MCU master control module is abnormal, in order to ensure that the system safely runs, the MCU master control module can be switched to a DCO-based PWM synthesis module, two paths of PWM signals with the same frequency and the wrong phase synthesized by the module are respectively connected with PWM-C (CMD-PWM) and PWM-D (DRM-PWM) after passing through a switch selection circuit S7, and due to the phase wrong phase, the capacitor array cannot be discharged while being charged, so that the safe input of a system power supply is protected, the MOSFET is prevented from being conducted at the same time, the direct communication between the system power supply and a load is caused, and the safety and the reliability of the system are improved.

The foregoing description shows and describes several preferred embodiments of the present application, but as aforementioned, it is to be understood that the application is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the application as described herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the application, which is to be protected by the claims appended hereto.