阅读说明：本技术 半导体激光装置 (Semiconductor laser device ) 是由 内海秀之 河上翔 田中良宜 于 2019-11-29 设计创作，主要内容包括：本发明提供一种半导体激光装置,其包括：半导体层,该半导体层包括：具有第一宽度的发光区域；和形成于上述发光区域外的区域的、具有大于上述第一宽度的第二宽度的焊垫区域；覆盖上述发光区域和上述焊垫区域的绝缘层；配线电极,其具有：贯通上述绝缘层与上述发光区域电连接的内部连接区域；和隔着上述绝缘层覆盖上述焊垫区域、且与导线进行外部连接的外部连接区域。(The present invention provides a semiconductor laser device, comprising: a semiconductor layer, the semiconductor layer comprising: a light emitting area having a first width; and a pad region formed in a region outside the light emitting region and having a second width greater than the first width; an insulating layer covering the light emitting region and the pad region; a wiring electrode having: an internal connection region penetrating the insulating layer and electrically connected to the light emitting region; and an external connection region which covers the pad region with the insulating layer interposed therebetween and is externally connected to a lead.)

1. A semiconductor laser device, comprising:

a semiconductor layer, comprising: a light emitting area having a first width; and a pad region having a second width greater than the first width, formed in a region outside the light emitting region;

an insulating layer covering the light emitting region and the pad region;

a wiring electrode having: an internal connection region penetrating the insulating layer and electrically connected to the light-emitting region; and an external connection region which covers the pad region with the insulating layer interposed therebetween and is externally connected to a lead.

2. A semiconductor laser device as claimed in claim 1, wherein:

the external connection region is externally connected to a wire having a connection width greater than the first width.

3. A semiconductor laser device according to claim 1 or 2, wherein:

the light emitting region extends in a stripe shape along a first direction and has the first width with respect to a second direction orthogonal to the first direction,

the pad region is opposed to the light-emitting region in the second direction, and is formed in a region outside the light-emitting region so as to extend in a band-like shape along the first direction, the second width being defined with respect to the second direction.

4. A semiconductor laser device according to any one of claims 1 to 3, wherein:

the light emitting region has a top portion, a base portion, and a sidewall connecting the top portion and the base portion, and includes a mesa configuration divided into a plateau shape,

the pad region is formed electrically isolated from the mesa formation,

the internal connection region of the wiring electrode is electrically connected to the top of the mesa structure.

5. The semiconductor laser device according to claim 4, wherein:

the sidewalls of the mesa formation slope obliquely downward from the top to the base.

6. A semiconductor laser device according to claim 4 or 5, characterized in that:

the mesa configuration includes a light emitting cell layer including a first semiconductor layer of a first conductivity type formed at the base side, a second semiconductor layer of a second conductivity type formed at the top side, and an active layer interposed between the first semiconductor layer and the second semiconductor layer,

the internal connection region of the wiring electrode is electrically connected to the second semiconductor layer.

7. The semiconductor laser device according to claim 6, wherein:

the mesa configuration includes: a plurality of the light emitting cell layers stacked from the base side to the top side; and a tunnel junction layer interposed between the plurality of light emitting cell layers.

8. A semiconductor laser device according to any one of claims 4 to 7, wherein:

the pad region has a pad top, a pad base, and a pad sidewall connecting the pad top and the pad base, and includes a pad mesa structure divided into a plateau shape,

the external connection region of the wiring electrode covers the pad top of the pad mesa structure.

9. A semiconductor laser device according to claim 8, wherein:

the pad sidewall of the pad mesa structure slopes downward from the pad top to the pad base.

10. A semiconductor laser device according to any one of claims 4 to 7, wherein:

the pad area is formed on the base side relative to the top of the mesa configuration.

11. The semiconductor laser device according to any one of claims 1 to 10, wherein:

further comprising a substrate having a first main surface on one side and a second main surface on the other side,

the semiconductor layer is formed on the first main surface of the substrate.

12. A semiconductor laser device according to claim 11, wherein:

the light emitting region is formed offset from the center of the substrate in a plan view.

13. A semiconductor laser device according to claim 11 or 12, wherein:

further comprising an electrode formed on the second main surface of the substrate and electrically connected to the semiconductor layer via the substrate.

14. A semiconductor core rod, comprising:

a metal mandrel base having a first surface on one side and a second surface on the other side;

a first terminal attached to the second face of the mandrel base;

a second terminal which penetrates the mandrel base from the second surface of the mandrel base and is led out to the first surface;

the semiconductor laser device according to any one of claims 1 to 13, which is disposed on the first surface of the plug base and is electrically connected to the first terminal via the plug base; and

a lead wire connected to the second terminal and the external connection region of the wiring electrode of the semiconductor laser device.

15. A semiconductor package, comprising:

a package main body containing a transparent resin or a translucent resin;

a terminal electrode sealed in the package body;

a semiconductor laser device according to any one of claims 1 to 13 sealed in the package body with a space from the terminal electrode;

and a lead wire sealed in the package body and connected to the terminal electrode and the external connection region of the wiring electrode of the semiconductor laser device.

16. The semiconductor package of claim 15, wherein:

the semiconductor laser device is disposed offset from the center of the package body in a plan view.

17. A semiconductor package, comprising:

a basket having an inner space;

a first wiring line routed inside and outside the housing;

a second wiring electrically insulated from the first wiring and arranged inside and outside the housing;

a semiconductor laser device according to any one of claims 1 to 13, disposed on the second wiring in the internal space and electrically connected to the second wiring;

and a lead wire connected to the first wiring and the external connection region of the wiring electrode of the semiconductor laser device.

18. The semiconductor package of claim 17, wherein:

the semiconductor laser device is disposed offset from the center of the housing in a plan view.

Technical Field

The present invention relates to a semiconductor laser device.

Background

Patent document 1 discloses a semiconductor laser device including a semiconductor layer, an insulating layer formed on the semiconductor layer, and an electrode formed on the insulating layer. The semiconductor layer has a light-emitting region for generating laser light and a non-light-emitting region outside the light-emitting region. The insulating layer covers the light-emitting region and the non-light-emitting region. The electrode covers the light-emitting region and the non-light-emitting region with an insulating layer interposed therebetween, and is electrically connected to the light-emitting region through the insulating layer. In a portion of the electrode covering the light emitting region, a bonding wire (wire) is externally connected.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open No. 2012 and 227313

Disclosure of Invention

Technical problem to be solved by the invention

By reducing the light emitting region, the directivity of the laser light can be improved. However, in this case, it is difficult to secure a connection region of the wire in the light-emitting region. Further, a failure may occur in the light emitting region due to an external force or stress at the time of connection of the lead.

One embodiment of the present invention provides a semiconductor laser device which is not limited by design due to a wire and can appropriately realize reduction of a light emitting region.

Means for solving the problems

One embodiment of the present invention provides a semiconductor laser device including: a semiconductor layer, the semiconductor layer comprising: a light emitting area having a first width; and a pad region formed in a region outside the light emitting region and having a second width greater than the first width; an insulating layer covering the light emitting region and the pad region; a wiring electrode having: an internal connection region penetrating the insulating layer and electrically connected to the light emitting region; and an external connection region which covers the pad region with the insulating layer interposed therebetween and is externally connected to a lead.

According to the semiconductor laser device, the light emitting region can be reduced appropriately without being limited by the design due to the wire.

The above and other objects, features and effects of the present invention will become more apparent from the following description of the embodiments with reference to the accompanying drawings.

Drawings

Fig. 1 is a perspective view showing a semiconductor laser device according to a first embodiment of the present invention together with a lead wire connected to the semiconductor laser device.

Fig. 2 is a plan view of the semiconductor laser device shown in fig. 1.

Fig. 3 is a sectional view taken along the line III-III shown in fig. 2.

Fig. 4 is an enlarged sectional view of the light-emitting region shown in fig. 3.

Fig. 5 is an enlarged cross-sectional view of the pad area shown in fig. 3.

Fig. 6 is an enlarged cross-sectional view of the outer region shown in fig. 3.

Fig. 7 is a diagram for explaining one configuration example of the light emitting cell layer.

Fig. 8 is a diagram for explaining one configuration example of the tunnel junction layer.

Fig. 9 is a perspective view showing a semiconductor laser device according to a second embodiment of the present invention together with a lead wire connected to the semiconductor laser device.

Fig. 10 is a plan view of the semiconductor laser device shown in fig. 9.

Fig. 11 is a sectional view taken along line XI-XI shown in fig. 10.

Fig. 12 is a perspective view showing a semiconductor laser device according to a third embodiment of the present invention together with a lead wire connected to the semiconductor laser device.

Fig. 13 is an isolated perspective view showing the package of the first embodiment.

Fig. 14 is a plan view showing a package of the second embodiment.

Fig. 15 is a sectional view taken along the line XV-XV shown in fig. 14.

Fig. 16 is a plan view showing a package of the third embodiment.

Fig. 17 is a bottom view of the package shown in fig. 16.

Fig. 18 is a sectional view taken along line XVIII-XVIII shown in fig. 17.

Detailed Description

Fig. 1 is a perspective view showing a semiconductor laser device 1 according to a first embodiment of the present invention together with a lead wire 34 connected to the semiconductor laser device 1. Fig. 2 is a plan view of the semiconductor laser device 1 shown in fig. 1. Fig. 3 is a sectional view taken along the line III-III shown in fig. 2.

Fig. 4 is an enlarged sectional view of light-emitting region 31 shown in fig. 3. Fig. 5 is an enlarged cross-sectional view of the bond pad area 32 shown in fig. 3. Fig. 6 is an enlarged sectional view of the outer region 33 shown in fig. 3. Fig. 7 is a diagram for explaining one configuration example of the light emitting cell layer 13. Fig. 8 is a diagram for explaining one configuration example of the tunnel junction layer 14.

Referring to fig. 1 to 3, a semiconductor laser device 1 includes a substrate 2 formed in a rectangular parallelepiped shape. In this embodiment, the substrate 2 is made of a GaAs (gallium arsenide) substrate to which an n-type impurity is added. The n-type impurity may include at least 1 of Si (silicon), Te (tellurium), and Se (selenium).

The substrate 2 includes: a first substrate main surface 3 on one side; the second substrate main surface 4 on the other side; and substrate side surfaces 5A, 5B, 5C, 5D connecting the first substrate main surface 3 and the second substrate main surface 4. The first substrate main surface 3 and the second substrate main surface 4 are formed in a quadrilateral shape (rectangular shape in this embodiment) in a plan view seen from the normal direction Z thereof (hereinafter simply referred to as "in plan view").

The substrate sides 5A-5D comprise a first substrate side 5A, a second substrate side 5B, a third substrate side 5C and a fourth substrate side 5D. The first substrate side 5A and the second substrate side 5B form the long sides of the substrate 2. The first substrate side 5A and the second substrate side 5B extend along the first direction X, opposing each other in a second direction Y intersecting the first direction X. The second direction Y, more specifically, is orthogonal to the first direction X.

The third substrate side 5C and the fourth substrate side 5D form the short sides of the substrate 2. The third substrate side 5C and the fourth substrate side 5D extend along the second direction Y, opposite to each other in the first direction X. At least the substrate side surface 5C and the substrate side surface 5D among the substrate side surfaces 5A to 5D are preferably mirror-mirrored. All of the substrate side surfaces 5A to 5D may be mirrored. The substrate sides 5A-5D may also be cleavage planes.

The thickness of the substrate 2 is 50 μm or more and 350 μm or less. The thickness may be 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, or 300 μm or more and 350 μm or less.

The length L1 of the first substrate side surface 5A (second substrate side surface 5B) may be 200 μm or more and 1000 μm or less. The length L1 may be 200 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less. The length L1 is 500 μm or more and 700 μm or less in this embodiment.

The length L2 of the third substrate side 5C (fourth substrate side 5D) may be 50 μm or more and 600 μm or less. The length L2 may be 50 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, or 500 μm or more and 600 μm or less. The length L2 is 300 μm or more and 500 μm or less in this embodiment.

The semiconductor laser device 1 further comprises a semiconductor layer 6 formed on the first substrate main surface 3. The semiconductor layer 6 is formed on the first substrate main surface 3 by epitaxial growth. The semiconductor layer 6 generates laser light. The semiconductor layer 6 generates laser light having a peak emission wavelength in a range of 800nm or more and 1000nm or less. That is, the semiconductor layer 6 generates laser light in the infrared region.

The semiconductor layer 6 includes a semiconductor main surface 7 and semiconductor side surfaces 8A, 8B, 8C, 8D. The semiconductor main surface 7 is formed in a square shape (rectangular shape in this embodiment) in a plan view. The semiconductor side surfaces 8A to 8D include a first semiconductor side surface 8A, a second semiconductor side surface 8B, a third semiconductor side surface 8C, and a fourth semiconductor side surface 8D. Semiconductor sides 8A-8D are connected to substrate sides 5A-5D. More specifically, the semiconductor side surfaces 8A to 8D are formed on the same plane as the substrate side surfaces 5A to 5D.

Referring to fig. 3 to 6, semiconductor layer 6 has a stacked structure including n-type buffer layer 10, light-emitting layer 11, and p-type contact layer 12. The n-type buffer layer 10 supplies electrons to the light emitting layer 11. The p-type contact layer 12 supplies holes to the light-emitting layer 11. The light emitting layer 11 generates laser light by combination of holes and electrons.

The n-type buffer layer 10 is laminated on the first substrate main surface 3. The n-type buffer layer 10 contains GaAs (gallium arsenide) to which an n-type impurity is added. The n-type impurity may include at least 1 of Si (silicon), Te (tellurium), and Se (selenium). The n-type impurity concentration of the n-type buffer layer 10 may be 1 × 10¹⁸cm^-3Above and 1 × 10¹⁹cm^-3The following.

The light emitting layer 11 is stacked on the n-type buffer layer 10. The light-emitting layer 11 includes a plurality of (3 in this embodiment) light-emitting unit layers 13 and a plurality of (2 in this embodiment) tunnel junction layers 14 in this embodiment. The light emitting unit layer 13 generates light by combination of holes and electrons. The tunnel junction layer 14 generates a tunnel current due to a tunnel effect, and supplies the tunnel current to the plurality of light emitting cell layers 13.

The plurality of light emitting unit layers 13 include a first light emitting unit layer 13A, a second light emitting unit layer 13B, and a third light emitting unit layer 13C, which are sequentially stacked from the n-type buffer layer 10 side.

Referring to fig. 7, each of the first, second, and third light emitting cell layers 13A, 13B, and 13C has a laminated structure including an n-type composite layer (clad layer, stacked layer) 15 (first semiconductor layer), a first guide layer 16, an active layer 17, a second guide layer 18, and a p-type composite layer 19 (second semiconductor layer) which are sequentially laminated from the substrate 2 side.

The n-type composite layer 15 includes AlGaAs (aluminum-gallium arsenide) added with n-type impurities. n typeThe impurities may include at least 1 of Si (silicon), Te (tellurium), and Se (selenium). The n-type impurity concentration of the n-type composite layer 15 may be 1 × 10¹⁷cm^-3Above and 1 × 10¹⁹cm^-3The following. The n-type composite layer 15 in this embodiment includes a first n-type composite layer 20 and a second n-type composite layer 21 stacked in this order from the substrate 2 side.

The first n-type composite layer 20 includes Al having a first Al composition A_AGa_(1-A)As. The first Al composition a may be 0.4 or more and 0.6 or less. The first Al composition a may be 0.4 or more and 0.45 or less, 0.45 or more and 0.5 or less, 0.5 or more and 0.55 or less, or 0.55 or more and 0.6 or less. The n-type impurity concentration of the first n-type composite layer 20 may be 5 × 10¹⁷cm^-3Above and 1 × 10¹⁹cm^-3The following.

The thickness of the first n-type composite layer 20 may beAbove andthe following. The thickness of the first n-type composite layer 20 may be setAbove andthe following components,Above andthe following components,Above andthe following components,Above andthe following areAbove andthe following.

The second n-type composite layer 21 includes Al having a second Al composition B_BGa_(1-B)As, the second Al composition B is different from the first Al composition a of the first n-type composite layer 20. The second Al composition B is more specifically smaller than the first Al composition A (B)<A) In that respect The second Al composition B may be 0.2 or more and 0.4 or less. The second Al composition B may be 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, or 0.35 or more and 0.4 or less.

The second n-type composite layer 21 has an n-type impurity concentration different from that of the first n-type composite layer 20. The n-type impurity concentration of the second n-type composite layer 21 is more specifically smaller than the n-type impurity concentration of the first n-type composite layer 20. The n-type impurity concentration of the second n-type composite layer 21 may be 1 × 10¹⁷cm^-3Above and 5 × 10¹⁸cm^-3The following.

The second n-type composite layer 21 may also have a thickness different from that of the first n-type composite layer 20. The second n-type composite layer 21 may also have a thickness greater than that of the first n-type composite layer 20.

The thickness of the second n-type composite layer 21 may beAbove andthe following. The thickness of the second n-type composite layer 21 may be setAbove andthe following components,Above andthe following components,Above andthe following components,Above andthe following components,Above andthe following areAbove andthe following.

The first guide layer 16 contains Al having a third Al composition C_CGa_(1-C)As, the third Al composition C is different from the Al composition (the first Al composition a and the second Al composition B) of the n-type composite layer 15. The third Al composition C is more specifically an Al composition (C) smaller than the n-type composite layer 15<B<A)。

The third Al composition C may be more than 0 and 0.2 or less. The third Al composition C may be greater than 0 and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, or 0.15 or more and 0.2 or less. The first guide layer 16 may be free from impurities.

The thickness of the first guide layer 16 is smaller than the thickness of the first n-type composite layer 20. The first guide layer 16 may have a thickness ofAbove andthe following. The thickness of the first guide layer 16 may be set to beAbove andthe following components,Above andthe following components,Above andthe following, orAbove andthe following.

The active layer 17 has a multiple quantum well structure including a well layer 22 and a barrier layer 23. The active layer 17 has a 3-layer structure in this embodiment, and includes a well layer 22, a barrier layer 23, and a well layer 22, which are stacked in this order from the substrate 2 side.

The active layer 17 may have a multiple quantum well structure including well layers 22 and barrier layers 23 alternately stacked over a plurality of periods (2 periods or more). In this case, the lowermost layer of the active layer 17 with respect to the substrate 2 side may be the well layer 22 or the barrier layer 23. The uppermost layer of the active layer 17 may be the well layer 22 or the barrier layer 23.

The well layer 22 contains In having an In composition α_αGa_(1-α)As. The In composition α may be more than 0 and 0.2 or less. The In composition α may be greater than 0 and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, or 0.15 or more and 0.2 or less. The well layer 22 may be free from impurity addition.

The thickness of the well layer 22 may be smaller than that of the first guide layer 16. The thickness of the well layer 22 may beAbove andthe following. The thickness of the well layer 22 may be setAbove andthe following components,Above andthe following, orAbove andthe following.

The barrier layer 23 comprises Al having a fourth Al composition D_DGa_(1-D)As, the fourth Al composition D is different from the Al composition (the first Al composition a and the second Al composition B) of the n-type composite layer 15. The fourth Al composition D is more specifically less than nAl composition (D) of the composite layer 15<B<A)。

The fourth Al composition D may be more than 0 and 0.2 or less. The fourth Al composition D may be greater than 0 and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, or 0.15 or more and 0.2 or less. The barrier layer 23 may be added without impurities.

The barrier layer 23 may also have a different thickness from the well layer 22. The barrier layer 23 may have a thickness greater than that of the well layer 22 and less than that of the first guide layer 16. The thickness of the barrier layer 23 may also beAbove andthe following. The thickness of the first guide layer 16 may be set to beAbove andthe following components,Above andthe following components,Above andthe following, orAbove andthe following.

The second guide layer 18 includes Al having a fifth Al composition E_EGa_(1-E)As, the fifth Al composition E is different from the Al composition (the first Al composition a and the second Al composition B) of the n-type composite layer 15. The fifth Al composition E is more specifically an Al composition (E) smaller than the n-type composite layer 15<B<A) In that respect The fifth Al composition E may be greater than 0 and 0.2 or less.

The fifth Al composition E may be greater than 0 and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, or 0.15 or more and 0.2 or less. The second guide layer 18 may be added without impurities.

The thickness of the second guide layer 18 may exceed the thickness of the barrier layer 23. The thickness of the second guide layer 18 may be setAbove andthe following. The thickness of the second guide layer 18 may be setAbove andthe following components,Above andthe following components,Above andthe following, orAbove andthe following.

The p-type composite layer 19 contains AlGaAs to which a p-type impurity is added. The p-type impurity may also contain C (carbon). The p-type impurity concentration of the p-type composite layer 19 may be 1 × 10¹⁷cm^-3Above and 1 × 10¹⁹cm^-3The following. The p-type composite layer 19 in this embodiment includes a first p-type composite layer 24 and a second p-type composite layer 25 stacked in this order from the active layer 17 side.

The first p-type composite layer 24 includes Al having a sixth Al composition F_FGa_(1-F)As. The sixth Al composition F may be 0.2 or more and 0.4 or less. The sixth Al composition F may be 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, or 0.35 or more and 0.4 or less. The p-type impurity concentration of the first p-type composite layer 24 may also be 1 × 10¹⁷cm^-3Above and 5 × 10¹⁸cm^-3The following.

The thickness of the first p-type composite layer 24 may beAbove andthe following. The thickness of the first p-type composite layer 24 may also beAbove andthe following components,Above andthe following components,Above andthe following components,Above andthe following components,Above andthe following components,Above andthe following, orAbove andthe following.

The second p-type composite layer 25 contains Al having a seventh Al composition G_GGa_(1-G)As, the seventh Al composition G is different from the sixth Al composition F of the first p-type composite layer 24. The seventh Al composition G is more specifically larger than the sixth Al composition F (F)<G) In that respect The seventh Al composition G may be 0.4 or more and 0.6 or less. The seventh Al composition G may be 0.4 or more and 0.45 or less, 0.45 or more and 0.5 or less, 0.5 or more and 0.55 or less, or 0.55 or more and 0.6 or less.

The second p-type composite layer 25 has a p-type impurity concentration different from that of the first p-type composite layer 24. The p-type impurity concentration of the second p-type composite layer 25 is more specifically greater than that of the first p-type composite layer 24. The p-type impurity concentration of the second p-type composite layer 25 may be 5 × 10¹⁷cm^-3Above and 1 × 10¹⁹cm^-3The following.

The second p-type composite layer 25 may also have a thickness different from that of the first p-type composite layer 24. The second p-type composite layer 25 may also have a thickness smaller than that of the first p-type composite layer 24.

The thickness of the second p-type composite layer 25 may beAbove andthe following. The thickness of the second p-type composite layer 25 may be setAbove andthe following components,Above andthe following components,Above andthe following components,Above andthe following components,Above andthe following, orAbove andthe following.

Referring to fig. 8, the plurality of tunnel junction layers 14 include a first tunnel junction layer 14A and a second tunnel junction layer 14B. The first tunnel junction layer 14A is interposed in a region between the first light emitting unit layer 13A and the second light emitting unit layer 13B. The second tunnel junction layer 14B is interposed in a region between the second light emitting unit layer 13B and the third light emitting unit layer 13C.

The first tunnel junction layer 14A and the second tunnel junction layer 14B each have a p-type tunnel junction layer 26 and an n-type tunnel junction layer 27 stacked in this order from the substrate 2 side. The first tunnel junction layer 14A and the second tunnel junction layer 14B are interposed in regions between the plurality of light emitting cell layers 13A to 13C so that the p-type tunnel junction layer 26 is electrically connected to the p-type composite layer 19 and the n-type tunnel junction layer 27 is electrically connected to the n-type composite layer 15.

p-type tunnel junction layer 26 contains GaAs with an added p-type impurity. The p-type impurity may also contain C (carbon). p-type tunnel junction layer 26 has a p-type impurity concentration different from that of p-type composite layer 19. The p-type impurity concentration of p-type tunnel junction layer 26 is more specifically greater than the p-type impurity concentration of p-type composite layer 19. The p-type impurity concentration of p-type tunnel junction layer 26 may be 1 × 10¹⁸cm^-3Above and 1 × 10²⁰cm^-3The following.

The p-type tunnel junction layer 26 may have a thickness ofAbove andthe following. The p-type tunnel junction layer 26 may also have a thickness ofAbove andthe following components,Above andthe following components,Above andthe following components,Above andthe following, orAbove andthe following.

The n-type tunnel junction layer 27 contains GaAs with an n-type impurity added thereto. The n-type impurity may also include at least 1 of Si (silicon), Te (tellurium), and Se (selenium). n-type tunnel junction layer 27 has an n-type impurity concentration different from the n-type impurity concentration of n-type composite layer 15. The n-type impurity concentration of n-type tunnel junction layer 27 is more specifically greater than the n-type impurity concentration of n-type composite layer 15. The n-type impurity concentration of n-type tunnel junction layer 27 may be 5 × 10¹⁷cm^-3Above and 5 × 10¹⁹cm^-3The following.

The n-type tunnel junction layer 27 may also have a thickness ofAbove andthe following. n-type tunnel junctionThe thickness of layer 27 may also beAbove andthe following components,Above andthe following components,Above andthe following components,Above andthe following, orAbove andthe following.

Referring to fig. 3 to 6, the p-type contact layer 12 is formed on the light emitting layer 11. The semiconductor main surface 7 of the semiconductor layer 6 is formed by a p-type contact layer 12. The p-type contact layer 12 contains GaAs with an added p-type impurity. The p-type impurity may also contain C (carbon).

The p-type contact layer 12 has a p-type impurity concentration different from that of the p-type composite layer 19. The p-type contact layer 12 has a p-type impurity concentration, more specifically, a p-type impurity concentration greater than that of the p-type composite layer 19. The p-type impurity concentration of the p-type contact layer 12 may be 5 × 10¹⁸cm^-3Above and 1 × 10²⁰cm^-3The following.

The thickness of the p-type contact layer 12 may be set toAbove andthe following. The thickness of the p-type contact layer 12 may be set toAbove andthe following components,Above andthe following components,Above andthe following, orAbove andthe following.

Referring to fig. 1 to 6, semiconductor layer 6 includes light emitting region 31, pad region 32, and outer region 33. The light emitting region 31 is a region where laser light is generated. The pad region 32 and the outer region 33 are regions where no laser light is generated. The pad area 32 is an area to which a wire 34 is connected. The outer region 33 is a region where the wires 34 are not connected.

The light emitting region 31 is formed in a band shape extending along the first direction X. Light-emitting region 31 is formed offset in second direction Y with respect to the center of substrate 2 in the top view. In this embodiment, light-emitting region 31 is biased from the center of substrate 2 toward second substrate side 5B in plan view.

The light-emitting region 31 has a first width W1 with respect to the second direction Y. Light-emitting region 31 has a first area S1 in a top view. The first area S1 has a value (L1 × W1) obtained by multiplying the length L1 of the first substrate side 5A by the first width W1.

The first width W1 may be 40 μm or more and 100 μm or less. The first width W1 may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, or 90 μm or more and 100 μm or less. The first width W1 is preferably 50 μm or more and 80 μm or less.

The pad region 32 is formed in a region on the first substrate side 5A side with respect to the light-emitting region 31. The pad region 32 is formed in a band shape extending along the first direction X. The pad region 32 has a second width W2 with respect to the second direction Y that is greater than the first width W1(W1< W2). The pad region 32 has a second area S2 greater than the first area S1 in the top view (S1< S2). The second area S2 has a value (L1 × W2) obtained by multiplying the length L1 of the first substrate side 5A by the second width W2.

The second width W2 is preferably greater than or equal to 1/4 and less than or equal to 2/3 of the length L2 of the third substrate side 5C. The second width W2 is preferably 1.5 times or more and 4 times or less the first width W1. The second width W2 may be 150 μm or more and 300 μm or less. The second width W2 may be 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or less, 225 μm or more and 250 μm or less, 250 μm or more and 275 μm or less, or 275 μm or more and 300 μm or less. The second width W2 is preferably 150 μm or more and 250 μm or less.

The outer region 33 is formed in a region on the second substrate side 5B side with respect to the light-emitting region 31. The outer region 33 is formed in a band shape extending along the first direction X. The outer region 33 has a third width W3 with respect to the second direction Y. The size of the third width W3 is arbitrary and can be adjusted according to the size of the first width W1 and the size of the second width W2.

From the viewpoint of securing the pad region 32, the third width W3 is preferably smaller than the second width W2(W3< W2). The third width W3 may be equal to or greater than the first width W1(W1 ≦ W3), or may be smaller than the first width W1(W3< W2). The third width W3 is adjusted to be greater than or equal to the first width W1 and smaller than the second width W2 in this manner (W1 ≦ W3< W2).

The outer region 33 has a third area S3 that is greater than or equal to the first area S1 and smaller than the second area S2 in plan view (S1 ≦ S3< S2). The third area S3 has a value (L1 × W3) obtained by multiplying the length L1 of the first substrate side 5A by the third width W3.

The third width W3 may be 25 μm or more and less than 150 μm. The third width W3 may be 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, or 125 μm or more and 150 μm or less. The third width W3 is preferably 50 μm or more and 100 μm or less.

The light-emitting region 31, the pad region 32, and the outer region 33 are divided by a first channel 41 and a second channel 42 formed in the semiconductor main surface 7 of the semiconductor layer 6, respectively. The first channel 41 is formed in a region between the light emitting region 31 and the pad region 32. The second trench 42 is formed in a region between the light-emitting region 31 and the outer region 33.

The first trench 41 and the second trench 42 are formed by removing unnecessary portions of the semiconductor layer 6 by an etching method using a resist mask. The etching method may be wet etching or dry etching.

The first channel 41 is formed in a band shape extending along the first direction X in a plan view. The first channel 41 communicates with the third semiconductor side 8C and the fourth semiconductor side 8D. The first channel 41 penetrates the p-type contact layer 12 and the light-emitting layer 11 so as to reach at least the second n-type composite layer 21 of the lowermost light-emitting cell layer 13 (first light-emitting cell layer 13A). In this embodiment, the first trench 41 penetrates the p-type contact layer 12, the light-emitting layer 11, and the n-type buffer layer 10 to reach the substrate 2.

The first channel 41 has a first sidewall 43 on the light emitting region 31 side, a second sidewall 44 on the pad region 32 side, and a bottom wall 45 connecting the first sidewall 43 and the second sidewall 44. The p-type contact layer 12, the light emitting layer 11, the n-type buffer layer 10, and the substrate 2 are exposed from the first and second sidewalls 43 and 44. The substrate 2 is exposed from the bottom wall 45. The first trench 41 is formed in a tapered shape with a narrow opening width from the semiconductor main surface 7 toward the bottom wall 45.

The second channel 42 is formed in a band shape extending along the first direction X in a plan view. The second channel 42 communicates with the third semiconductor side 8C and the fourth semiconductor side 8D. The second channel 42 penetrates the p-type contact layer 12 and the light-emitting layer 11 so as to reach at least the second n-type composite layer 21 of the lowermost light-emitting cell layer 13 (first light-emitting cell layer 13A). The second trench 42 penetrates the p-type contact layer 12, the light-emitting layer 11, and the n-type buffer layer 10 in this manner, and reaches the substrate 2.

The second channel 42 has a first sidewall 46 on the outer region 33 side, a second sidewall 47 on the light-emitting region 31 side, and a bottom wall 48 connecting the first sidewall 46 and the second sidewall 47. The p-type contact layer 12, the light emitting layer 11, the n-type buffer layer 10, and the substrate 2 are exposed from the first and second sidewalls 46 and 47. The substrate 2 is exposed from the bottom wall 48. The second trench 42 is formed in a tapered shape with a narrow opening width from the semiconductor main surface 7 toward the bottom wall 48.

The first width W1 of the light emitting region 31 is defined by the width between the bottom wall 45 of the first channel 41 and the bottom wall 48 of the second channel 42 with respect to the second direction Y. The second width W2 of the pad region 32 is defined with respect to the second direction Y by the width between the bottom wall 45 of the first channel 41 and the first semiconductor side 8A (first substrate side 5A).

The third width W3 of the outer region 33 is defined by the width between the bottom wall 48 of the second channel 42 and the second semiconductor side 8B (second substrate side 5B) with respect to the second direction Y. Light-emitting region 31, pad region 32, and outer region 33 are specifically specified by the following configuration.

The light emitting region 31 has a mesa structure 51 in a raised shape (mountain shape) protruding from the first substrate main surface 3 to the side opposite to the second substrate main surface 4. The mesa formation 51 is divided by the first trench 41 and the second trench 42. Mesa configuration 51 includes a top 52, a base 53, a first sidewall 54 on the bond pad region 32 side, and a second sidewall 55 on the outer region 33 side.

The top portion 52 is formed by a portion of the semiconductor main face 7. That is, the top portion 52 is formed by the p-type contact layer 12. The top 52 is formed parallel to the first main substrate surface 3 of the substrate 2. The base 53 is preferably located on the substrate 2 side at least with respect to the light emitting layer 11. The base 53 is formed in this manner by the substrate 2. The base 53 may be formed of the n-type buffer layer 10.

The first sidewall 54 is formed by the first sidewall 43 of the first trench 41. Second sidewall 55 is formed by second sidewall 47 of second trench 42. First and second sidewalls 54 and 55 connect top 52 and base 53, respectively. The first and second sidewalls 54 and 55 are formed of the p-type contact layer 12, the light emitting layer 11, the n-type buffer layer 10, and the substrate 2, respectively.

The mesa configuration 51 also includes a first end surface 56 and a second end surface 57. The first end face 56 is exposed from the third substrate side face 5C. More specifically, the first end surface 56 is formed on the same plane as the third substrate side surface 5C. The first end surface 56 forms a mirror surface. The first end face 56 forms in this manner a cleavage plane with the third substrate side 5C.

The second end face 57 is exposed from the fourth substrate side face 5D. The second end face 57 is formed on the same plane with respect to the fourth substrate side face 5D more specifically. The second end surface 57 forms a mirror surface. The second end face 57 forms in this manner a cleavage plane between it and the fourth substrate side 5D.

The first end surface 56 and the second end surface 57 form a resonator end surface. The light generated by the light emitting layer 11 reciprocates between the first end face 56 and the second end face 57, and is amplified by stimulated emission. The amplified light is extracted as laser light from either the first end surface 56 or the second end surface 57 to the outside of the semiconductor layer 6.

The peripheral edge of the top portion 52 is located more inward than the peripheral edge of the base portion 53 in plan view. That is, the planar area of the region surrounded by the peripheral edge of the top portion 52 is smaller than the planar area of the region surrounded by the peripheral edge of the base portion 53. The first side wall 54 and the second side wall 55 are inclined downward from the top 52 to the base 53 in this manner. The first and second sidewalls 54 and 55 may also be formed perpendicularly with respect to the top 52.

In the mesa structure 51, the angle θ 1 formed between the first sidewall 54 and the first substrate main surface 3 may be 50 ° or more and 90 ° or less. The angle θ 1 may be 50 ° or more and 60 ° or less, 60 ° or more and 70 ° or less, 70 ° or more and 80 ° or less, or 80 ° or more and 90 ° or less. When the angle θ 1 is smaller than 80 °, light leaks from the first side wall 54 of the mesa structure 51.

Therefore, the angle θ 1 is preferably 80 ° or more. In this case, the angle θ 1 is preferably 80 ° or more and 82.5 ° or less, 82.5 ° or more and 85 ° or less, 85 ° or more and 87.5 ° or less, or 87.5 ° or more and 90 ° or less. The first side wall 54 may be formed so that the angle θ 1 gradually increases from the top portion 52 to the base portion 53 in a range of 50 ° to 90 °.

Similarly, in the mesa structure 51, the angle θ 2 formed between the second side wall 55 and the first substrate main surface 3 may be 50 ° or more and 90 ° or less. The angle θ 2 may be 50 ° or more and 60 ° or less, 60 ° or more and 70 ° or less, 70 ° or more and 80 ° or less, or 80 ° or more and 90 ° or less. The angle θ 2 is preferably 80 ° or more and 82.5 ° or less, 82.5 ° or more and 85 ° or less, 85 ° or more and 87.5 ° or less, or 87.5 ° or more and 90 ° or less. The second side wall 55 may be formed so that the angle θ 2 gradually increases from the top portion 52 to the base portion 53 in a range of 50 ° to 90 °.

The width of the top portion 52 in the second direction Y may be 10 μm or more and 100 μm or less. The width of the top portion 52 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. The width of the top portion 52 in the second direction Y is preferably 20 μm or more and 60 μm or less. The width of the base portion 53 in the second direction Y is the first width W1 of the light-emitting region 31.

The pad region 32 has a land-shaped (ridge-shaped) pad mesa structure 61 protruding from the first substrate main surface 3 to the side opposite to the second substrate main surface 4. The pad mesa formation 61 is divided by the first trench 41 and the semiconductor flanks 8A, 8C, 8D. Pad mesa structure 61 includes a pad top 62, a pad base 63, and a pad sidewall 64.

The pad top 62 is formed by a portion of the semiconductor main surface 7. That is, the pad top 62 of the pad mesa structure 61 is located on the same plane as the top 52 of the mesa structure 51. In addition, the pad top 62 is formed by the p-type contact layer 12. The pad tip 62 is formed parallel to the first substrate main surface 3 of the substrate 2.

The pad base 63 is preferably located on the substrate 2 side at least with respect to the light emitting layer 11. The pad base 63 is formed by the substrate 2 in this manner. The pad base 63 may be formed of the n-type buffer layer 10.

A pad sidewall 64 is formed by the second sidewall 44 of the first trench 41. Pad sidewall 64 connects pad top 62 and pad base 63. The pad sidewall 64 is formed by the p-type contact layer 12, the light emitting layer 11, the n-type buffer layer 10, and the substrate 2, respectively.

In the top view, the peripheral edge of the pad top 62 is located inward from the peripheral edge of the pad base 63. That is, the planar area of the region surrounded by the peripheral edge of the pad top 62 is smaller than the planar area of the region surrounded by the peripheral edge of the pad base 63. Pad sidewall 64 slopes downward in this manner from pad top 62 to pad base 63. The pad sidewall 64 may also be formed vertically with respect to the pad top 62.

In the pad mesa structure 61, an angle θ 3 formed between the pad sidewall 64 and the first substrate main surface 3 may be 80 ° or more and 90 ° or less. The angle θ 3 may be 80 ° or more and 82.5 ° or less, 82.5 ° or more and 85 ° or less, 85 ° or more and 87.5 ° or less, or 87.5 ° or more and 90 ° or less.

The width of the pad top 62 in the second direction Y may be 120 μm or more and 280 μm or less. The width of the pad top 62 may be 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, 180 μm or more and 200 μm or less, 200 μm or more and 220 μm or less, 220 μm or more and 240 μm or less, 240 μm or more and 260 μm or less, or 260 μm or more and 280 μm or less. The width of the second direction Y of the pad base 63 is the second width W2 of the pad region 32.

The outer region 33 has an outer mesa structure 71 in a plateau shape (ridge shape) protruding from the first substrate main surface 3 to the side opposite to the second substrate main surface 4. The outer mesa formation 71 is divided by the second trench 42 and the semiconductor flanks 8B, 8C, 8D. The outboard mesa configuration 71 includes an outboard top 72, an outboard base 73, and an outboard sidewall 74.

The outer top 72 is formed by a portion of the semiconductor main surface 7. That is, the outer top 72 of the outer mesa 71 is in the same plane as the top 52 of the mesa 51. In addition, the outer top portion 72 is formed by the p-type contact layer 12. The outer top 72 is formed parallel to the first substrate main surface 3 of the substrate 2.

The outer base 73 is preferably disposed on the substrate 2 side with respect to at least the light-emitting layer 11. The outer base 73 is formed in this way by the substrate 2. The outer base 73 may be formed of the n-type buffer layer 10.

The outboard sidewall 74 is formed by the first sidewall 46 of the second channel 42. An outboard sidewall 74 connects the outboard top 72 and the outboard base 73. The outer side wall 74 is formed by the p-type contact layer 12, the light emitting layer 11, the n-type buffer layer 10, and the substrate 2, respectively.

In plan view, the peripheral edge of the outboard top 72 is located inward of the peripheral edge of the outboard base 73. That is, the planar area of the region surrounded by the peripheral edge of the outside top 72 is smaller than the planar area of the region surrounded by the peripheral edge of the outside base 73. The outboard side wall 74 is inclined downwardly from the outboard top 72 to the outboard base 73 in this manner. The outboard sidewall 74 may also be formed perpendicularly with respect to the outboard top 72.

In the outer mesa structure 71, the angle θ 4 formed between the outer sidewall 74 and the first substrate main surface 3 may be 80 ° or more and 90 ° or less. The angle θ 4 may be 80 ° or more and 82.5 ° or less, 82.5 ° or more and 85 ° or less, 85 ° or more and 87.5 ° or less, or 87.5 ° or more and 90 ° or less.

The width of the outer top 72 in the second direction Y may be 10 μm or more and less than 125 μm. The third width W3 may be 10 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, or 100 μm or more and 125 μm or less. The width of the outer base 73 in the second direction Y is the third width W3 of the outer region 33.

Referring to fig. 4, mesa configuration 51 includes contact hole 79 formed in top 52. The contact hole 79 is formed in the surface layer portion of the p-type contact layer 12. The contact hole 79 is recessed in the top portion 52 toward the base portion 53. In this manner, the contact holes 79 are formed at intervals inward from the peripheral edge of the top portion 52.

The contact holes 79 extend in a strip shape along the second direction Y in the plan view. The contact hole 79 may communicate with the first and second end faces 56 and 57. The contact hole 79 may be formed in a region surrounded by the peripheral edge of the top portion 52 so as not to communicate with the first end surface 56 and the second end surface 57.

The contact hole 79 may haveAbove andthe following depths. The depth can also beAbove andthe following components,Above andthe following components,Above andthe following, orAbove andthe following. The depth is preferablyAbove andthe following.

The semiconductor laser device 1 further includes an insulating layer 80 covering the semiconductor main surface 7. In fig. 2, the insulating layer 80 is shaded for clarity. The insulating layer 80 is formed in a film shape on the semiconductor main surface 7. The insulating layer 80 may also comprise silicon nitride or silicon oxide. The insulating layer 80 comprises silicon nitride in this manner.

The insulating layer 80 integrally includes a first region 81, a second region 82, and a third region 83. The first region 81 covers the light emitting region 31. The second area 82 covers the pad area 32. The third region 83 covers the outer region 33.

The first region 81 covers the top 52, base 53, first side wall 54 and second side wall 55 of the mesa configuration 51. Second region 82 covers pad top 62, pad base 63, and pad sidewalls 64 of pad mesa structure 61. In the second region 82, a portion covering the pad top 62 of the pad mesa structure 61 is formed at an interval inward from the first semiconductor side surface 8A. Thereby, the peripheral edge of the semiconductor main surface 7 on the first semiconductor side surface 8A side is exposed from the insulating layer 80 (second region 82).

The third region 83 covers the outboard top 72, outboard base 73, and outboard sidewall 74 of the outboard mesa configuration 71. The third region 83 is formed so as to cover the outer top portion 72 with a space inward from the second semiconductor side surface 8B. Thereby, the peripheral edge of the semiconductor main surface 7 on the second semiconductor side surface 8B side is exposed from the insulating layer 80 (third region 83).

In a portion of the insulating layer 80 (first region 81) covering the top 52 of the mesa structure 51, a contact opening 84 is formed. The contact opening 84 communicates with the contact hole 79. The contact opening 84 exposes the inner wall of the contact hole 79. The inner walls of the contact openings 84 extend along the inner walls of the contact holes 79. The insulating layer 80 may expose the inner wall of the contact hole 79. The insulating layer 80 may also cover the inner wall of the contact hole 79.

The semiconductor laser device 1 further includes a wiring electrode 88 formed on the insulating layer 80. The wiring electrode 88 is formed in a film shape on the insulating layer 80. The wiring electrode 88 includes: an internal connection region 89 that penetrates the insulating layer 80 and is electrically connected to the light-emitting region 31; and an external connection region 90 that covers the pad region 32 with an insulating layer 80 interposed therebetween and makes external connection with the wire 34.

More specifically, the wiring electrode 88 integrally includes: a first wiring region 91 covering the light-emitting region 31; a second wiring region 92 covering the pad region 32; and a third wiring region 93 covering the outer region 33.

The first wiring region 91 covers the top 52, the base 53, the first sidewall 54, and the second sidewall 55 of the mesa structure 51 via the first region 81 of the insulating layer 80. The first wiring region 91 enters the contact opening 84 of the insulating layer 80 at the top 52 of the mesa structure 51, and is electrically connected to the light-emitting region 31.

The first wiring region 91 is electrically connected to the p-type contact layer 12 in the contact hole 79. An internal connection region 89 is formed in the first wiring region 91 at a portion connected to the p-type contact layer 12.

The second wiring region 92 covers the pad top 62, the pad base 63, and the pad sidewall 64 of the pad mesa structure 61 via the second region 82 of the insulating layer 80. The second wiring region 92 is formed at a distance from the peripheral edge of the second region 82 toward the light-emitting region 31, in a portion covering the second region 82.

Thereby, the peripheral edge of the second region 82 is exposed from the second wiring region 92. The second wiring region 92 is formed with an external connection region 90 for external connection to the lead 34, at a portion covering the pad top 62 of the pad mesa structure 61.

The third wiring region 93 covers the outer top portion 72, the outer base portion 73, and the outer side wall 74 of the outer mesa structure 71 with the third region 83 of the insulating layer 80 interposed therebetween. The third wiring region 93 is formed at a distance from the peripheral edge of the third region 83 toward the light-emitting region 31, in a portion covering the outer top 72. Thereby, the peripheral edge of the third region 83 is exposed from the third wiring region 93.

The third wiring region 93 may be removed. However, in view of the stress applied to light-emitting region 31, light-emitting region 31 preferably has a structure sandwiched between second wiring region 92 and third wiring region 93. In this case, a balance can be achieved between the stress applied to the light-emitting region 31 due to the second wiring region 92 and the stress applied to the light-emitting region 31 due to the third wiring region 93.

The wiring electrode 88 may have a laminated structure in which a plurality of electrode layers are laminated. In this embodiment, the wiring electrode 88 includes a first electrode 95 and a second electrode 96 which are stacked in this order from the insulating layer 80 side.

The first electrode 95 may be a barrier electrode layer including at least 1 of a Pt (platinum) layer, a Ti (titanium) layer, and a TiN (titanium nitride) layer. The thickness of the first electrode 95 may be 10nm or more and 200nm or less. The thickness of the first electrode 95 may be 10nm to 50nm, 50nm to 100nm, 100nm to 150nm, or 150nm to 200 nm.

The second electrode 96 may be a low-resistance electrode layer including an Au (gold) layer. The thickness of the second electrode 96 is greater than the thickness of the first electrode 95. The thickness of the second electrode 96 may be 1 μm or more and 5 μm or less. The thickness of the second electrode 96 may be 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, or 4.5 μm or more and 5 μm or less.

The semiconductor laser device 1 further includes an electrode 97 formed on the second substrate main surface 4. The electrode 97 is electrically connected to the substrate 2. In this embodiment, the electrode 97 covers the front surface of the second substrate main surface 4. The electrode 97 may be formed on the second substrate main surface 4 so that the peripheral edge portion of the second substrate main surface 4 is exposed. The electrode 97 may have a stacked structure including a plurality of electrode layers.

The electrode 97 may also include at least one of a Ni (nickel) layer, an AuGe (gold-germanium alloy) layer, a Ti (titanium) layer, and an Au (gold) layer. The electrode 97 may have a laminated structure in which at least two of a Ni layer, an AuGe layer, a Ti layer, and an Au layer are laminated in an arbitrary manner. The electrode 97 may include an AuGe layer, an Ni layer, a Ti layer, and an Au layer stacked in this order from the second substrate main surface 4 side.

Referring to fig. 1 to 3, 1 or more leads 34 are connected to an external connection region 90 (second wiring region 92) of the wiring electrode 88. The number of the wires 34 is arbitrary and is not limited to a specific number. In this embodiment, an example is shown in which 3 lead wires 34A, 34B, and 34C are connected to the external connection region 90 (second wiring region 92).

Each wire 34 may comprise a bond wire or Clip wire. Each wire 34 is formed by a bonding wire in this manner. The clip wire has the same form as the bonding wire except that it is formed of a metal plate having a relatively wide width.

Each of the wires 34 may include at least 1 of gold wire, silver wire, aluminum wire, and copper wire as an example of the bonding wire. Each of the wires 34 is preferably formed of a gold wire.

Each wire 34 includes a bonding portion 98 and a wire portion 99. The joint 98 is a portion connected to the external connection region 90. When each of the wires 34 is formed of a bonding wire, the joint portion 98 is sometimes referred to as a "lead ball (wire ball)", "bump (stud bump)", or the like. The lead portion 99 is a portion linearly extending from the joint portion 98 to another connection target.

Referring to fig. 2, the joint 98 has a connection width WC (W1< WC) greater than the first width W1 of the light-emitting region 31 with respect to the second direction Y. The connection width WC is smaller than the second width W2 of the pad area 32 (WC < W2). In this embodiment, the connection width WC is equal to or greater than the third width W3 of the outer region 33 (W3 ≦ WC). The connection width WC is more specifically larger than the third width W3(W3< WC).

The connection width WC may be 50 μm or more and less than 300 μm. The connection width WC may be 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, or 250 μm or more and less than 300 μm. The connection width WC is 80 μm or more and 150 μm or less in this embodiment.

It is also conceivable to connect lead lines 34A to 34C to light-emitting region 31. However, in this case, since bonding portion 98 has a connection width WC (W1< WC) exceeding first width W1 of light-emitting region 31, the connection area of bonding portion 98 to light-emitting region 31 is insufficient, and wires 34A to 34C cannot be appropriately electrically connected to light-emitting region 31. Further, a failure may occur in light-emitting region 31 due to external force or stress at the time of connection of lead wires 34A to 34C.

Therefore, in the semiconductor laser device 1, the pad region 32 of the connection wires 34A to 34C is formed in a region outside the light emitting region 31. This allows light-emitting region 31 to be reduced appropriately without being subjected to design restrictions due to wires 34A to 34C. This can suppress unwanted diffusion of the current in the mesa structure 51, and therefore can improve the directivity of the laser light.

Fig. 9 is a perspective view showing a semiconductor laser device 101 according to a second embodiment of the present invention together with a lead wire 34 connected to the semiconductor laser device 101. Fig. 10 is a plan view of the semiconductor laser device 101 shown in fig. 9. Fig. 11 is a sectional view taken along line XI-XI shown in fig. 10. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described for the semiconductor laser device 1, and the description thereof is omitted.

In the semiconductor laser device 101, the pad region 32 does not have the pad mesa structure 61. The pad region 32 is formed on the base 53 side with respect to the top 52 of the mesa structure 51 of the light-emitting region 31. The pad region 32 is more specifically formed on the first substrate main surface 3 of the substrate 2. The portion of the first substrate main surface 3 where the pad region 32 is formed may be located on the second substrate main surface 4 side with respect to the portion of the first substrate main surface 3 located within the mesa structure 51.

In the semiconductor laser device 101, the outer region 33 does not have the outer mesa structure 71. The outer region 33 is formed on the base 53 side with respect to the top 52 of the mesa structure 51 of the light-emitting region 31. The outer region 33 is more specifically formed on the first substrate main surface 3 of the substrate 2. The portion of the first substrate main surface 3 where the outer region 33 is formed may be located on the second substrate main surface 4 side with respect to the portion of the first substrate main surface 3 located within the mesa structure 51. The outer region 33 may be in the same plane as the pad region 32.

The second region 82 of the insulating layer 80 covers the first substrate main face 3 in the pad region 32. The third region 83 of the insulating layer 80 covers the first substrate main surface 3 in the outer region 33. The second wiring region 92 of the wiring electrode 88 covers the first substrate main surface 3 via the second region 82 of the insulating layer 80. The third wiring region 93 of the wiring electrode 88 covers the first substrate main surface 3 via the third region 83 of the insulating layer 80.

As described above, the semiconductor laser device 101 can also achieve the same effects as those described for the semiconductor laser device 1. In this embodiment, an example in which the pad region 32 and the outer region 33 are formed by the first substrate main surface 3 is described. However, the pad region 32 and the outer region 33 may be formed of the n-type buffer layer 10, respectively.

Fig. 12 is a perspective view showing a semiconductor laser device 111 according to a third embodiment of the present invention together with a lead wire 34 connected to the semiconductor laser device 111. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described for the semiconductor laser device 1, and the description thereof is omitted.

The semiconductor laser device 1 has a structure in which the outer region 33 is not connected to the lead wire 34. In contrast, in the semiconductor laser device 111, the outer region 33 has the same structure as the pad region 32. That is, in the semiconductor laser device 111, the outer region 33 is formed as the second pad region 121 to which the wire 34 is connected.

The third width W3 of the outer region 33 is greater than the first width W1 of the light-emitting region 31 (W1< W3). The third width W3 is preferably greater than or equal to 1/4 and less than or equal to 2/3 of the length L2 of the third substrate side 5C. The third width W3 is preferably 1.5 times or more and 4 times or less the first width W1. The third area S3 of the outside area 33 has a relationship larger than the first area S1(S1< S3) in plan view.

The third width W3 may be 150 μm or more and 300 μm or less. The second width W2 may be 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or less, 225 μm or more and 250 μm or less, 250 μm or more and 275 μm or less, or 275 μm or more and 300 μm or less. The third width W3 is preferably 150 μm or more and 250 μm or less.

The third width W3 of the outer region 33 may be equal to or greater than the second width W2 of the pad region 32 (W2 ≦ W3), or may be smaller than the second width W2 of the pad region 32 (W3< W2). In this embodiment, the third width W3 is equal to the second width W2 (W2 — W3).

In the third wiring region 93 of the wiring electrode 88, which covers the outer top portion 72 of the outer mesa structure 71, a second external connection region 113 for external connection to the lead wire 34 is formed, similarly to the second wiring region 92.

In the external connection region 90 (second wiring region 92) and the second external connection region 113 (third wiring region 93), 1 or more leads 34 are connected, respectively. The number of the wires 34 is arbitrary and is not limited to a specific number. In this embodiment, an example is shown in which 3 lead wires 34A, 34B, and 34C are connected to the external connection region 90 (second wiring region 92), and 3 lead wires 34D, 34E, and 34F are connected to the second external connection region 113 (third wiring region 93).

As described above, the semiconductor laser device 111 can also achieve the same effects as those described for the semiconductor laser device 1. The structure of connecting the lead wires 34 to the second external connection region 113 (third wiring region 93) can also be applied to the second embodiment described above.

Fig. 13 is an exploded perspective view showing a package 201 according to the first embodiment. Hereinafter, an example in which the semiconductor laser device 1 is mounted on the package 201 will be described. However, the semiconductor laser device 101 or the semiconductor laser device 111 may be mounted on the package 201 instead of the semiconductor laser device 1.

Referring to fig. 13, a package 201 is a metal case in which a semiconductor core (stem) of a semiconductor laser device 1 is housed. The package 201 includes: a semiconductor laser device 1, a core rod base 202, a first lead terminal 203, a second lead terminal 204, a third lead terminal 205, a first insulator 206, a second insulator 207, a heat sink (heat sink, heat absorbing member, heat sink) 208, a photodiode 209, a first wire 210, a second wire 211, a cap 212, and a sealing member 213.

The mandrel base 202 includes a plate-like member made of metal (e.g., iron). The mandrel base 202 is formed in a disk shape in this embodiment. The mandrel base 202 has a first surface 214 on one side, a second surface 215 on the other side, and a side surface 216 connecting the first surface 214 and the second surface 215.

A plurality of (3 in this embodiment) notch portions are formed at intervals in an arbitrary region on the side surface 216 of the mandrel base 202. The plurality of notched portions include a first notched portion 217, a second notched portion 218, and a third notched portion 219.

The first notch 217 is recessed in a quadrangular shape toward the center of the mandrel base 202. The second cutout portion 218 and the third cutout portion 219 are each recessed in a triangular shape toward the center portion of the plug base 202. The second notch portion 218 and the third notch portion 219 face each other across the center portion of the mandrel base 202. The first notched portion 217, the second notched portion 218, and the third notched portion 219 also represent the arrangement of the first lead terminal 203, the second lead terminal 204, and the third lead terminal 205.

The first lead terminal 203, the second lead terminal 204, and the third lead terminal 205 are disposed on the second surface 215 of the mandrel base 202 at intervals from each other. The first lead terminal 203, the second lead terminal 204, and the third lead terminal 205 are respectively extended in a rod shape, a column shape, or an axis shape along a normal direction of the second surface 215.

The first lead terminal 203 is connected to the second surface 215 of the mandrel base 202. Thereby, the first lead terminal 203 is electrically connected to the mandrel base 202.

The second lead terminal 204 includes a lead portion 220 led from the second surface 215 side of the plug base 202 to the first surface 214 side of the plug base 202. The lead-out portion 220 of the second lead terminal 204 is led out through a first through hole 221 formed in the mandrel base 202.

The third lead terminal 205 includes a lead-out portion 222 led out from the second surface 215 side of the plug base 202 to the first surface 214 side of the plug base 202. The lead-out portion 222 of the third lead terminal 205 is led out through a second through hole 223 formed in the mandrel base 202.

The first insulator 206 is inserted between the second lead terminal 204 and the mandrel base 202 through the first through hole 221. The first insulator 206 electrically insulates the second lead terminal 204 from the mandrel base 202. The first insulator 206 supports the second lead terminal 204.

Second insulator 207 is inserted between third lead terminal 205 and mandrel base 202 through second through hole 223. The second insulator 207 electrically insulates the third lead terminal 205 from the mandrel base 202. The second insulator 207 supports the third lead terminal 205.

The heat sink 208 is disposed on a first side 214 of the mandrel base 202. The heat sink 208 includes a block-shaped or plate-shaped member made of silicon, aluminum nitride, or metal (e.g., iron). The heat sink 208 is integrally formed with respect to the first face 214.

The heat sink 208 may be disposed on the peripheral edge portion side of the mandrel base 202 with respect to the central portion of the mandrel base 202 in a plan view seen from the normal direction of the first surface 214. The heat sink 208 has a first mounting surface 224. The first mounting surface 224 extends in a direction normal to the first surface 214. The first mounting surface 224 is oriented toward a central portion of the mandrel base 202.

The semiconductor laser device 1 is mounted on the first mounting surface 224 of the heat sink 208. A mounting substrate (Submount, heat dissipating substrate, base) may also be interposed between the semiconductor laser device 1 and the heat sink 208. The semiconductor laser device 1 irradiates laser light in the direction of the normal to the first surface 214. The semiconductor laser device 1 is electrically connected to a first lead terminal 203 via a mandrel base 202.

The photodiode 209 is mounted to the first surface 214 of the mandrel base 202. The photodiode 209 is mounted on the first surface 214 in a region facing the heat sink 208 via the center portion of the mandrel base 202.

More specifically, the photodiode 209 is mounted in a Recess (process) portion 225 formed in the first surface 214. The recess portion 225 has a second mounting surface 226 formed at the bottom. The photodiode 209 is mounted on the second mounting surface 226. The photodiode 209 is electrically connected to the first lead terminal 203 via the mandrel base 202.

The first conductive line 210 corresponds to the conductive line 34 described above. The first wire 210 electrically connects the semiconductor laser device 1 and the second lead terminal 204. More specifically, the first lead wire 210 is electrically connected to the external connection region 90 of the semiconductor laser device 1 and the lead portion 220 of the second lead terminal 204. Thereby, the semiconductor laser device 1 is electrically connected to the second lead terminal 204 via the first wire 210.

Thus, semiconductor laser device 1 is mounted on mandrel base 202 such that the cathode is electrically connected to first lead terminal 203 and the anode is electrically connected to second lead terminal 204.

The second conductive line 211 may be a bonding wire. The second wire 211 electrically connects the photodiode 209 and the third lead terminal 205. More specifically, the second wire 211 is connected to the lead portion 222 of the third lead terminal 205. Thereby, the photodiode 209 is electrically connected to the third lead terminal 205 via the second wire 211.

A photodiode 209 is mounted on the mandrel base 202 such that a cathode is electrically connected to the third lead terminal 205 and an anode is electrically connected to the first lead terminal 203. Thereby, the anode of the photodiode 209 is electrically connected to the cathode of the semiconductor laser device 1 via the plug base 202.

The cover 212 includes a metal (e.g., iron) cylindrical member. The cap 212 is mounted on a first face 214 of the mandrel base 202. The cap 212 accommodates the heat sink 208, the semiconductor laser device 1, the photodiode 209, the lead-out portion 220 of the second lead terminal 204, the lead-out portion 222 of the third lead terminal 205, the first wire 210, and the second wire 211.

The cover 212 includes opposing walls 227, side walls 228, and a flange 229. The opposing wall 227 is formed in a plate shape (in this embodiment, a disc shape). The opposing wall 227 is opposite the first face 214 of the mandrel base 202. The side wall 228 is formed in a cylindrical shape (cylindrical shape in this embodiment), and is connected to a peripheral edge of the opposing wall 227. The side wall 228 demarcates an opening 230 on the opposite side from the opposing wall 227.

The flange 229 protrudes at the opening end of the opening 230 to the side opposite to the opening 230. The flange 229 is formed in a ring shape (circular ring shape in this embodiment) along the opening end of the opening 230. The cap 212 is fixed to the mandrel base 202 by being attached to the first surface 214 via a flange 229.

A light extraction window 231 is formed in the cover 212. The light extraction window 231 is formed in the opposing wall 227. The light extraction window 231 guides the laser light generated by the semiconductor laser device 1 from inside the cover 212 to outside the cover 212.

The sealing member 213 is a member for sealing the light extraction window 231. The closing member 213 is preferably formed of a translucent insulator or a transparent insulator. The closing member 213 is formed of glass in this manner. The closing member 213 may also be a lens for providing directivity of the laser light. In this embodiment, the closing member 213 closes the light extraction window 231 from the inside of the cover 212. The closing member 213 may close the light extraction window 231 from the outside of the cover 212.

In this embodiment, an example in which the package 201 includes the photodiode 209 is described. However, the package 201 without the photodiode 209 may be employed. In this case, the third lead terminal 205 may be removed and may be left as an open terminal.

Fig. 14 is a plan view showing a package 301 of the second embodiment. Fig. 15 is a sectional view taken along the line XV-XV shown in fig. 14. In fig. 14, the package body 302 is seen through for clarity of the internal structure.

Hereinafter, an example in which the semiconductor laser device 1 is mounted on the package 301 will be described. However, instead of the semiconductor laser device 1, the semiconductor laser device 101 or the semiconductor laser device 111 may be mounted on the package 301.

Referring to fig. 14 and 15, a package 301 is a semiconductor package in which the semiconductor laser device 1 is sealed with a sealing resin. The package 301 includes the semiconductor laser device 1, a package body 302, a terminal electrode 303, and a wire 304. In fig. 14, the wiring electrode 88 and the terminal electrode 303 of the semiconductor laser device 1 are indicated by hatching.

The package body 302 includes a transparent resin or a translucent resin. The package body 302 may include an epoxy resin as an example of a transparent resin or a translucent resin. The package body 302 is formed in a rectangular parallelepiped shape.

The package body 302 includes a first surface 305 on one side, a second surface 306 on the other side, and a plurality of side surfaces 307A, 307B, 307C, 307D connecting the first surface 305 and the second surface 306. The plurality of side surfaces 307A to 307D more specifically include a first side surface 307A, a second side surface 307B, a third side surface 307C, and a fourth side surface 307D.

The first surface 305 and the second surface 306 are formed in a quadrilateral shape (rectangular shape in this embodiment) in a plan view seen from the normal direction Z thereof. The plurality of side surfaces 307A to 307D extend in a plane along the normal direction Z.

The first side surface 307A and the second side surface 307B extend along the first direction X and are opposite in the second direction Y. First side 307A and second side 307B form the long sides of package body 302. The third side 307C and the fourth side 307D extend along the second direction Y and are opposite in the first direction X. The third side 307C and the fourth side 307D form short sides of the package body 302.

The terminal electrode 303 is disposed in the package body 302. In this embodiment, the terminal electrode 303 is disposed in a region on the fourth side surface 307D side in the package body 302. The terminal electrode 303 may contain a metal such as Fe, Cu, Ni, or Al.

A plating layer may be formed on the outer surface of the terminal electrode 303. The plating layer may have a single-layer structure including a single plating layer. The plating layer may have a laminated structure including a plurality of plating layers. The plating layer may contain at least 1 metal among Ti, TiN, Ni, Ag, Pd, Au, and Sn.

The terminal electrode 303 in this manner integrally includes a terminal main body 308 and a plurality of extending portions 309A, 309B, 309C. The plurality of extensions 309A to 309C more specifically include a first extension 309A, a second extension 309B, and a third extension 309C.

The terminal body 308 is formed in the package body 302 at intervals from the side surfaces 307A to 307D. The terminal body 308 is formed in a rectangular parallelepiped shape. The terminal main body 308 includes a first terminal surface 310 on the first surface 305 side, a second terminal surface 311 on the second surface 306 side, and a plurality of terminal side surfaces 312A, 312B, 312C, 312D connecting the first terminal surface 310 and the second terminal surface 311. More specifically, the plurality of terminal side surfaces 312A to 312D include a first terminal side surface 312A, a second terminal side surface 312B, a third terminal side surface 312C, and a fourth terminal side surface 312D.

The first terminal surface 310 and the second terminal surface 311 are formed in a quadrilateral shape in plan view (in this embodiment, a rectangle extending along the second direction Y). The second terminal surface 311 is exposed from the second surface 306 of the package body 302. The second terminal surface 311 is formed as an external terminal for external connection to an object to be connected. The second terminal face 311 may be formed on the same plane with respect to the second face 306.

The plurality of terminal side surfaces 312A to 312D extend planarly along the normal direction Z. The first terminal side 312A is opposite the first side 307A of the package body 302. Second terminal side 312B is opposite second side 307B of package body 302. The third terminal side 312C is opposite to the third side 307C of the package body 302. The fourth terminal side 312D is opposite to the fourth side 307D of the package body 302.

The terminal side surface 312A and the second terminal side surface 312B extend along the first direction X and are opposed in the second direction Y. The terminal side surface 312A and the second terminal side surface 312B form short sides of the terminal body 308. The third and fourth terminal sides 312C and 312D extend along the second direction Y and are opposite in the first direction X. Third terminal side surface 312C and fourth terminal side surface 312D form the long sides of terminal body 308.

The first extension 309A is drawn out in a band shape from the first terminal side surface 312A toward the first side surface 307A. The first extension 309A has a first exposed portion 313A exposed from the first side surface 307A. The first exposed portion 313A may be formed on the same plane with respect to the first side surface 307A.

The second extension 309B is drawn out in a band shape from the second terminal side surface 312B toward the second side surface 307B. The second extension 309B has a second exposed portion 313B exposed from the second side surface 307B. The second extension 309B may be formed at the same plane with respect to the second side surface 307B.

The third extension 309C is drawn out in a band shape from the third terminal side surface 312C to the fourth side surface 307D. The third extension 309C has a third exposed portion 313C exposed from the fourth side surface 307D. The third extension 309C may be formed in the same plane with respect to the fourth side 307D.

The plurality of extending portions 309A to 309C form a part of the first terminal surface 310, respectively. In this embodiment, the plurality of extending portions 309A to 309C are formed at intervals from the second terminal surface 311 toward the first terminal surface 310 side in the terminal side surfaces 312A to 312D.

Thus, the step portions 314 are defined between the plurality of extending portions 309A to 309C and the corresponding terminal side surfaces 312A to 312D. The step portion 314 is formed in a curved shape toward the terminal body 308. A portion of the package body 302 enters the step portion 314. This suppresses the terminal electrode 303 from falling off the package body 302.

The semiconductor laser device 1 is disposed in the package body 302 with a space from the terminal electrode 303 to the third side surface 307C side. The semiconductor laser device 1 is disposed in the package body 302 in a posture in which the first substrate main surface 3 of the substrate 2 faces the first surface 305 of the package body 302.

The long sides (the first substrate side 5A and the second substrate side 5B) of the substrate 2 are opposed to the first side 307A and the second side 307B of the package body 302. The short sides (the third substrate side 5C and the fourth substrate side 5D) of the substrate 2 are opposed to the third side 307C and the fourth side 307D of the package body 302.

The semiconductor laser device 1 is arranged such that the light-emitting region 31 is located on a line connecting the center of the third side surface 307C and the center of the fourth side surface 307D in a plan view. Thereby, the semiconductor laser device 1 is biased toward the first side surface 307A in a plan view. When the semiconductor laser device 111 is mounted in place of the semiconductor laser device 1, the semiconductor laser device 111 may be sealed in the package body 302 without being biased. The laser light generated by the semiconductor laser device 1 is extracted from the third side surface 307C of the package body 302.

The electrode 97 of the semiconductor laser device 1 is exposed from the second surface 306 of the package body 302. The electrode 97 is formed as an external terminal for external connection to an object to be connected. The electrode 97 is formed on the same plane with respect to the second face 306 of the package body 302.

The plurality of conductive lines 304 correspond to the conductive lines 34A to 34C described above. The number of the conductive lines 304 is arbitrary and is not limited to a specific number. The plurality of leads 304 are electrically connected to the external connection region 90 (wiring electrode 88) of the semiconductor laser device 1 and the first terminal surface 310 of the terminal electrode 303, respectively, in the package body 302.

The plurality of wires 304 respectively include a first bonding portion 315, a second bonding portion 316, and a wire portion 317. The first bonding portion 315 is connected to the external connection region 90 (wiring electrode 88) of the semiconductor laser device 1. The second joint portion 316 is connected to the first terminal surface 310 of the terminal electrode 303. The lead portion 317 extends linearly from the first bonding portion 315 to the second bonding portion 316.

In this embodiment, an example in which the electrode 97 of the semiconductor laser device 1 is exposed from the second surface 306 of the package body 302 is described. However, the semiconductor laser device 1 may be disposed on a second terminal electrode that is exposed from the second surface 306 of the package body 302 and that forms an external terminal different from the terminal electrode 303. In this case, the electrode 97 of the semiconductor laser device 1 is electrically connected to the second terminal electrode.

Fig. 16 is a plan view showing a package 401 of the third embodiment. Fig. 17 is a bottom view of the package 401 shown in fig. 16. Fig. 18 is a sectional view taken along line XVIII-XVIII shown in fig. 17.

Hereinafter, an example in which the semiconductor laser device 1 is mounted on the package 401 will be described. However, the semiconductor laser device 101 or the semiconductor laser device 111 may be mounted on the package 401 instead of the semiconductor laser device 1.

Referring to fig. 16 to 18, a package 401 is a semiconductor package in which the semiconductor laser device 1 is housed in a case made of an insulating material. The package 401 includes a housing 402, the semiconductor laser device 1, a first wiring 403, and a second wiring 404. The enclosure 402 has an internal space 405 and a light extraction window 406. The semiconductor laser device 1 is housed in the internal space 405. The light of the semiconductor laser device 1 is extracted through the light extraction window 406.

The first wiring 403 is routed inside and outside the internal space 405. The first wiring 403 has a first end 407 located inside the internal space 405 and a second end 408 located outside the internal space 405. A first end portion 407 of the first wiring 403 is electrically connected to the wiring electrode 88 of the semiconductor laser device 1 in the internal space 405. The second end 408 of the first wire 403 is formed as an external terminal for external connection to a connection target.

The second wiring 404 is routed inside and outside the internal space 405. The second wiring 404 has a first end 409 located inside the internal space 405 and a second end 410 located outside the internal space 405. The first end 409 of the second wire 404 is electrically connected to the electrode 97 of the semiconductor laser device 1 in the internal space 405. The second end 410 of the second wire 404 is formed as an external terminal for external connection to a connection target. Hereinafter, a specific structure of the package 401 will be described.

The housing 402 is formed in a rectangular parallelepiped shape. The housing 402 is formed of an insulator in this embodiment. The housing 402 has a first main surface 411 on one side, a second main surface 412 on the other side, and a plurality of side surfaces 413A, 413B, 413C, and 413D connecting the first main surface 411 and the second main surface 412. The plurality of side surfaces 413A to 413D more specifically include a first side surface 413A, a second side surface 413B, a third side surface 413C, and a fourth side surface 413D.

The first main surface 411 and the second main surface 412 are formed in a square shape (rectangular shape in this embodiment) in a plan view seen along the normal direction Z thereof. The side surfaces 413A to 413D extend in a plane along the normal direction Z.

The first side 413A and the second side 413B extend along the first direction X and are opposite in the second direction Y. The first side 413A and the second side 413B form long sides of the enclosure 402. The third side 413C and the fourth side 413D extend along the second direction Y and are opposite in the first direction X. The third side 413C and the fourth side 413D form short sides of the enclosure 402.

An internal space 405 for housing the semiconductor laser device 1 is defined inside the housing 402. In this embodiment, the internal space 405 is divided into a square shape in a plan view. The planar shape of the internal space 405 is arbitrary and is not limited to a specific shape.

A first window 415 communicating with the internal space 405 is defined in the third side 413C. The first window 415 is formed as a light extraction window 406 for extracting light from the semiconductor laser device 1. The first window 415 is divided into a quadrangle in a front view of the third side 413C from the front. The first window 415 is divided into rectangles extending in the second direction Y in this manner. That is, the third side 413C is formed in a quadrilateral ring shape in front view (rectangular ring shape in this embodiment) due to the first window 415.

A second window 416 communicating with the internal space 405 is defined in the first main face 411. The semiconductor laser device 1 is accommodated in the internal space 405 through the second window 416. In this manner, the second window 416 is divided into a quadrangle in a top view.

That is, the first main surface 411 is formed in a quadrilateral ring shape (rectangular ring shape in this embodiment) in plan view by the second windows 416. The planar shape of the second window 416 is arbitrary and is not limited to a specific shape. The planar shape of the second window 416 does not necessarily need to coincide with (match) the planar shape of the internal space 405.

The package body 401 includes a first closing member 417 closing the first window 415 (the internal space 405). The first closing member 417 is formed of a plate-like member. The first sealing member 417 is preferably formed of a member that transmits light of the semiconductor laser device 1. The first closing member 417 is preferably made of a translucent insulator or a transparent insulator.

The first closing member 417 is attached to the third side 413C of the housing 402. The first closing member 417 is mounted to a first support portion 418 formed around the first window 415. In this embodiment, the first support portion 418 is defined by a groove formed in a surface layer portion of the third side face 413C so as to communicate with the first window 415. The first support portion 418 (groove) is divided into a quadrilateral ring shape (rectangular ring shape in this embodiment) surrounding the first window 415 in a plan view in this embodiment.

The first closing member 417 has a first plate face 419 on the third side 413C side and a second plate face 420 on the fourth side 413D side. The first plate 419 and the second plate 420 have flat surfaces parallel to the third side 413C. The first plate surface 419 may protrude sideward from the third side surface 413C. The first plate face 419 may be located on the fourth side 413D side with respect to the third side 413C. The first panel 419 may be located on the same plane as the third side 413C.

The second plate surface 420 is attached to the first support portion 418 in a region on the fourth side 413D side with respect to the third side 413C. The second plate surface 420 may be attached to the first support portion 418 using an adhesive. The bonding agent may comprise a resin (e.g., an infrared curable resin).

The package body 401 includes a second closing member 421 closing the second window 416 (the internal space 405). The second closing member 421 is constituted by a plate-like member. The material of the second sealing member 421 is not particularly limited, and preferably includes an insulator. The insulator may be an inorganic insulator or an organic insulator. The second closing member 421 may have a light-shielding property.

The second closing member 421 is attached to the first main surface 411 of the housing 402. The second closing member 421 is more specifically mounted on the second support portion 422 formed around the second window 416. In this embodiment, the second support portion 422 is defined by a concave groove formed in the surface layer portion of the first main surface 411 so that the second window 416 communicates with the concave groove. In this embodiment, the second support portion 422 (concave groove) is divided into a four-sided ring shape surrounding the second window 416 in a plan view.

The second closing member 421 has a first plate surface 423 on the first main surface 411 side and a second plate surface 424 on the second main surface 412 side. The first plate surface 423 and the second plate surface 424 have flat surfaces parallel to the first main surface 411. The first plate surface 423 may protrude above the first main surface 411. The first plate surface 423 may be located on the second main surface 412 side with respect to the first main surface 411. The first plate surface 423 may be located on the same plane as the first main surface 411.

Second plate surface 424 is attached to second support portion 422 in a region on the second main surface 412 side with respect to first main surface 411. The second plate surface 424 may be attached to the second support 422 using an adhesive. The bonding agent may also contain a resin (e.g., an infrared curable resin).

The enclosure 402 more specifically includes a base layer 431 and a frame layer 432. The first main surface 411 of the enclosure 402 is formed by a frame layer 432. The second main surface 412 of the housing 402 is formed of a base layer 431. The side surfaces 413A to 413D of the enclosure 402 are formed by a base layer 431 and a frame layer 432.

The base layer 431 is formed of a plate-like member in a rectangular parallelepiped shape. The base layer 431 includes a first face 433 on the first principal face 411 side, a second face 434 on the second principal face 412 side, and a plurality of side faces 435A, 435B, 435C, 435D connecting the first face 433 and the second face 434. More specifically, the plurality of side surfaces 435A to 435D includes a first side surface 435A, a second side surface 435B, a third side surface 435C, and a fourth side surface 435D.

The first face 433 forms a portion of the interior space 405. The second surface 434 forms the second main surface 412 of the enclosure 402. The side surfaces 435A to 435D form parts of side surfaces 413A to 413D of the enclosure 402, respectively.

The base layer 431 includes either or both of an inorganic insulator and an organic insulator. The base layer 431 may include at least 1 of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride as an example of an inorganic insulator.

The underlayer 431 may contain either one or both of a photosensitive resin and a thermosetting resin as an example of an organic insulator. The base layer 431 may include at least 1 of epoxy resin, polyimide resin, polybenzoxazole resin, acrylic resin, and silicone resin, which are examples of the organic insulator. In this embodiment, the base layer 431 is formed of a glass epoxy substrate in which glass fibers are impregnated with an epoxy resin.

The frame layer 432 is formed in a ring shape (a quadrangular ring shape in this embodiment) surrounding an inner region of the base layer 431 in a plan view, and defines an internal space 405 between itself and the first surface 433 of the base layer 431. The frame layer 432 includes a first face 443 on the first principal face 411 side, a second face 444 on the second principal face 412 side, a plurality of inner walls 445A, 445B, 445C, 445D connecting the first face 443 and the second face 444, and a plurality of outer walls 446A, 446B, 446C, 446D connecting the first face 443 and the second face 444.

The plurality of inner walls 445A to 445D more specifically include a first inner wall 445A, a second inner wall 445B, a third inner wall 445C, and a fourth inner wall 445D. Inner walls 445A-445D define interior space 405 between them and first surface 433 of base layer 431.

More specifically, the plurality of outer walls 446A to 446D include a first outer wall 446A, a second outer wall 446B, a third outer wall 446C, and a fourth outer wall 446D. The outer walls 446A to 446D form parts of side surfaces 413A to 413D of the enclosure 402, respectively.

The first window 415 and the first support portion 418 (groove) are formed in the frame layer 432 at a portion where the third side 413C of the enclosure 402 is formed. The second window 416 and the second support portion 422 (groove) are formed on the first surface 443 of the frame layer 432.

The frame layer 432 includes either or both of an inorganic insulator and an organic insulator. The frame layer 432 may include at least 1 of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride as an example of an inorganic insulator.

The frame layer 432 may include either one or both of a photosensitive resin and a thermosetting resin as an example of an organic insulator. The frame layer 432 may include at least 1 of epoxy resin, polyimide resin, polybenzoxazole resin, acrylic resin, and silicone resin, which are examples of the organic insulator. In this embodiment, the frame layer 432 is made of an epoxy resin molded by a mold.

The first wiring 403 is led out to the second main surface 412 from the internal space 405 through the housing 402. More specifically, the first wiring 403 passes through the inside of the base layer 431 from the first surface 433 of the base layer 431 and is drawn out to the second surface 434 of the base layer 431.

The first wire 403 includes a first connection portion 451, a first through portion 452, and a first external terminal portion 453. The first connection portion 451 forms the first end portion 407 of the first wiring 403. The first external terminal portion 453 forms the second end portion 408 of the first wire 403.

The first connection portion 451 is formed in the first surface 433 of the base layer 431 in a region on the fourth side surface 413D side of the enclosure 402. The first connection portion 451 is formed in a film shape. The first connection portion 451 is formed in a quadrangular shape in a plan view. The planar shape of the first connection portion 451 is arbitrary and is not limited to a specific shape. The first connection portion 451 may also include at least 1 kind of Cu, Ni, Ti, and Au.

The first through portion 452 penetrates the base layer 431 from the first surface 433 to the second surface 434, and is exposed from the first surface 433 and the second surface 434. The first through portion 452 overlaps with the first connection portion 451 in a plan view. The first through portion 452 is electrically connected to the first connection portion 451 at a portion exposed from the first surface 433 of the base layer 431.

The first through portion 452 is formed in a circular shape in a plan view. The planar shape of the first through portion 452 is arbitrary and is not limited to a specific shape. The first connection portion 451 may also include at least 1 kind of Cu, Ni, Ti, and Au.

The first external terminal portions 453 are formed in the second surface 434 of the base layer 431 in the region on the fourth side surface 413D side of the enclosure 402. The first external terminal portion 453 is formed in a film shape. The first external terminal portion 453 covers the first through portion 452. The first external terminal portion 453 is electrically connected to the first through portion 452.

The first external terminal portion 453 is formed in a square shape in a plan view. The planar shape of the first external terminal portion 453 is arbitrary and is not limited to a specific shape. The first external terminal portion 453 may include at least 1 kind among Cu, Ni, Ti, and Au.

The second wiring 404 penetrates the housing 402 from the internal space 405 and is drawn out to the second main surface 412. More specifically, the second wire 404 passes through the inside of the base layer 431 from the first surface 433 of the base layer 431 and is drawn out to the second surface 434 of the base layer 431.

The second wiring 404 includes a second connection portion 461, a plurality of second through portions 462, and a second external terminal portion 463. The second connection portion 461 forms the first end portion 409 of the second wire 404. The second external terminal portion 463 forms a second terminal portion 410 of the second wiring 404.

The second connection portion 461 is formed in the first surface 433 of the base layer 431 in a region on the third side surface 413C side of the housing 402 at an interval from the first connection portion 451. The second connection portion 461 is formed in a film shape. The second connection portion 461 is formed in a quadrangular shape in a plan view. The planar shape of the second connection part 461 is arbitrary and is not limited to a specific shape. The second connection part 461 may also include at least 1 kind among Cu, Ni, Ti, and Au.

The second through holes 462 penetrate the base layer 431 from the first surface 433 to the second surface 434, and are exposed from the first surface 433 and the second surface 434. In this embodiment, the second through holes 462 are formed at intervals along the first direction X. The number and arrangement of the second through holes 462 are arbitrary and are not limited to a specific number and arrangement.

The second through portions 462 overlap with the second connection portions 461 in a plan view. The second through holes 462 are electrically connected to the second connection portions 461 at the portions exposed from the second surface 434 of the base layer 431.

The second through portion 462 is formed in a circular shape in a plan view. The planar shape of the second through hole 462 is arbitrary and is not limited to a specific shape. The second connection part 461 may also include at least 1 kind among Cu, Ni, Ti, and Au.

The second external terminal portion 463 is formed in a region on the third side 413C side of the enclosure 402 on the second surface 434 of the base layer 431 with a space from the first external terminal portion 453. The second external terminal portion 463 is formed in a film shape. The second external terminal portion 463 covers the plurality of second through portions 462. The second external terminal portion 463 is electrically connected to the second through portions 462.

The second external terminal portion 463 is formed in a quadrangular shape in plan view. The planar shape of the second external terminal portion 463 is arbitrary and is not limited to a specific shape. The second external terminal portion 463 may also include at least 1 of Cu, Ni, Ti, and Au.

The package 401 further includes a mounting substrate (submount, heat sink, submount) 471 in this manner. The mounting substrate 471 is formed of a plate-like member formed in a rectangular parallelepiped shape. The mounting substrate 471 includes a first face 472 on the first principal face 411 side, a second face 473 on the second principal face 412 side, and a side face 474 connecting the first face 472 and the second face 473. The second surface 473 of the mounting substrate 471 is connected to the second connection portion 461 of the second wire 404. The mounting substrate 471 may also contain at least 1 material among Si, GaN, SiC, and AlN.

The mounting substrate 471 includes 1 or more through wirings 475. The through wiring 475 penetrates the mounting substrate 471 from the first surface 472 to the second surface 473, and is exposed from the first surface 472 and the second surface 473. The through wiring 475 is electrically connected to the second connection portion 461 of the second wiring 404 on the second surface 473.

The through-wiring 475 is formed in a circular shape in a plan view. The planar shape of the through wiring 475 is arbitrary and is not limited to a specific shape. The through wiring 475 may include at least 1 kind of Cu, Ni, Ti, and Au.

The semiconductor laser device 1 is disposed on the first surface 472 of the mounting substrate 471 in a posture in which the first substrate main surface 3 of the substrate 2 faces the first main surface 411 of the enclosure 402. The long sides (the first substrate side 5A and the second substrate side 5B) of the substrate 2 are opposed to the first side 413A and the second side 413B of the enclosure 402. The short sides (the third substrate side 5C and the fourth substrate side 5D) of the substrate 2 are opposed to the third side 413C and the fourth side 413D of the enclosure 402.

The electrode 97 of the semiconductor laser device 1 is electrically connected to the through wiring 475 of the mounting substrate 471. Thereby, the semiconductor laser device 1 is electrically connected to the second wiring 404 via the through wiring 475. The electrode 97 may be connected to the through wiring 475 via a conductive bonding material. The conductive bonding material may be a metal paste or a solder.

The light extraction surface of the semiconductor laser device 1 (in this embodiment, the third substrate side surface 5C (first end surface 56)) protrudes from the mounting substrate 471 toward the third side surface 413C of the housing 402 in plan view. The first substrate main surface 3 of the substrate 2 faces the first surface 433 of the base layer 431 in the normal direction Z.

According to this configuration, the laser light of the semiconductor laser device 1 is taken out from the region outside the mounting substrate 471. Therefore, disturbance (reflection, absorption, or the like of light) of the laser light by the mounting substrate 471 can be suppressed. Of course, the entire area of the semiconductor laser device 1 may be located on the mounting substrate 471.

In the semiconductor laser device 1, the light-emitting region 31 is arranged on a line connecting the center of the third side face 413C and the center of the fourth side face 413D in a plan view. Thus, the semiconductor laser device 1 is biased toward the first side face 413A in plan view. When the semiconductor laser device 111 is mounted in place of the semiconductor laser device 1, the semiconductor laser device 111 may be disposed inside the housing 402 without being biased.

The package 401 further includes 1 or more (3 in this manner) leads 480. The plurality of conductive lines 480 correspond to the conductive lines 34A to 34C. The number of the wires 480 is arbitrary, and is not limited to a specific number. The plurality of wires 480 are electrically connected to the external connection region 90 (wiring electrode 88) of the semiconductor laser device 1 and the first connection portion 451 of the first wiring 403, respectively.

The plurality of wires 480 more specifically include a first bonding portion 481, a second bonding portion 482, and a wire portion 483, respectively. The first junction 481 is connected to the external connection region 90 (wiring electrode 88) of the semiconductor laser device 1. The second joint portion 482 is connected to the first connection portion 451 of the first wiring 403. The lead portion 483 extends linearly from the first joint 481 to the second joint 482. Thereby, the semiconductor laser device 1 is electrically connected to the first wiring 403 via the lead 480.

While the embodiments of the present invention have been described above, the present invention can be implemented in other embodiments.

In the above-described embodiment, the description has been made on the example in which the semiconductor layer 6 includes 3 light emitting cell layers 13 and 2 tunnel junction layers 14. However, the number of the light emitting cell layers 13 is arbitrary and is not limited to 3. It is also possible to form 1, 2 or 3, or more than 3 light emitting unit layers 13. The number of tunnel junction layers 14 is adjustable according to the number of light emitting cell layers 13, and is not limited to 2.

In the above embodiment, a structure in which the conductivity type of each semiconductor portion is inverted may be employed. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

This application corresponds to application No. 2019-042890, filed on 8.3.2019 to the sunward franchise, the entire disclosure of which is hereby incorporated by reference. The embodiments of the present invention have been described in detail, but these descriptions are merely specific examples used for clarifying the technical content of the present invention, and the present invention should not be construed as limited to these specific examples, and the scope of the present invention is defined only by the scope of the appended claims.

1 semiconductor laser device

6 semiconductor layer

10 n-type buffer layer

11 light emitting layer

12p type contact layer

13 light emitting unit layer

13A first light emitting unit layer

13B second light emitting cell layer

13C third light emitting cell layer

14 tunnel bonding layer

14A first Tunnel junction layer

14B second Tunnel bonding layer

31 light emitting region

32 pad area

34 conducting wire

34A lead wire

34B lead

34C conducting wire

51 mesa structure

52 top of the container

53 base

54 first side wall

55 second side wall

Mesa structure of 61 bonding pad

62 bond pad top

63 pad base

64 pad sidewall

88 wiring electrode

89 internal connection zone

90 outer connection region

101 semiconductor laser device

111 semiconductor laser device

201 package (semiconductor core rod) 301 package (semiconductor package)

401 package (semiconductor package) W1 first width

W2 second width

W3 third Width

WC connection width.