阅读说明：本技术 Fmcw调频源信号产生模块及延时控制方法 (FMCW frequency modulation source signal generation module and time delay control method ) 是由 张传胜 龚高茂 邓姣 赵海军 于 2019-10-30 设计创作，主要内容包括：本发明公开了一种FMCW调频源信号产生模块及延时控制方法,所述模块包括软核处理器Microblaze模块、DDR接口模块、DDR模块、AXI内部连接模块和两路调频源信号生成通道；DDR模块的输入输出端与DDR接口模块的输入输出端连接,DDR接口模块的输入输出端与AXI内部连接模块的输入输出端连接,AXI内部连接模块的输入输出端与软核处理器Microblaze模块的输入输出端连接。本发明实现了多档可调调频连续波信号调节和延时控制,可满足不同条件激光雷达测距的精度要求。(The invention discloses an FMCW frequency modulation source signal generation module and a time delay control method, wherein the module comprises a soft core processor Microblaze module, a DDR interface module, a DDR module, an AXI internal connection module and two paths of frequency modulation source signal generation channels; the input and output ends of the DDR module are connected with the input and output end of the DDR interface module, the input and output end of the DDR interface module is connected with the input and output end of the AXI internal connection module, and the input and output end of the AXI internal connection module is connected with the input and output end of the Microblaze module of the soft-core processor. The invention realizes the multi-gear adjustable frequency modulation continuous wave signal adjustment and time delay control, and can meet the precision requirements of laser radar ranging under different conditions.)

1. An FMCW modulated frequency source signal generation module comprising:

the system comprises a soft core processor Microblaze module, a DDR interface module, a DDR module, an AXI internal connection module and two channels of frequency modulation source signal generation channels;

the input and output ends of the DDR module are connected with the input and output ends of the DDR interface module, the input and output ends of the DDR interface module are connected with the input and output ends of an AXI internal connection module, and the input and output ends of the AXI internal connection module are connected with the input and output ends of a soft core processor Microblaze module;

the first frequency modulation source signal generation channel comprises a first DMA reading module, a first FIFO module, a first serial-to-parallel conversion and data sequence modulation module, a plurality of first output serializer OSERDES modules and a first DAC module; the input and output ends of the first DMA reading module are connected with the input and output ends of the AXI internal connection module, the output end of the first DMA reading module is connected with the input end of the first FIFO module, the output end of the first FIFO module is connected with the input end of the first serial-to-parallel conversion and data sequence regulation module, the output end of the first serial-to-parallel conversion and data sequence regulation module is respectively connected with the input ends of a plurality of first output serializer OSERDES modules, and the output end of each first output serializer OSERDES module is connected with the input end of the first DAC module;

the second frequency modulation source signal generation channel comprises a second DMA reading module, a second FIFO module, a data delay processing module, a second serial-parallel conversion and data sequence modulation module, a plurality of second output serializer OSERDES modules and a second DAC module; the input and output ends of the second DMA reading module are connected with the input and output ends of the AXI internal connection module, the output end of the second DMA reading module is connected with the input end of the second FIFO module, the output end of the second FIFO module is connected with the input end of the data delay processing module, the output end of the data delay processing module is connected with the input end of the second serial-parallel conversion and data sequence adjusting module, the output ends of the second serial-parallel conversion and data sequence adjusting module are respectively connected with the input ends of the plurality of second output serializer OSERDES modules, and the output end of each second output serializer OSERDES module is connected with the input end of the second DAC module.

2. An FMCW FM source signal generation module as claimed in claim 1, wherein said first DAC block is a 12-bit or higher digital-to-analog converter.

3. An FMCW FM source signal generation module as claimed in claim 1, wherein said second DAC block is a 12-bit or higher digital-to-analog converter.

4. An FMCW frequency modulation source signal generation module as claimed in any one of claims 1 to 3, comprising a serial control interface module, wherein the serial control interface module is connected to the data delay processing module, and the serial module may be RS422 or other type of serial port.

5. The FMCW modulated frequency source signal generation module of claim 1, wherein the first FIFO module is configured to perform bit width conversion and clock domain crossing processing on the data read by the first DMA read module; and the second FIFO module is used for performing bit width conversion and clock domain crossing processing on the data read by the second DMA reading module.

6. The FMCW modulated frequency source signal generating module of claim 1, wherein the first deserializer and data permuter module is configured to intercept 12 bits or more of the sample data processed by the first FIFO module, and the second deserializer and data permuter module is configured to intercept 12 bits or more of the sample data processed by the second FIFO module.

7. A delay control method based on the FMCW fm source signal generating module as described above, characterized in that a data delay processing module is added to the channel 2, and includes the following steps:

s1, before the frequency modulation signal is started to be generated, the number of delayed cycles is calculated according to the delay time, and for the integral multiple N delay, the N cycles are directly delayed for output; for non-integral multiple delay, processing data to reach integral multiple delay, and directly delaying integral cycle output;

s2, when receiving the frequency modulation signal, the channel 1 and the channel 2 respectively read the needed waveform signal from the DDR to the FIFO;

s3, starting data transmission of channel 1, then starting data transmission of channel 2 according to the number of delay cycles, and the data delay processing can only be one of N half cycles and N cycles, where N half cycles correspond to non-integer cycle delay and N cycles correspond to integer cycle delay.

8. The method of claim 7, wherein in step S1, for the lowest resolution of the delay control, the data processing is shifted by a half cycle on the basis of the delay of an integer cycle.

Technical Field

The invention relates to the technical field of laser radars, in particular to an FMCW frequency modulation source signal generation module and a time delay control method.

Background

Frequency Modulated Continuous Wave (FMCW) radar is a radar system that obtains range and speed information by frequency modulating a continuous wave, which may be modulated in a variety of ways, such as linear modulation and sinusoidal modulation. The Linear Frequency Modulation Continuous Wave (LFMCW) radar has the advantages of high distance resolution, low transmitting power, high receiving sensitivity, simple structure and the like, does not have a ranging blind area, and has the characteristics of better anti-stealth, anti-background clutter and anti-interference capability compared with a pulse radar. The prior art adopts fixed signal frequency, can not accord with different distances and high accuracy range finding requirement.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides an FMCW frequency modulation source signal generation module and a time delay control method, so that frequency modulation continuous wave signal adjustment and time delay control are realized, and the precision requirements of laser radar ranging under different conditions can be met.

The purpose of the invention is realized by the following technical scheme:

an FMCW modulated frequency source signal generation module comprising:

the system comprises a soft core processor Microblaze module, a DDR interface module, a DDR module, an AXI internal connection module and two channels of frequency modulation source signal generation channels; the input and output ends of the DDR module are connected with the input and output ends of the DDR interface module, the input and output ends of the DDR interface module are connected with the input and output ends of an AXI internal connection module, and the input and output ends of the AXI internal connection module are connected with the input and output ends of a soft core processor Microblaze module;

the first frequency modulation source signal generation channel comprises a first DMA reading module, a first FIFO module, a first serial-to-parallel conversion and data sequence modulation module, a plurality of first output serializer OSERDES modules and a first DAC module; the input and output ends of the first DMA reading module are connected with the input and output ends of the AXI internal connection module, the output end of the first DMA reading module is connected with the input end of the first FIFO module, the output end of the first FIFO module is connected with the input end of the first serial-to-parallel conversion and data sequence regulation module, the output end of the first serial-to-parallel conversion and data sequence regulation module is respectively connected with the input ends of a plurality of first output serializer OSERDES modules, and the output end of each first output serializer OSERDES module is connected with the input end of the first DAC module;

the second frequency modulation source signal generation channel comprises a second DMA reading module, a second FIFO module, a data delay processing module, a second serial-parallel conversion and data sequence modulation module, a plurality of second output serializer OSERDES modules and a second DAC module; the input and output ends of the second DMA reading module are connected with the input and output ends of the AXI internal connection module, the output end of the second DMA reading module is connected with the input end of the second FIFO module, the output end of the second FIFO module is connected with the input end of the data delay processing module, the output end of the data delay processing module is connected with the input end of the second serial-parallel conversion and data sequence adjusting module, the output ends of the second serial-parallel conversion and data sequence adjusting module are respectively connected with the input ends of the plurality of second output serializer OSERDES modules, and the output end of each second output serializer OSERDES module is connected with the input end of the second DAC module.

Further, the first DAC module is a 12-bit or higher digital-to-analog converter.

Further, the second DAC module is a 12-bit or higher digital-to-analog converter.

And further, the device comprises a serial port control interface module, and the serial port control interface module is connected with the data delay processing module.

Further, the first FIFO module is configured to perform bit width conversion and clock domain crossing processing on the data read by the first DMA read module; and the second FIFO module is used for performing bit width conversion and clock domain crossing processing on the data read by the second DMA reading module.

Furthermore, the first serial-parallel conversion and data sequence-adjusting module is used for intercepting the sample data processed by the first FIFO module with the higher bits by 12 or more, and the second serial-parallel conversion and data sequence-adjusting module is used for intercepting the sample data processed by the second FIFO module with the higher bits by 12 or more.

A delay control method based on the FMCW fm source signal generating module as described above, based on adding a data delay processing module at the channel 2, comprising the following steps:

s1, before the frequency modulation signal is started to be generated, the number of delayed cycles is calculated according to the delay time, and for the integral multiple N delay, the N cycles are directly delayed for output; for non-integral multiple delay, processing data to reach integral multiple delay, and directly delaying integral cycle output;

s2, when receiving the frequency modulation signal, the channel 1 and the channel 2 respectively read the needed waveform signal from the DDR to the FIFO;

s3, starting data transmission of channel 1, then starting data transmission of channel 2 according to the number of delay cycles, and the data delay processing can only be one of N half cycles and N cycles, where N half cycles correspond to non-integer cycle delay and N cycles correspond to integer cycle delay.

Further, for the lowest resolution of the delay control, the data processing is delayed by an integer period and then staggered by a half period.

The invention has the beneficial effects that:

(1) the invention realizes the multi-gear adjustable frequency modulation continuous wave signal adjustment and time delay control, and can meet the precision requirement of laser radar ranging under different conditions.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of the FMCW laser detection principle of the present invention.

FIG. 2 is a schematic diagram of the FMCW laser detection signal conversion process of the present invention.

Fig. 3 is a schematic diagram illustrating the principle of the modulation distance measurement and velocity measurement of the present invention.

FIG. 4 is a schematic diagram of the difference frequency without velocity according to the present invention.

Fig. 5 is a block diagram of a signal receiving and processing system according to the present invention.

Fig. 6 is a block diagram of a system for generating a frequency modulated source according to the present invention.

Fig. 7 is a flow chart of the chirp generation process of the present invention.

Detailed Description

The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following. All of the features disclosed in this specification, or all of the steps of a method or process so disclosed, may be combined in any combination, except combinations where mutually exclusive features and/or steps are used.

Any feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.

Specific embodiments of the present invention will be described in detail below, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known circuits, software, or methods have not been described in detail so as not to obscure the present invention.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Before describing the embodiments, some necessary terms need to be explained. For example:

if the terms "first," "second," etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a "first" element discussed below could also be termed a "second" element without departing from the teachings of the present invention. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

The various terms appearing in this application are used for the purpose of describing particular embodiments only and are not intended as limitations of the invention, with the singular being intended to include the plural unless the context clearly dictates otherwise.

When the terms "comprises" and/or "comprising" are used in this specification, these terms are intended to specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence and/or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As shown in fig. 1 to 7, an FMCW fm source signal generating module includes:

the system comprises a soft core processor Microblaze module, a DDR interface module, a DDR module, an AXI internal connection module and two channels of frequency modulation source signal generation channels;

the input and output ends of the DDR module are connected with the input and output ends of the DDR interface module, the input and output ends of the DDR interface module are connected with the input and output ends of an AXI internal connection module, and the input and output ends of the AXI internal connection module are connected with the input and output ends of a soft core processor Microblaze module;

the first frequency modulation source signal generation channel comprises a first DMA reading module, a first FIFO module, a first serial-to-parallel conversion and data sequence modulation module, a plurality of first output serializer OSERDES modules and a first DAC module; the input and output ends of the first DMA reading module are connected with the input and output ends of the AXI internal connection module, the output end of the first DMA reading module is connected with the input end of the first FIFO module, the output end of the first FIFO module is connected with the input end of the first serial-to-parallel conversion and data sequence regulation module, the output end of the first serial-to-parallel conversion and data sequence regulation module is respectively connected with the input ends of a plurality of first output serializer OSERDES modules, and the output end of each first output serializer OSERDES module is connected with the input end of the first DAC module;

the second frequency modulation source signal generation channel comprises a second DMA reading module, a second FIFO module, a data delay processing module, a second serial-parallel conversion and data sequence modulation module, a plurality of second output serializer OSERDES modules and a second DAC module; the input and output ends of the second DMA reading module are connected with the input and output ends of the AXI internal connection module, the output end of the second DMA reading module is connected with the input end of the second FIFO module, the output end of the second FIFO module is connected with the input end of the data delay processing module, the output end of the data delay processing module is connected with the input end of the second serial-parallel conversion and data sequence adjusting module, the output ends of the second serial-parallel conversion and data sequence adjusting module are respectively connected with the input ends of the plurality of second output serializer OSERDES modules, and the output end of each second output serializer OSERDES module is connected with the input end of the second DAC module.

Further, the first DAC module is a 12-bit or higher digital-to-analog converter.

Further, the second DAC module is a 12-bit or higher digital-to-analog converter.

And further, the device comprises a serial port control interface module, and the serial port control interface module is connected with the data delay processing module.

Further, the first FIFO module is configured to perform bit width conversion and clock domain crossing processing on the data read by the first DMA read module; and the second FIFO module is used for performing bit width conversion and clock domain crossing processing on the data read by the second DMA reading module.

Furthermore, the first serial-parallel conversion and data sequence-adjusting module is used for intercepting the sample data processed by the first FIFO module with the higher bits by 12 or more, and the second serial-parallel conversion and data sequence-adjusting module is used for intercepting the sample data processed by the second FIFO module with the higher bits by 12 or more.

A delay control method based on the FMCW fm source signal generating module as described above, based on adding a data delay processing module at the channel 2, comprising the following steps:

s1, before the frequency modulation signal is started to be generated, the number of delayed cycles is calculated according to the delay time, and for the integral multiple N delay, the N cycles are directly delayed for output; for non-integral multiple delay, processing data to reach integral multiple delay, and directly delaying integral cycle output;

s2, when receiving the frequency modulation signal, the channel 1 and the channel 2 respectively read the needed waveform signal from the DDR to the FIFO;

s3, starting data transmission of channel 1, then starting data transmission of channel 2 according to the number of delay cycles, and the data delay processing can only be one of N half cycles and N cycles, where N half cycles correspond to non-integer cycle delay and N cycles correspond to integer cycle delay.

Further, for the lowest resolution of the delay control, the data processing is delayed by an integer period and then staggered by a half period.

In an embodiment of the present invention, the system uses a tunable frequency modulated continuous wave, for example, the frequency modulated continuous wave laser detection philosophy is shown in fig. 1. The local emission source DDS1 emits triangular frequency modulation continuous waves, the triangular frequency modulation continuous waves are amplified and frequency-doubled and then emitted by the laser part, the signals are reflected back when meeting obstacles, and are received by the laser receiving part and mixed with the local replica signal DDS2 to generate difference frequency signals, and the difference frequency signals contain the distance and speed information of a target. The difference frequency is amplified, A/D is carried out on the difference frequency, then digital signal processing is carried out, a target is captured and tracked, and information such as target distance, speed and the like is solved.

The FMCW laser detection system determines information such as a target distance, a target speed, and the like by frequency measurement of an intermediate frequency signal obtained by mixing a transmitted and received laser frequency modulation signal, and thus, the FMCW laser detection system goes through four processes from generation of a modulation signal to acquisition of the intermediate frequency signal, i.e., laser intensity modulation, laser spatial transmission and target scattering, and reception and mixing by a photodetector, as shown in fig. 2.

The frequency modulation continuous wave can have various waveforms, and the scheme adopts an improved triangular waveform and is divided into three sections: frequency rise, frequency fall, frequency invariance. The temporal variation of the instantaneous frequencies of the transmitted signal and the target echo signal is shown in fig. 3. In order to prevent the fbd frequency difference from exceeding the processing range too much, a frequency invariant segment is used.

The round trip transit time of the light and the target speed are such that there is a certain frequency difference between the two. And setting the signal scanning bandwidth as B, the repetition period as T, the distance R and the target echo signal delay as tau.

In the case of a stationary target:

obtaining:

c light speed 3X 10⁸m/s

Target present speed case:

f_bu＝f_b-f_v

f_bd＝f_b+f_v

f₀: center frequency point

Combining the above formula, we can get:

according to the formula, to obtain the speed and distance information, the system digital signal processing is to solve f_vHeel f_bu。

1. Ranging resolution

Distance calculation formula:

derivation of the formula yields:

as can be seen, the range resolution is determined by the frequency resolution of the frequency domain processing of the echo signal. When the signal in one period time is subjected to spectrum analysis, the minimum frequency interval capable of being distinguished is minimum 1/T, because f_bThe observation period is T/3, i.e. Δ f_bMinimum value of Δ f_bSubstituting the formula for 3/T to obtain:

from the above formula, the detection range resolution is only related to the bandwidth B of the fm signal, and is not related to other factors.

The bandwidth designed by the scheme is 450MHz, namely the distance resolution is

(one) System index calculation

The following technical indexes are used as examples to explain the calculation process of system parameters

The system scans the bandwidth: b ═ 2 GHz.

Signal repetition frequency: 1 kHz-500 kHz.

The requirement of the range measurement is as follows: less than or equal to 10 Km.

The requirement of speed measurement range: is less than or equal to 3400 m/s.

Systematic frequency difference calculation

From the distance calculation formula

Then, the maximum frequency difference is generated by substituting the 1KHz repetition frequency and the 10Km distance into the formula:

frequency difference generated by speed:

assuming that the laser wavelength is 1500nm, substituting the formula to obtain:

the velocity doppler is down-converted to control the range within 200MHz for signal sampling processing.

The software is divided into a transmitting part and a receiving part, the transmitting part and the receiving part are completely separated on the hardware, and the FPGA is used for data processing, so that the software is divided into two parts to be designed respectively.

The FPGA software realizes the block diagram, and the software part mainly comprises two parts of echo signal receiving, processing and frequency modulation source signal transmitting. The receiving part realizes the main functions of signal acquisition and DDR storage, signal capture, signal tracking and real-time output of sampled signals. The transmitting part mainly realizes the generation of two-channel frequency modulation source signals and the time delay control of two channels.

Fig. 5 is a software block diagram of echo signal receiving processing, and fig. 6 is a software block diagram of frequency modulation source signal generation. The FPGA chips all adopt xilinx K7 series chips. Microblaze in the figure is a processor (soft core), and mainly implements parameter configuration, data flow control, data scheduling of each functional module and parsing and encapsulation of an internet protocol (only a receiving part needs to process the internet protocol); MIG (memory Interface Generator) is a DDR controller (soft core); the Ethernet _ pcs _ pma (soft core) and the AXI _ Ethernet (soft core) mainly realize the communication between the upper computer and the FPGA processing board card; GTX (hard core) is a high-speed serial data transceiver, and the single line rate can support 12Gb/s at most.

Generation of (a) chirp signals

The chirp signal is generated using a waveform direct read method. Firstly, storing a waveform file to be generated in Norflash, reading the waveform file from the Norflash to a DDR cache by an FPGA, and then sending the waveform file read from the DDR cache by the FPGA to a DAC through a JESD204B interface to form a chirp transmitting signal. The data processing flow is as shown in FIG. 7

The frequency modulation signal generation module is mainly used for generating frequency modulation signals with multiple gears and adjustable different repetition frequencies (1 kHz-500 kHz), wherein each repetition frequency comprises three waveforms of frequency rising, frequency falling and frequency invariance and is divided equally. The module control interface is a serial interface, and controllable signals are as follows: the size of a repetition period and the delay of two channels (the resolution is 100ns, and the range is 0-1 ms).

The frequency modulation signal adopts an AWG scheme, and Matlab is utilized to generate a corresponding waveform signal according to different frequency modulation repetition frequencies in the early stage, and the waveform signal is sampled and stored in the Nor flash. When receiving a starting signal generated by a frequency modulation source, directly reading the signal from the Nor flash to the DDR for buffering, and then sending the signal to the DAC.

Regarding the delay control part, a data delay processing block is optionally added at the channel 2. For an equivalent parallel 32 samples, lane 2 is delayed by 1 clock cycle of 125MHz relative to lane 1, which corresponds to a delay of 8ns for the lane 2 waveform relative to lane 1. And before the generation of the frequency modulation signal is started, calculating the number of delayed cycles according to the delay time. For integral multiple N delay, directly delaying N period output; for non-integer multiples of delay, additional data processing is required. For the lowest resolution of delay control, 100ns, that is, 100/8 is 12.5 clock cycles, data processing only needs to stagger a half cycle on the basis of delaying an integer cycle (only one cycle needs to be delayed in FPGA processing, then 16 samples after the previous cycle of the previous cycle are spliced into 32 samples, and 16 sample values in the previous cycle are 0 during initialization). Therefore, in the actual process, when the fm generation signal is received, the two channels respectively read the required waveform signal from the DDR into the FIFO, then the data transmission of the channel 1 is started first, and then the data transmission of the channel 2 is started according to the number of delay cycles, and the data delay process may only be two, that is, N half cycles (non-integer cycles) and N cycles (integer cycles).

In other technical features of the embodiment, those skilled in the art can flexibly select and use the features according to actual situations to meet different specific actual requirements. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known algorithms, methods or systems have not been described in detail so as not to obscure the present invention, and are within the scope of the present invention as defined by the claims.

For simplicity of explanation, the foregoing method embodiments are described as a series of acts or combinations, but those skilled in the art will appreciate that the present application is not limited by the order of acts, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and elements referred to are not necessarily required in this application.

Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The disclosed systems, modules, and methods may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be only one logical division, and there may be other divisions in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be referred to as an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

It will be understood by those skilled in the art that all or part of the processes in the methods for implementing the embodiments described above can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when executed, the program can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a ROM, a RAM, etc.

The foregoing is illustrative of the preferred embodiments of this invention, and it is to be understood that the invention is not limited to the precise form disclosed herein and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the concept as disclosed herein, either as described above or as apparent to those skilled in the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.