阅读说明：本技术 一种应用于单光子飞行时间测距系统的光子同步检测电路及其制备方法 (Photon synchronous detection circuit applied to single photon flight time ranging system and preparation method thereof ) 是由 韩冬 徐跃 孙飞阳 于 2019-09-30 设计创作，主要内容包括：本发明公开了一种应用于单光子飞行时间测距系统的光子同步检测电路及其制备方法。本发明属于激光测距和3D成像技术领域,包括T触发器TFF_1、T触发器TFF_2、T触发器TFF_3、T触发器TFF_4、树型判断电路以及复位电路。本发明适用于像素单元中各器件雪崩响应时间间隔较小或同时响应的情况；通过设定控制电平可以根据噪声的强弱改变噪声抑制性能的等级；本发明新颖且实现简单,不需要使用大面积的触发器部件,主要的树型判断电路仅采用简单的门电路连接,复杂度低,制造工艺完全和CMOS工艺兼容,制造成本低,各个电路之间的性能一致性好,成品率高,而且本发明主要部分采用数字电路的方式实现,检测结果具有更高的准确性和精度,电路具有很高的稳定性和可靠性。(The invention discloses a photon synchronous detection circuit applied to a single photon flight time ranging system and a preparation method thereof. The invention belongs to the technical field of laser ranging and 3D imaging, and comprises a T trigger TFF _1, a T trigger TFF _2, a T trigger TFF _3, a T trigger TFF _4, a tree-type judgment circuit and a reset circuit. The invention is suitable for the condition that the avalanche response time interval of each device in the pixel unit is smaller or the devices respond simultaneously; the level of the noise suppression performance can be changed according to the intensity of the noise by setting the control level; the invention is novel and simple to realize, does not need to use large-area trigger parts, the main tree type judgment circuit only adopts simple gate circuit connection, has low complexity, complete compatible manufacturing process with CMOS process, low manufacturing cost, good performance consistency among all circuits and high yield, and the main part of the invention is realized by adopting a digital circuit mode, so that the detection result has higher accuracy and precision, and the circuit has higher stability and reliability.)

1. The utility model provides a photon synchronous detection circuit for single photon time-of-flight ranging system which characterized in that: the photon synchronous detection circuit comprises a T trigger TFF _1, a T trigger TFF _2, a T trigger TFF _3, a T trigger TFF _4, a tree type judgment circuit and a reset circuit.

2. The photonic synchronization detection circuit applied to the single photon time-of-flight ranging system of claim 1,

the clock input end Clk1 of the T flip-flop TFF _1 and the input end W1 of the reset circuit are respectively connected to the avalanche pulse input signal a1 generated by the single-photon avalanche diode,

the clock input Clk2 of the T flip-flop TFF _2 and the input W2 of the reset circuit are respectively connected to the avalanche pulse input signal a2 generated by the single photon avalanche diode,

the clock input end Clk3 of the T flip-flop TFF _3 and the input end W3 of the reset circuit are respectively connected to the avalanche pulse input signal A3 generated by the single-photon avalanche diode,

the clock input end Clk4 of the T trigger TFF _1 and the input end W4 of the reset circuit are respectively connected to an avalanche pulse input signal A4 generated by the single-photon avalanche diode;

the trigger input end T1 of the T trigger TFF _1 is connected to a power supply voltage VDD, and the output end Q1 of the T trigger TFF _1 is connected to the input end A of the tree-type judging circuit;

the trigger input end T2 of the T trigger TFF _2 is connected to a power supply voltage VDD, and the output end Q2 of the T trigger TFF _2 is connected to the input end B of the tree-type judging circuit;

the trigger input end T3 of the T trigger TFF _3 is connected to a power supply voltage VDD, and the output end Q3 of the T trigger TFF _3 is connected to the input end C of the tree-type judging circuit;

the trigger input end T4 of the T trigger TFF _4 is connected to a power supply voltage VDD, and the output end Q4 of the T trigger TFF _4 is connected to the input end D of the tree-type judging circuit;

two input ends S1 and S0 of the tree-shaped judging circuit are respectively externally connected with working mode selection signals S1 and S0 to realize four working modes;

the TRIGGER signal TRIGGER output by the output end S of the reset circuit is connected to a subsequent time-digital conversion circuit and used for triggering the time-digital conversion circuit to start working;

the decision signal OK output by the output end OUT of the tree-type decision circuit is connected with a subsequent time-digital conversion circuit and used for deciding whether an avalanche pulse input signal of the photon synchronous detection circuit is triggered by effective laser photons or not, and when the decision signal OK is at a high level; the conversion result of the subsequent time-to-digital conversion circuit is valid when the determination signal OK is low; the conversion result of the subsequent time-to-digital conversion circuit is invalid;

the output end N of the Reset circuit outputs a local Reset signal Reset which is simultaneously connected with the Reset ends of a T trigger TFF _1, a T trigger TFF _2, a T trigger TFF _3 and a T trigger TFF _ 4;

and the input end R of the reset circuit is connected with an external global reset signal R.

3. The photonic synchronization detection circuit applied to the single photon time-of-flight ranging system of claim 1,

the tree type judgment circuit comprises a four-to-one data selector MUX, a four-input OR4_1, a four-input OR4_2, a four-input AND gate AND4_1, a three-input OR3_1, a three-input AND gate AND3_1, a three-input AND gate 3_2, a three-input AND gate AND3_3, a three-input AND gate 3_4, a two-input OR2_1, a two-input OR gate OR2_2, a two-input AND gate 2_1, a two-input AND gate AND2_2 AND a two-input AND gate 2_3,

wherein: the input end A of the tree type judgment circuit is respectively connected with a first input end of a four-input OR gate 4_1, one input end of a two-input AND gate 2_1, one input end of a two-input OR gate OR2_1, a first input end of a three-input AND gate 3_1, a first input end of a three-input AND gate 3_2, a first input end of a three-input AND gate 3_3 AND a first input end of a four-input AND gate 4_ 1;

the input end B of the tree type judgment circuit is respectively connected with the second input end of a four-input OR gate 4_1, the other input end of a two-input AND gate 2_1, the other input end of a two-input OR gate OR2_1, the second input end of a three-input AND gate 3_1, the second input end of a three-input AND gate 3_2, the first input end of a three-input AND gate 3_4 AND the second input end of a four-input AND gate 4_ 1;

the input end C of the tree-type judging circuit is respectively connected with the third input end of a four-input OR gate 4_1, one input end of a two-input OR gate OR2_2, one input end of a two-input AND gate 2_2, the third input end of a three-input AND gate 3_1, the second input end of a three-input AND gate 3_3, the second input end of a three-input AND gate 3_4 AND the third input end of a four-input AND gate 4_ 1;

the input end D of the tree type judgment circuit is respectively connected with the fourth input end of a four-input OR gate 4_1, the other input end of a two-input OR gate 2_2, the other input end of a two-input AND gate 2_2, the third input end of a three-input AND gate 3_2, the third input end of a three-input AND gate 3_3, the third input end of a three-input AND gate 3_4 AND the fourth input end of a four-input AND gate 4_ 1;

the output end of a two-input OR gate OR2_1 of the tree type judgment circuit is connected with one input end of a two-input AND gate 2_3, AND the output end of a two-input OR gate OR2_2 is connected with the other input end of a two-input AND gate 2_ 3; the output ends of the two-input AND gate AND2_1, the two-input AND gate AND2_2 AND the two-input AND gate AND2_3 are respectively connected with three input ends of a three-input OR gate OR3_ 1; the output ends of the three-input AND gate AND3_1, the three-input AND gate AND3_2, the three-input AND gate AND3_3 AND the three-input AND gate AND3_4 are respectively connected with four input ends of a four-input OR gate OR4_ 2; the output ends of the four-input OR gate OR4_1, the three-input OR gate OR3_1, the four-input OR gate OR4_2 AND the four-input AND gate AND4_1 are respectively connected with four data input ends C1, C2, C3 AND C4 of the four-one-by-one data selector MUX;

the control input terminals S1 and S0 of the one-OUT-of-four data selector MUX of the tree type decision circuit are externally connected with the operation mode selection signals S1 and S0, respectively, and the output terminal OUT of the data selector MUX outputs the decision signal OK.

4. The photonic synchronization detection circuit applied to the single photon time-of-flight ranging system of claim 1,

the reset circuit comprises a two-input OR gate OR _1, a two-input OR gate OR _2, a two-input OR gate OR _3, a two-input OR gate OR _4, a two-input NOR gate NOR _1, a two-input NOR gate NOR _2, a two-input NOR gate NOR _3, a PMOS transistor MP1, an NMOS transistor MN1 and an NMOS transistor MN2,

the input end W1 and the input end W2 of the reset circuit are respectively connected with two input ends of a two-input OR gate OR _1, the input end W3 and the input end W4 are respectively connected with two input ends of a two-input OR gate OR _2, the output ends of the two-input OR gate OR _1 and the two-input OR gate OR _2 are respectively connected with two input ends of a two-input OR gate OR _3, and the output end of the two-input OR gate OR _3 is connected with one input end of the two-input NOR gate NOR _ 2;

the other input end of the two-input NOR gate NOR _2 is simultaneously connected with the output end of the two-input NOR gate NOR _1, the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN 1; the output end of the two-input NOR gate NOR _2 is simultaneously connected with one input end of the two-input NOR gate NOR _1 and one input end of the two-input NOR gate NOR _ 3; the other input end of the two-input NOR gate NOR _1 is connected with the output end of the two-input OR gate OR _ 4;

the source electrode of the PMOS tube MP1 is connected with a power supply voltage VDD, the drain electrode of the PMOS tube MP1 is simultaneously connected with the drain electrode of the NMOS tube MN1, the gate electrode of the NMOS tube MN2 and the other input end of the two-input NOR gate NOR _ 3; the source electrode of the NMOS transistor MN1 is grounded; the drain electrode of the NMOS transistor MN2 is simultaneously connected with the source electrode and the ground;

the output end of the two-input NOR gate NOR _3 is connected with one input end of the two-input OR gate OR _4, and the input end R of the reset circuit is connected with the other input end of the two-input OR gate OR _ 4; the output end S of the two-input NOR gate NOR _1 outputs a TRIGGER signal TRIGGER; the output terminal N of the two-input OR gate OR _4 outputs a local Reset signal Reset.

5. The method of claim 1, wherein the circuit comprises three stages, namely a preparation stage, a start/detection stage, and a reset stage:

(1) and a preparation stage: firstly, before laser photons or ambient photon noise arrives, the global reset signal R is at a high level, and the output ends Q1, Q2, Q3 and Q4 of the T flip-flop TFF _1, the T flip-flop TFF _2, the T flip-flop TFF _3 and the T flip-flop TFF _4 are all at a low level; the tree-shaped judging circuit and the reset circuit stop working, and the output judging signal OK and the TRIGGER signal TRIGGER are both low level; when the global reset signal R is changed from high level to low level, the global reset work is completed; then setting the levels of the working mode selection signals S1 and S0, wherein the working mode I is set when S1 and S0 are low simultaneously; operation mode two when S1 is low and S0 is high; operation mode three with S1 high and S0 low; s1 and S0 are simultaneously in a high state, namely a working mode IV, and detection operation is prepared after the working mode is selected;

(2) and a starting/detecting stage: when a photon or noise arrives, namely, a high level is detected in the avalanche pulse input signal A1, the avalanche pulse input signal A2, the avalanche pulse input signal A3 and the avalanche pulse input signal A4, the output end Q of the corresponding T flip-flop TFF _1, TFF _2, TFF _3 and TFF _4 becomes a high level; the TRIGGER signal TRIGGER output by the output end S of the reset circuit becomes high level, and a subsequent time-digital conversion circuit is started to work; the tree-type judging circuit outputs a corresponding judging signal OK according to the selected working mode; when the working mode is selected, if only one signal of the four paths of avalanche pulse input signals responds in the detection time, the output of a signal OK is judged to be high level, and the conversion result of a subsequent time-digital conversion circuit is judged to be effective; when the second working mode is selected, when at least two paths of avalanche pulse input signals respond in the detection time, the judgment signal OK is output as a high level, and the conversion result of a subsequent time digital-conversion circuit is judged to be effective; when the third working mode is selected, when at least three avalanche pulse input signals respond in the detection time, the OK output signal is judged to be high level, and the conversion result of the subsequent time-digital conversion circuit is judged to be effective; when the working mode four is selected, when the four paths of avalanche pulse input signals all respond in the detection time, the judgment signal OK is output to be high level, and the conversion result of the subsequent time digital-conversion circuit is judged to be effective; thus, the functions of synchronous detection and noise suppression are realized;

(3) and a reset stage: when one triggering and detecting work is finished, the Reset circuit generates a local Reset signal Reset at the output end N of the Reset circuit through the charging and discharging process of the MOS capacitor formed by the NMOS tube MN2, and simultaneously resets the T trigger TFF _1, the T trigger TFF _2, the T trigger TFF _3 and the T trigger TFF _ 4.

Technical Field

The invention belongs to the technical field of laser ranging and 3D imaging; a photon synchronous detection circuit applied to a single photon flight time ranging system and a preparation method thereof are provided.

Background

The Single-Photon Avalanche Diode (SPAD) has wide application prospect in the technical fields of Single-Photon flight time ranging, 3D imaging and the like due to the remarkable advantages of high sensitivity, high detection efficiency, high time resolution, low power consumption, complete compatibility with a CMOS (complementary metal oxide semiconductor) process and the like. However, in the application of single photon time-of-flight ranging, when detecting photons of laser echoes, the SPAD device is seriously affected by environmental photon noise, and how to inhibit the interference of environmental photons is particularly important when the environmental light is strong and the target distance is long. When the traditional door and window method is adopted, when the photon noise of the external environment is large, the avalanche response interval time of the devices in the pixel units is short or the devices simultaneously respond, so that the counting of the counter is seriously wrong, and the method cannot inhibit the strong photon noise of the environment. The invention provides a novel digital photon synchronous detection circuit, which can still have good noise suppression capability under the conditions of large photon noise in the external environment and short avalanche response interval time of a device in a pixel unit, can effectively reduce the complexity of the circuit and improve the detection precision while improving the noise suppression capability and the application range of a detector, and greatly improves the manufacturability and the reliability of a ranging pixel unit.

Disclosure of Invention

The invention aims to solve the problems that the existing photon synchronous detection circuit is complex in structure, difficult to manufacture, low in detection precision and the like, and provides a photon synchronous detection circuit which is simple in circuit structure, low in cost and high in precision and a preparation method thereof, which are applied to single photon flight time distance measurement.

The technical scheme of the invention is as follows: a photon synchronous detection circuit applied to a single photon flight time ranging system comprises a T trigger TFF _1, a T trigger TFF _2, a T trigger TFF _3, a T trigger TFF _4, a tree type judgment circuit and a reset circuit,

wherein:

the clock input end Clk1 of the T flip-flop TFF _1 and the input end W1 of the reset circuit are respectively connected to the avalanche pulse input signal a1 generated by the single-photon avalanche diode,

the clock input Clk2 of the T flip-flop TFF _2 and the input W2 of the reset circuit are respectively connected to the avalanche pulse input signal a2 generated by the single photon avalanche diode,

the clock input end Clk3 of the T flip-flop TFF _3 and the input end W3 of the reset circuit are respectively connected to the avalanche pulse input signal A3 generated by the single-photon avalanche diode,

the clock input end Clk4 of the T trigger TFF _1 and the input end W4 of the reset circuit are respectively connected to an avalanche pulse input signal A4 generated by the single-photon avalanche diode;

the trigger input end T1 of the T trigger TFF _1 is connected to a power supply voltage VDD, and the output end Q1 of the T trigger TFF _1 is connected to the input end A of the tree-type judging circuit;

the trigger input end T2 of the T trigger TFF _2 is connected to a power supply voltage VDD, and the output end Q2 of the T trigger TFF _2 is connected to the input end B of the tree-type judging circuit;

the trigger input end T3 of the T trigger TFF _3 is connected to a power supply voltage VDD, and the output end Q3 of the T trigger TFF _3 is connected to the input end C of the tree-type judging circuit;

the trigger input end T4 of the T trigger TFF _4 is connected to a power supply voltage VDD, and the output end Q4 of the T trigger TFF _4 is connected to the input end D of the tree-type judging circuit;

two input ends S1 and S0 of the tree-shaped judging circuit are respectively externally connected with working mode selection signals S1 and S0 to realize four working modes;

the TRIGGER signal TRIGGER output by the output end S of the reset circuit is connected to a subsequent time-digital conversion circuit and used for triggering the time-digital conversion circuit to start working;

the decision signal OK output by the output end OUT of the tree-type decision circuit is connected with a subsequent time-digital conversion circuit and used for deciding whether an avalanche pulse input signal of the photon synchronous detection circuit is triggered by effective laser photons or not, and when the decision signal OK is at a high level; the conversion result of the subsequent time-to-digital conversion circuit is valid when the determination signal OK is low; the conversion result of the subsequent time-to-digital conversion circuit is invalid;

the output end N of the Reset circuit outputs a local Reset signal Reset which is simultaneously connected with Reset ends Reset1, Reset2, Reset3 and Reset4 of a T flip-flop TFF _1, a T flip-flop TFF _2, a T flip-flop TFF _3 and a T flip-flop TFF _ 4;

and the input end R of the reset circuit is connected with an external global reset signal R.

Preferably, the tree type decision circuit includes a four-to-one data selector MUX, a four-input OR gate OR4_1, a four-input OR gate OR4_2, a four-input AND gate AND4_1, a three-input OR gate OR3_1, a three-input AND gate AND3_1, a three-input AND gate AND3_2, a three-input AND gate AND3_3, a three-input AND gate AND3_4, a two-input OR gate OR2_1, a two-input OR gate OR2_2, a two-input AND gate AND2_1, a two-input AND gate 2_2, a two-input AND gate AND2_3,

wherein: the input end A of the tree type judgment circuit is respectively connected with the first input end of a four-input OR gate 4_1, one input end of a two-input AND gate 2_1, one input end of a two-input OR gate OR2_1, the first input end of a three-input AND gate 3_1, the first input end of a three-input AND gate 3_2, the first input end of a three-input AND gate 3_3 AND the first input end of a four-input AND gate 4_ 1;

the input end B of the tree-type judging circuit is respectively connected with the second input end of the four-input OR gate OR4_1, the other input end of the two-input AND gate AND2_1, the other input end of the two-input OR gate OR2_1, the second input end of the three-input AND gate AND3_1, the second input end of the three-input AND gate AND3_2, the first input end of the three-input AND gate AND3_4 AND the second input end of the four-input AND gate AND4_ 1;

the input end C of the tree-type judging circuit is respectively connected with the third input end of a four-input OR gate 4_1, one input end of a two-input OR gate OR2_2, one input end of a two-input AND gate 2_2, the third input end of a three-input AND gate 3_1, the second input end of a three-input AND gate 3_3, the second input end of a three-input AND gate 3_4 AND the third input end of a four-input AND gate 4_ 1;

the input end D of the tree-type judging circuit is respectively connected with a fourth input end of a four-input OR gate 4_1, another input end of a two-input OR gate 2_2, another input end of a two-input AND gate 2_2, a third input end of a three-input AND gate 3_2, a third input end of a three-input AND gate 3_3, a third input end of a three-input AND gate 3_4 AND a fourth input end of a four-input AND gate 4_ 1;

the output end of a two-input OR gate OR2_1 of the tree type judgment circuit is connected with one input end of a two-input AND gate 2_3, AND the output end of a two-input OR gate OR2_2 is connected with the other input end of a two-input AND gate 2_ 3; the output ends of the two-input AND gate AND2_1, the two-input AND gate AND2_2 AND the two-input AND gate AND2_3 are respectively connected with three input ends of a three-input OR gate OR3_ 1; the output ends of the three-input AND gate AND3_1, the three-input AND gate AND3_2, the three-input AND gate AND3_3 AND the three-input AND gate AND3_4 are respectively connected with four input ends of a four-input OR gate OR4_ 2; the output ends of the four-input OR gate OR4_1, the three-input OR gate OR3_1, the four-input OR gate OR4_2 AND the four-input AND gate AND4_1 are respectively connected with four data input ends C1, C2, C3 AND C4 of the four-one-by-one data selector MUX;

the control input terminals S1 and S0 of the one-OUT-of-four data selector MUX of the tree type decision circuit are externally connected with the operation mode selection signals S1 and S0, respectively, and the output terminal OUT of the data selector MUX outputs the decision signal OK.

Preferably, the reset circuit comprises a two-input OR gate OR _1, a two-input OR gate OR _2, a two-input OR gate OR _3, a two-input OR gate OR _4, a two-input NOR gate NOR _1, a two-input NOR gate NOR _2, a two-input NOR gate NOR _3, a PMOS transistor MP1, an NMOS transistor MN1 and an NMOS transistor MN2,

the input end W1 and the input end W2 of the reset circuit are respectively connected with two input ends of a two-input OR gate OR _1, the input end W3 and the input end W4 are respectively connected with two input ends of a two-input OR gate OR _2, the output ends of the two-input OR gate OR _1 and the two-input OR gate OR _2 are respectively connected with two input ends of a two-input OR gate OR _3, and the output end of the two-input OR gate OR _3 is connected with one input end of the two-input NOR gate NOR _ 2;

the other input end of the two-input NOR gate NOR _2 is simultaneously connected with the output end of the two-input NOR gate NOR _1, the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN 1; the output end of the two-input NOR gate NOR _2 is simultaneously connected with one input end of the two-input NOR gate NOR _1 and one input end of the two-input NOR gate NOR _ 3; the other input end of the two-input NOR gate NOR _1 is connected with the output end of the two-input OR gate OR _ 4;

the source electrode of the PMOS tube MP1 is connected with a power supply voltage VDD, the drain electrode of the PMOS tube MP1 is simultaneously connected with the drain electrode of the NMOS tube MN1, the gate electrode of the NMOS tube MN2 and the other input end of the two-input NOR gate NOR _ 3; the source electrode of the NMOS transistor MN1 is grounded; the drain electrode of the NMOS transistor MN2 is simultaneously connected with the source electrode and the ground;

the output end of the two-input NOR gate NOR _3 is connected with one input end of the two-input OR gate OR _4, and the input end R of the reset circuit is connected with the other input end of the two-input OR gate OR _ 4; the output end S of the two-input NOR gate NOR _1 outputs a TRIGGER signal TRIGGER; the output terminal N of the two-input OR gate OR _4 outputs a local Reset signal Reset.

Preferably, the work flow of the circuit comprises three phases, namely a preparation phase, a start/detection phase and a reset phase:

(1) and a preparation stage: firstly, before laser photons or ambient photon noise arrives, the global reset signal R is at a high level, and the output ends Q1, Q2, Q3 and Q4 of the T flip-flop TFF _1, the T flip-flop TFF _2, the T flip-flop TFF _3 and the T flip-flop TFF _4 are all at a low level; the tree-shaped judging circuit and the reset circuit stop working, and the output judging signal OK and the TRIGGER signal TRIGGER are both low level; when the global reset signal R is changed from high level to low level, the global reset work is completed; then setting the levels of the working mode selection signals S1 and S0, wherein the working mode I is set when S1 and S0 are low simultaneously; operation mode two when S1 is low and S0 is high; operation mode three with S1 high and S0 low; s1 and S0 are simultaneously in a high state, namely a working mode IV, and detection operation is prepared after the working mode is selected;

(2) and a starting/detecting stage: when a photon or noise arrives, namely, a high level is detected in the avalanche pulse input signal A1, the avalanche pulse input signal A2, the avalanche pulse input signal A3 and the avalanche pulse input signal A4, the output end Q of the corresponding T flip-flop TFF _1, TFF _2, TFF _3 and TFF _4 becomes a high level; the TRIGGER signal TRIGGER output by the output end S of the reset circuit becomes high level, and a subsequent time-digital conversion circuit is started to work; the tree-type judging circuit outputs a corresponding judging signal OK according to the selected working mode; when the working mode is selected, if only one signal of the four paths of avalanche pulse input signals responds in the detection time, the output of a signal OK is judged to be high level, and the conversion result of a subsequent time digital-conversion circuit is judged to be effective; when the second working mode is selected, when at least two paths of avalanche pulse input signals respond in the detection time, the judgment signal OK is output as a high level, and the conversion result of a subsequent time digital-conversion circuit is judged to be effective; when the third working mode is selected, when at least three avalanche pulse input signals respond in the detection time, the OK output signal is judged to be high level, and the conversion result of the subsequent time-digital conversion circuit is judged to be effective; when the working mode four is selected, when the four paths of avalanche pulse input signals all respond in the detection time, the judgment signal OK is output to be high level, and the conversion result of the subsequent time digital-conversion circuit is judged to be effective; thus, the functions of synchronous detection and noise suppression are realized;

(3) and a reset stage: when one triggering and detecting work is finished, the Reset circuit generates a local Reset signal Reset at the output end N of the Reset circuit through the charging and discharging process of the MOS capacitor formed by the NMOS tube MN2, and simultaneously resets the T trigger TFF _1, the T trigger TFF _2, the T trigger TFF _3 and the T trigger TFF _ 4.

The invention has the beneficial effects that: 1. the photon synchronous detection circuit provided by the invention can accurately and efficiently suppress noise in single photon flight time ranging. The synchronous detection method is applicable to the condition that the avalanche response time interval of each device in the pixel unit is small or the devices respond simultaneously; the level of the noise suppression performance can be changed according to the intensity of the noise by setting the control level.

2. The photon synchronous detection circuit provided by the invention has the advantages of novel structure, simple realization, no need of using large-area trigger parts, low complexity, complete compatibility of the manufacturing process and the CMOS process, low manufacturing cost, good performance consistency among all circuits and high yield, and the main tree type judgment circuit only adopts simple gate circuit connection.

3. The main part of the photon synchronous detection circuit provided by the invention is realized by adopting a digital circuit mode, the detection result has higher accuracy and precision, and the circuit has higher stability and reliability.

Drawings

FIG. 1 is a schematic diagram of the overall circuit structure of the photonic synchronous detection circuit according to the present invention;

FIG. 2 is a schematic diagram of a tree-type decision circuit according to the present invention;

FIG. 3 is a schematic diagram of a reset circuit according to the present invention;

FIG. 4 is a timing diagram of the operation of the photonic synchronous detection circuit according to the present invention;

fig. 5 is a schematic diagram of a simulation result of an embodiment of the photonic synchronous detection circuit according to the present invention.

Detailed Description

The present invention is further illustrated by the following description in conjunction with the accompanying drawings and the specific embodiments, it is to be understood that these examples are given solely for the purpose of illustration and are not intended as a definition of the limits of the invention, since various equivalent modifications will occur to those skilled in the art upon reading the present invention and fall within the limits of the appended claims.

As shown in fig. 1, a photon synchronous detection circuit applied to a single photon time-of-flight ranging system; the photon synchronous detection circuit comprises a T trigger TFF _1, a T trigger TFF _2, a T trigger TFF _3, a T trigger TFF _4, a tree type judgment circuit and a reset circuit,

wherein:

the clock input end Clk1 of the T flip-flop TFF _1 and the input end W1 of the reset circuit are respectively connected to the avalanche pulse input signal a1 generated by the single-photon avalanche diode,

the clock input Clk2 of the T flip-flop TFF _2 and the input W2 of the reset circuit are respectively connected to the avalanche pulse input signal a2 generated by the single photon avalanche diode,

the clock input end Clk3 of the T flip-flop TFF _3 and the input end W3 of the reset circuit are respectively connected to the avalanche pulse input signal A3 generated by the single-photon avalanche diode,

the clock input end Clk4 of the T trigger TFF _1 and the input end W4 of the reset circuit are respectively connected to an avalanche pulse input signal A4 generated by the single-photon avalanche diode;

the trigger input end T1 of the T trigger TFF _1 is connected to a power supply voltage VDD, and the output end Q1 of the T trigger TFF _1 is connected to the input end A of the tree-type judging circuit;

the trigger input end T2 of the T trigger TFF _2 is connected to a power supply voltage VDD, and the output end Q2 of the T trigger TFF _2 is connected to the input end B of the tree-type judging circuit;

the trigger input end T3 of the T trigger TFF _3 is connected to a power supply voltage VDD, and the output end Q3 of the T trigger TFF _3 is connected to the input end C of the tree-type judging circuit;

the trigger input end T4 of the T trigger TFF _4 is connected to a power supply voltage VDD, and the output end Q4 of the T trigger TFF _4 is connected to the input end D of the tree-type judging circuit;

two input ends S1 and S0 of the tree-shaped judging circuit are respectively externally connected with working mode selection signals S1 and S0 to realize four working modes;

the TRIGGER signal TRIGGER output by the output end S of the reset circuit is connected to a subsequent time-digital conversion circuit and used for triggering the time-digital conversion circuit to start working;

the decision signal OK output by the output end OUT of the tree-type decision circuit is connected with a subsequent time-digital conversion circuit and used for deciding whether an avalanche pulse input signal of the photon synchronous detection circuit is triggered by effective laser photons or not, and when the decision signal OK is at a high level; the conversion result of the subsequent time-to-digital conversion circuit is valid when the determination signal OK is low; the conversion result of the subsequent time-to-digital conversion circuit is invalid;

the output end N of the Reset circuit outputs a local Reset signal Reset which is simultaneously connected with Reset ends Reset1, Reset2, Reset3 and Reset4 of a T flip-flop TFF _1, a T flip-flop TFF _2, a T flip-flop TFF _3 and a T flip-flop TFF _ 4;

and the input end R of the reset circuit is connected with an external global reset signal R.

As shown in fig. 2, the tree type decision circuit includes a four-to-one data selector MUX, a four-input OR gate OR4_1, a four-input OR gate OR4_2, a four-input AND gate AND4_1, a three-input OR gate OR3_1, a three-input AND gate AND3_1, a three-input AND gate AND3_2, a three-input AND gate AND3_3, a three-input AND gate AND3_4, a two-input OR gate OR2_1, a two-input OR gate OR2_2, a two-input AND gate AND2_1, a two-input AND gate AND2_2, AND a two-input AND gate 2_3,

wherein: the input end A of the tree type judgment circuit is respectively connected with the first input end of a four-input OR gate 4_1, one input end of a two-input AND gate 2_1, one input end of a two-input OR gate OR2_1, the first input end of a three-input AND gate 3_1, the first input end of a three-input AND gate 3_2, the first input end of a three-input AND gate 3_3 AND the first input end of a four-input AND gate 4_ 1;

the input end B of the tree-type judging circuit is respectively connected with the second input end of the four-input OR gate OR4_1, the other input end of the two-input AND gate AND2_1, the other input end of the two-input OR gate OR2_1, the second input end of the three-input AND gate AND3_1, the second input end of the three-input AND gate AND3_2, the first input end of the three-input AND gate AND3_4 AND the second input end of the four-input AND gate AND4_ 1;

the input end C of the tree-type judging circuit is respectively connected with the third input end of a four-input OR gate 4_1, one input end of a two-input OR gate OR2_2, one input end of a two-input AND gate 2_2, the third input end of a three-input AND gate 3_1, the second input end of a three-input AND gate 3_3, the second input end of a three-input AND gate 3_4 AND the third input end of a four-input AND gate 4_ 1;

the input end D of the tree-type judging circuit is respectively connected with a fourth input end of a four-input OR gate 4_1, another input end of a two-input OR gate 2_2, another input end of a two-input AND gate 2_2, a third input end of a three-input AND gate 3_2, a third input end of a three-input AND gate 3_3, a third input end of a three-input AND gate 3_4 AND a fourth input end of a four-input AND gate 4_ 1;

the output end of a two-input OR gate OR2_1 of the tree type judgment circuit is connected with one input end of a two-input AND gate 2_3, AND the output end of a two-input OR gate OR2_2 is connected with the other input end of a two-input AND gate 2_ 3; the output ends of the two-input AND gate AND2_1, the two-input AND gate AND2_2 AND the two-input AND gate AND2_3 are respectively connected with three input ends of a three-input OR gate OR3_ 1; the output ends of the three-input AND gate AND3_1, the three-input AND gate AND3_2, the three-input AND gate AND3_3 AND the three-input AND gate AND3_4 are respectively connected with four input ends of a four-input OR gate OR4_ 2; the output ends of the four-input OR gate OR4_1, the three-input OR gate OR3_1, the four-input OR gate OR4_2 AND the four-input AND gate AND4_1 are respectively connected with four data input ends C1, C2, C3 AND C4 of the four-one-by-one data selector MUX;

the control input terminals S1 and S0 of the one-OUT-of-four data selector MUX of the tree type decision circuit are externally connected with the operation mode selection signals S1 and S0, respectively, and the output terminal OUT of the data selector MUX outputs the decision signal OK.

As shown in fig. 3, the reset circuit includes a two-input OR gate OR _1, a two-input OR gate OR _2, a two-input OR gate OR _3, a two-input OR gate OR _4, a two-input NOR gate NOR _1, a two-input NOR gate NOR _2, a two-input NOR gate NOR _3, a PMOS transistor MP1, an NMOS transistor MN1, and an NMOS transistor MN2,

the input end W1 and the input end W2 of the reset circuit are respectively connected with two input ends of a two-input OR gate OR _1, the input end W3 and the input end W4 are respectively connected with two input ends of a two-input OR gate OR _2, the output ends of the two-input OR gate OR _1 and the two-input OR gate OR _2 are respectively connected with two input ends of a two-input OR gate OR _3, and the output end of the two-input OR gate OR _3 is connected with one input end of the two-input NOR gate NOR _ 2;

the other input end of the two-input NOR gate NOR _2 is simultaneously connected with the output end of the two-input NOR gate NOR _1, the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN 1; the output end of the two-input NOR gate NOR _2 is simultaneously connected with one input end of the two-input NOR gate NOR _1 and one input end of the two-input NOR gate NOR _ 3; the other input end of the two-input NOR gate NOR _1 is connected with the output end of the two-input OR gate OR _ 4;

the source electrode of the PMOS tube MP1 is connected with a power supply voltage VDD, the drain electrode of the PMOS tube MP1 is simultaneously connected with the drain electrode of the NMOS tube MN1, the gate electrode of the NMOS tube MN2 and the other input end of the two-input NOR gate NOR _ 3; the source electrode of the NMOS transistor MN1 is grounded; the drain electrode of the NMOS transistor MN2 is simultaneously connected with the source electrode and the ground;

the output end of the two-input NOR gate NOR _3 is connected with one input end of the two-input OR gate OR _4, and the input end R of the reset circuit is connected with the other input end of the two-input OR gate OR _ 4; the output end S of the two-input NOR gate NOR _1 outputs a TRIGGER signal TRIGGER; the output terminal N of the two-input OR gate OR _4 outputs a local Reset signal Reset.

When the input end W1, the input end W2, the input end W3 and the input end W4 of the reset circuit are at a low level, the global reset signal R is at a high level, the output of the two-input OR gate four OR _4 is at a high level, the output end S of the two-input NOR gate NOR _1 is at a low level, and the high level is output to the gate of the NMOS transistor MN2 after passing through the PMOS transistor MP1 and the NMOS transistor MN1, so that the MOS capacitor formed by the NMOS transistor MN2 is charged; when the input end W1, the input end W2, the input end W3 and the input end W4 of the reset circuit have active high levels, the two-input OR gate OR _3 outputs high level, and the TRIGGER signal TRIGGER output by the output end S of the two-input NOR gate NOR _1 is at high level; meanwhile, the high level output by the output end S of the two-input NOR gate NOR _1 passes through the PMOS tube MP1 and the NMOS tube MN1 and then outputs the low level to the gate of the NMOS tube MN2, and the MOS capacitor formed by the NMOS tube MN2 is discharged with certain delay, so that the potential of the gate of the NMOS tube MN2 is reduced in delay; the potential of the gate of the NMOS transistor MN2 and the low level of the output terminal of the two-input NOR gate NOR _2 are negated through the two-input NOR gate NOR _ 3; the result of the NOR is further connected with the global Reset signal R through the two-input OR gate OR _4, and a local Reset signal Reset is generated at the output end N of the Reset circuit, and the local Reset signal is simultaneously sent to one input end of the two-input NOR gate NOR _1 and Reset ends Reset1, Reset2, Reset3 and Reset4 of the four T flip-flops, so that Reset zero clearing after one operation is realized.

As shown in fig. 4, the work flow of the circuit includes three phases, namely, a preparation phase, a start/detection phase, and a reset phase:

(1) and a preparation stage: firstly, before laser photons or ambient photon noise arrives, the global reset signal R is at a high level, and the output ends Q1, Q2, Q3 and Q4 of the T flip-flop TFF _1, the T flip-flop TFF _2, the T flip-flop TFF _3 and the T flip-flop TFF _4 are all at a low level; the tree-shaped judging circuit and the reset circuit stop working, and the output judging signal OK and the TRIGGER signal TRIGGER are both low level; when the global reset signal R is changed from high level to low level, the global reset work is completed; then setting the levels of the working mode selection signals S1 and S0, wherein the working mode I is set when S1 and S0 are low simultaneously; operation mode two when S1 is low and S0 is high; operation mode three with S1 high and S0 low; s1 and S0 are simultaneously in a high state, namely a working mode IV, and detection operation is prepared after the working mode is selected;

(2) and a starting/detecting stage: when a photon or noise arrives, namely, a high level is detected in the avalanche pulse input signal A1, the avalanche pulse input signal A2, the avalanche pulse input signal A3 and the avalanche pulse input signal A4, the output end Q of the corresponding T flip-flop TFF _1, TFF _2, TFF _3 and TFF _4 becomes a high level; the TRIGGER signal TRIGGER output by the output end S of the reset circuit becomes high level, and a subsequent time-digital conversion circuit is started to work; the tree-type judging circuit outputs a corresponding judging signal OK according to the selected working mode; when the working mode is selected, if only one signal of the four paths of avalanche pulse input signals responds in the detection time, the output of a signal OK is judged to be high level, and the conversion result of a subsequent time digital-conversion circuit is judged to be effective; when the second working mode is selected, when at least two paths of avalanche pulse input signals respond in the detection time, the judgment signal OK is output as a high level, and the conversion result of a subsequent time digital-conversion circuit is judged to be effective; when the third working mode is selected, when at least three avalanche pulse input signals respond in the detection time, the OK output signal is judged to be high level, and the conversion result of the subsequent time-digital conversion circuit is judged to be effective; when the working mode four is selected, when the four paths of avalanche pulse input signals all respond in the detection time, the judgment signal OK is output to be high level, and the conversion result of the subsequent time digital-conversion circuit is judged to be effective; thus, the functions of synchronous detection and noise suppression are realized;

(3) and a reset stage: when one triggering and detecting work is finished, the Reset circuit generates a local Reset signal Reset at the output end N of the Reset circuit through the charging and discharging process of the MOS capacitor formed by the NMOS tube MN2, and simultaneously resets the T trigger TFF _1, the T trigger TFF _2, the T trigger TFF _3 and the T trigger TFF _ 4.