阅读说明：本技术 一种基于负反馈的高精度频率锁定电路 (High-precision frequency locking circuit based on negative feedback ) 是由 李响 蔡胜凯 董渊 于 2021-08-18 设计创作，主要内容包括：本发明公开了一种基于负反馈的高精度频率锁定电路,涉及时钟产生电路领域,该高精度频率锁定电路由开关控制电路按照输出的信号的输出频率调节电压输出回路中的开关的开闭频率,从而调节电路电压输出回路提供给压控振荡器的输入电压,使得压控振荡器改变输出的信号的输出频率,实现对输出频率的负反馈调节直到达到稳定,该高精度频率锁定电路无需复杂的补偿电路就可以保持高精度且高稳定性的输出频率,具有较优的电路性能。(The invention discloses a high-precision frequency locking circuit based on negative feedback, which relates to the field of clock generation circuits, wherein a switch control circuit adjusts the switching frequency of a switch in a voltage output loop according to the output frequency of an output signal, so that the input voltage provided by the voltage output loop to a voltage-controlled oscillator is adjusted, the voltage-controlled oscillator changes the output frequency of the output signal, the negative feedback adjustment of the output frequency is realized until the output frequency is stable, the high-precision frequency locking circuit can keep the output frequency with high precision and high stability without a complex compensation circuit, and the high-precision frequency locking circuit has better circuit performance.)

1. A high-precision frequency locking circuit based on negative feedback is characterized by comprising a voltage output loop, a voltage-controlled oscillator and a switch control circuit; in the voltage output loop, a capacitor C_FThe negative electrode of the first switch is grounded, and the positive electrode of the first switch passes through the first switch S₁Is connected with a reference voltage terminal V_BCapacitor C₂The negative electrode of the reference voltage terminal is grounded, and the positive electrode of the reference voltage terminal is connected with the reference voltage terminal V_BCapacitor C_FAre connected in parallel with a second switch S₂Said reference voltage terminal V_BIs connected to a power supply VDD through a switching tube, and the capacitor C_FIs much smaller than the capacitance C₂；

The input end of the voltage-controlled oscillator is connected to the voltage output loop to obtain input voltage, the output end of the voltage-controlled oscillator is used as the signal output end of the high-precision frequency locking circuit, and the output frequency f of the signal output by the signal output end_clkoutPositively correlated with the input voltage of the voltage controlled oscillator;

the first switch S₁And a second switch S₂Are complementary and do not overlap, the switch control circuit being responsive to the output frequency f_clkoutAdjusting the first switch S₁And a second switch S₂So that the input voltage and the output frequency f of the voltage controlled oscillator_clkoutForm a negative correlation with respect to the output frequency f_clkoutNegative feedback regulation of (2).

2. The high accuracy frequency locking circuit of claim 1 wherein said first switch S₁And a second switch S₂The two switches are alternately closed once to form a switching period, the closing time of the two switches in the switching period is equal, and the capacitor C₂Is decreased by Δ q ═ V in one switching cycle_BC_FSo that the equivalent sinking current of the reference voltage terminal isWhen the output frequency is increased, the switching period is decreased to decrease the voltage value of the reference voltage end and decrease the input voltage of the voltage-controlled oscillator, so as to drive the output frequency to decrease until the output frequency reaches a preset value, and when the output frequency is decreased, the switching period is increased to increase the voltage value of the reference voltage end and increase the input voltage of the voltage-controlled oscillator, so as to drive the output frequency to increase until the output frequency reaches the preset value, so that the output frequency f is increased_clkoutNegative feedback regulation of (2).

3. A high accuracy frequency locking circuit as in claim 2 wherein said switch control circuit comprises an N-divider, said switch control circuit being in accordance withRespectively control the on-off state of two switches, the switching period

4. The high accuracy frequency locking circuit of claim 1, wherein said reference voltage terminal V is in said voltage output loop_BThe source electrode of a second NMOS transistor MN2 is connected, the drain electrode of the second NMOS transistor MN2 is connected with the drain electrode of a second PMOS transistor MP2, and the drain electrode of the second PMOS transistor MP2The source electrode is connected with the power supply VDD, and the common end of the second PMOS transistor MP2 and the second NMOS transistor MN2 is connected with the input end of the voltage-controlled oscillator;

a first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to form a current mirror, the drain terminal of the first PMOS transistor MP1 is connected to the drain electrode of a first NMOS transistor MN1, and the source electrode of the first NMOS transistor MN1 passes through a resistor R_FThe first NMOS transistor MN1 is connected with the gate of the second NMOS transistor MN2 and the output end of the operational amplifier, the non-inverting input end of the operational amplifier is connected with a reference voltage V_REFAnd the inverting input end is connected with the source electrode of the first NMOS tube MN 1.

5. The high accuracy frequency lock circuit of claim 4, wherein the output frequency f_clkoutOnly with the capacitor C_FAnd the capacitance value of (C) and the resistance R_FIs related to the reference voltage V_REFIs irrelevant.

6. The high accuracy frequency lock circuit of claim 4, wherein the output frequency is greater than the output frequencyWhere k is an inherent coefficient related to the circuit structure.

7. The high accuracy frequency lock circuit of claim 6, wherein the output frequency is greater than the output frequencyWherein m is the current ratio of the first PMOS tube MP1 to the second PMOS tube MP2 in the current mirror, and the switch control circuit is used for controlling the output frequency f_clkoutAs the switching frequency of the two switches.

Technical Field

The invention relates to the field of clock generation circuits, in particular to a high-precision frequency locking circuit based on negative feedback.

Background

Clock generation circuits are an important part of integrated circuits, and in many integrated circuits, the clock generation circuits are required to output reference clock signals so that digital circuits and analog circuits with switching actions are normally operated. Common clock generation circuits include an LC oscillator using LC resonance, a ring oscillator in which a plurality of inverters are connected in series, and a comparison oscillator which determines an oscillation frequency by comparing a charged/discharged capacitor voltage with a reference voltage.

A conventional oscillator circuit is shown in fig. 1, and compares a ramp-up signal with a comparator to determine an oscillation frequency. The biggest disadvantage of this oscillator is that the delay of the comparator affects the oscillation frequency, and when the output signal frequency is high, the delay variation of the comparator can seriously affect the oscillation frequency under different temperature and process drifts. Another common oscillator circuit configuration is shown in fig. 2, which is a conventional ring oscillator in which a capacitor and a resistor determine the large signal delay of the inverter chain, thereby determining the oscillation frequency. The traditional ring oscillator has larger oscillation frequency change under different temperatures and process drifts, and meanwhile, the oscillation frequency of the traditional ring oscillator does not change linearly along with resistance or capacitance, so that the traditional ring oscillator is not suitable for application needing to adjust the frequency of the oscillator in a larger range. The existing various oscillators also have inherent defects in the aspects of stability of output frequency, circuit power consumption, precision and circuit area.

Disclosure of Invention

The present invention provides a high-precision frequency locking circuit based on negative feedback, aiming at the above problems and technical requirements, and the technical scheme of the present invention is as follows:

a high-precision frequency locking circuit based on negative feedback comprises a voltage output loop, a voltage-controlled oscillator and a switch control circuit; in the voltage output circuit, a capacitor C_FThe negative electrode of the first switch is grounded, and the positive electrode of the first switch passes through the first switch S₁Is connected with a reference voltage terminal V_BCapacitor C₂The negative electrode of the transformer is grounded, and the positive electrode of the transformer is connected with a reference voltage end V_BCapacitor C_FAre connected in parallel with a second switch S₂Reference voltage terminal V_BIs connected to a power supply VDD and a capacitor C through a switching tube_FHas a capacitance value much smaller than that of the capacitor C₂；

The input end of the voltage-controlled oscillator is connected to the voltage output circuit to obtain the input voltage, the output end of the voltage-controlled oscillator is used as the signal output end of the high-precision frequency locking circuit, and the signal output by the signal output endOutput frequency f of the signal_clkoutPositively correlated with the input voltage of the voltage controlled oscillator;

first switch S₁And a second switch S₂Are complementary and do not overlap, the switch control circuit is based on the output frequency f_clkoutAdjusting the first switch S₁And a second switch S₂So that the input voltage and the output frequency f of the voltage-controlled oscillator_clkoutForm a pair of output frequencies f in negative correlation_clkoutNegative feedback regulation of (2).

The further technical proposal is that the first switch S₁And a second switch S₂One switching period is formed by alternately closing the two switches once, the closing time of the two switches in one switching period is equal, and the capacitor C₂Is decreased by Δ q ═ V in one switching cycle_BC_FSo that the equivalent sinking current of the reference voltage terminal isWhen the output frequency is increased, the switching period is reduced to reduce the voltage value of the reference voltage end and reduce the input voltage of the voltage-controlled oscillator, the output frequency is driven to be reduced until the output frequency reaches a preset value, when the output frequency is reduced, the switching period is increased to increase the voltage value of the reference voltage end and increase the input voltage of the voltage-controlled oscillator, the output frequency is driven to be increased until the output frequency reaches the preset value, and the output frequency f is output_clkoutNegative feedback regulation of (2).

The further technical scheme is that the switch control circuit comprises an N frequency divider and is characterized in thatRespectively controlling the on-off state and the on-off period of the two switches

The further technical scheme is that in a voltage output loop, a reference voltage end V_BThe source electrode of the second NMOS transistor MN2 is connected, and the drain electrode of the second NMOS transistor MN2 is connected with the second PMOS transistorThe drain electrode of the MP2, the source electrode of the second PMOS tube MP2 are connected with a power supply VDD, and the common end of the second PMOS tube MP2 and the second NMOS tube MN2 is connected with the input end of the voltage-controlled oscillator;

the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to form a current mirror, the drain terminal of the first PMOS transistor MP1 is connected with the drain electrode of the first NMOS transistor MN1, and the source electrode of the first NMOS transistor MN1 passes through a resistor R_FThe grid electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected with the ground, the grid electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected with the output end of an operational amplifier, and the non-inverting input end of the operational amplifier is connected with a reference voltage V_REFAnd the inverting input end is connected with the source electrode of the first NMOS tube MN 1.

The further technical proposal is that the output frequency f_clkoutOnly with the capacitor C_FCapacitance value and resistance R_FIs related to the reference voltage V_REFIs irrelevant.

The further technical proposal is that the output frequency isWhere k is an inherent coefficient related to the circuit structure.

The further technical proposal is that the output frequency isWherein m is the current ratio of the first PMOS tube MP1 and the second PMOS tube MP2 in the current mirror, and the switch control circuit outputs the frequency f_clkoutAs the switching frequency of the two switches.

The beneficial technical effects of the invention are as follows:

the application discloses high accuracy frequency locking circuit based on negative feedback, this circuit is provided the input voltage of voltage-controlled oscillator by switch control circuit according to the output frequency regulation voltage output return circuit of the signal of output for voltage-controlled oscillator negative feedback adjusts the output frequency of the signal of output, thereby need not complicated compensating circuit and just can keep the output frequency of high accuracy and high stability.

The output frequency of the signal output by the high-precision frequency locking circuit is irrelevant to the reference voltage, so that only a rough reference voltage needs to be provided, and the requirement on the voltage precision is low. And the temperature drift of the output frequency is small because the parameters of the MOS tube changing along with the temperature change are not needed to be considered.

Drawings

Fig. 1 shows a circuit structure of a conventional oscillator.

Fig. 2 shows another conventional oscillator circuit structure.

Fig. 3 is a circuit configuration of the high-precision frequency locking circuit of the present application.

Fig. 4 is a circuit configuration diagram of the voltage controlled oscillator of fig. 3.

Fig. 5 is a circuit configuration diagram of the switch control circuit in fig. 3.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

Referring to fig. 3, the high-precision frequency locking circuit includes a voltage output loop, a voltage controlled oscillator, and a switch control circuit. In the voltage output circuit, a capacitor C_FThe negative electrode of the first switch is grounded, and the positive electrode of the first switch passes through the first switch S₁Is connected with a reference voltage terminal V_BCapacitor C₂The negative electrode of the transformer is grounded, and the positive electrode of the transformer is connected with a reference voltage end V_BCapacitor C_FAre connected in parallel with a second switch S₂Reference voltage terminal V_BIs connected to a power supply VDD and a capacitor C through a switching tube_FHas a capacitance value much smaller than that of the capacitor C₂。

The input end of the voltage-controlled oscillator is connected to the voltage output circuit to obtain input voltage, the output end of the voltage-controlled oscillator is used as the signal output end of the high-precision frequency locking circuit, and a signal V output by the signal output end_outOutput frequency f_clkoutInput voltage V to voltage controlled oscillator_CAnd (4) positively correlating. A circuit structure of a commonly used voltage-controlled oscillator is shown in fig. 4, and better linearity and output frequency f can be ensured by proper size selection_clkout＝dV_CAnd d is the gain factor of the voltage controlled oscillator.

First switch S₁And a second switch S₂Are complementary and do not overlap, the switch control circuit is based on the output frequency f_clkoutAdjusting the first switch S₁And a second switch S₂So that the input voltage V of the voltage controlled oscillator_CAnd an output frequency f_clkoutForm a pair of output frequencies f in negative correlation_clkoutNegative feedback regulation of (2).

In the present application, the first switch S₁And a second switch S₂One switching period is formed by alternately closing the two switches once, the closing time of the two switches in one switching period is equal, and the capacitor C₂Is decreased by Δ q ═ V in one switching cycle_BC_FSo that the equivalent sinking current of the reference voltage terminal isWhen the output frequency is increased, the switching frequency of the switch is increased, and the switching period T is increased_SReducing so that the reference voltage terminal V_BIs reduced, in turn, the input voltage V of the voltage-controlled oscillator_CReduce, drive the output frequency f_clkoutThe decrease stabilizes until a predetermined value is reached. When the output frequency f_clkoutWhen the frequency is reduced, the switching frequency of the switch is increased, and the switching period T is prolonged_SIncrease so that the reference voltage terminal V_BVoltage value rising, input voltage V of voltage controlled oscillator_CIncrease to drive the output frequency f_clkoutIncrease until reaching a predetermined value, thereby realizing output frequency f_clkoutNegative feedback regulation of (2).

Wherein the switch control circuit includes an N-frequency divider, referring to fig. 5, the switch control circuit outputs a signal V to the signal output terminal_outThe division by N is performed in conjunction with a logic circuit to generate control signals Ctrl1 and Ctrl2 for the two switches, Ctrl1 and Ctrl2 having a frequency ofWhereby the switch control circuit is in accordance withRespectively controls the on-off state of the two switches, the switching periodThe multiple N of the frequency division is preconfigured in the circuit design stage.

In the voltage output loop, specifically, referring to FIG. 3, the reference voltage terminal V_BThe source electrode of the second NMOS transistor MN2 is connected, the drain electrode of the second NMOS transistor MN2 is connected with the drain electrode of the second PMOS transistor MP2, the source electrode of the second PMOS transistor MP2 is connected with a power supply VDD, and the common end of the second PMOS transistor MP2 and the second NMOS transistor MN2 is connected with the input end of the voltage-controlled oscillator. The input end of the voltage-controlled oscillator is also connected with a compensation capacitor C₁。

The first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to form a current mirror, specifically, the source of MP1 is connected to the power VDD, and the drain and gate of MP1 are connected to the gate of MP 2. The drain terminal of the first PMOS transistor MP1 is connected to the drain terminal of the first NMOS transistor MN1, and the source terminal of the first NMOS transistor MN1 is connected to the drain terminal of the first PMOS transistor MP 8926 through a resistor R_FThe grid electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected with the ground, the grid electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected with the output end of an operational amplifier, and the non-inverting input end of the operational amplifier is connected with a reference voltage V_REFThe inverting input end is connected with the source electrode of the first NMOS tube MN1, namely V_AA voltage terminal.

Since the operational amplifier OP and the first NMOS transistor MN1 form negative feedback, V is generated_AThe voltage value of the voltage end is equal to the reference voltage. And the gate voltages of MN1 and MN2 are the same, so that V is equal_AVoltage terminal and reference voltage terminal V_BAre also equal and thus have a voltage of V_A＝V_B＝V_REF。

Current I flowing through MP1_MP1And through a resistor R_FCurrent of (I)_RFIs equal to, there areAssume that the current ratio of the first PMOS transistor MP1 to the second PMOS transistor MP2 in the current mirror is m, i.e. I_MP2＝mI_MP1The current ratio m is pre-configured at the circuit design stage. Thus the current flowing through MP2

Then during the negative feedback regulation, when the equivalent sinking currentCurrent of MP2When the output frequency f is consistent with the output frequency f_clkoutWhen the predetermined value is stable, the method comprisesBased on the structure of FIG. 3 and the switch control circuit of FIG. 5, there areV_B＝V_REFThus there areIt can be known thatThe current ratio is m and the frequency division multiple N is well configured in the circuit design stage, and the circuit structure can be considered as inherent. So that the output frequency can be knownWhere k is an inherent coefficient related to the circuit structure.

From the above expression, the output frequency f_clkoutOnly with the capacitor C_FCapacitance value and resistance R_FIs related by changing C_FAnd R_FThe output frequency f can be adjusted_clkout. Resistance R_FVariable resistors may be used, after the circuit structure is fixed, by adjusting R_FCan realize the output frequency f_clkoutAnd (4) adjusting. Due to the output frequency f_clkoutAnd a reference voltage V_REFIs irrelevant, so only a coarse reference voltage V needs to be provided_REFI.e. the requirements on voltage accuracy are lower. And the output frequency f_clkoutAnd the temperature drift of the output frequency is small because the parameters of the MOS tube changing along with the temperature change are not needed to be considered.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.