阅读说明：本技术 一种无Mesa台面的VCSEL芯片的制作方法 (Method for manufacturing VCSEL chip without Mesa ) 是由 袁章洁 李雪松 于 2021-06-24 设计创作，主要内容包括：本发明公开了一种无Mesa台面的VCSEL芯片的制作方法,涉及垂直腔面发射激光器技术领域。本发明的一种无Mesa台面的VCSEL芯片的制作方法,所述方法在量子阱生长完成后在量子阱表面沉积了一层光电限制层,然后对光电限制层进行光刻和刻蚀,定义出发光区域,所述光电限制层的材料为三氧化二铝。本发明的一种无Mesa台面的VCSEL芯片的制作方法,在整个生产过程中省去了传统的氧化或离子注入工艺,可以减少VCSEL芯片制备过程中设备的投入,同时缩短了整个工艺流程,能够有效缩短生产时间,提高生产效率,降低生产成本。(The invention discloses a method for manufacturing a VCSEL chip without a Mesa, and relates to the technical field of vertical cavity surface emitting lasers. The invention discloses a manufacturing method of a VCSEL chip without a Mesa, which is characterized in that a photoelectric limiting layer is deposited on the surface of a quantum well after the growth of the quantum well is finished, then the photoelectric limiting layer is subjected to photoetching and etching to define a light emitting region, and the photoelectric limiting layer is made of aluminum oxide. According to the manufacturing method of the VCSEL chip without the Mesa, the traditional oxidation or ion implantation process is omitted in the whole production process, the equipment investment in the VCSEL chip preparation process can be reduced, the whole process flow is shortened, the production time can be effectively shortened, the production efficiency is improved, and the production cost is reduced.)

1. A manufacturing method of a VCSEL chip without a Mesa is characterized in that a photoelectric limiting layer is deposited on the surface of a quantum well after the growth of the quantum well is completed, and then photoetching and etching are carried out on the photoelectric limiting layer to define a light emitting region.

2. The method of claim 1, wherein the material of the optical confinement layer is alumina.

3. The method of claim 2, wherein the optoelectronic confinement layer is deposited by magnetron sputtering or atomic layer deposition.

4. The method of claim 3, wherein the thickness of the optical confinement layer is 20-40 nm.

5. A method of fabricating a VCSEL chip without a Mesa according to any of claims 1 to 4, wherein the method of fabricating is specifically:

s1: providing a GaAs substrate;

s2: sequentially growing an N-DBR structure and a quantum well on the GaAs substrate;

s3: depositing a photoelectric limiting layer on the surface of the quantum well to obtain a pattern, etching the photoelectric limiting layer to form a through hole by etching, and defining a light emitting area;

s4: growing a P-DBR structure on the surface of the photoelectric limiting layer by using MOCVD;

s5: depositing and covering a silicon nitride layer on the surface of the P-DBR structure to be used as a protective film;

s6: etching an electrode position on the SiNx layer;

s7: evaporating P-contact on the P surface;

s8: bonding and binding the P surface of the wafer and the sapphire, and grinding and thinning the N surface;

s9: and (4) evaporating and plating an N-metal electrode on the N surface of the wafer, annealing and unbinding, and scribing to obtain the VCSEL chip.

6. The method of claim 5, wherein the step of S3 is specifically operated as follows: and (2) feeding the wafer with the quantum well grown in the step S2 into an RF magnetron sputtering machine, vacuumizing the RF magnetron sputtering machine, introducing argon and oxygen into the machine, controlling the sputtering pressure and sputtering power of the machine to deposit on the surface of the quantum well to obtain a photoelectric limiting layer, coating photoresist on the surface of the photoelectric limiting layer in a spinning mode, baking, exposing and developing to obtain a luminous zone pattern, etching the photoelectric limiting layer according to the luminous zone pattern by utilizing ICP (inductively coupled plasma) etching, etching a plurality of through holes on the photoelectric limiting layer, and cleaning and removing redundant photoresist after etching is finished.

7. The method as claimed in claim 6, wherein the flow rate of argon is 40-60ml/min, the flow rate of oxygen is 1-10ml/min, the sputtering pressure is 0.5-5pa, and the sputtering power is 70W.

8. The method as claimed in claim 6, wherein a positive photoresist is spin-coated when a light emitting region pattern is formed on the photoelectric confinement layer, the photoresist is coated at a rotation speed of 1200r/min and 800-.

9. The method of claim 6, wherein the IPC is etched with BCl₃The process gas flow is 50-100sccm, the process pressure is 0.5pa, the ICP power is 800-.

10. A method of fabricating a VCSEL chip without Mesa according to any of claims 6-9, wherein the via hole has a diameter of 8-12 μm.

Technical Field

The invention relates to the technical field of vertical cavity surface emitting lasers, in particular to a manufacturing method of a VCSEL chip without a Mesa.

Background

A vertical cavity surface emitting laser chip (VCSEL) is a semiconductor laser chip whose laser light is emitted perpendicularly to the top surface. The existing VCSEL chip is mainly prepared by growing an N-DBR layer, a quantum well, an oxidation layer and a P-DBR layer on a substrate in sequence by MOCVD (metal organic chemical vapor deposition), making P-metal ohmic contact through photoetching and coating film, protecting the coating film, making a chip mesa structure through photoetching and etching, feeding the chip mesa structure into an oxidation furnace to oxidize the oxidation layer to enable the chip to form photoelectric limitation, then coating an insulation film for protection, opening an electrode channel through photoetching and etching, making a seed layer, thickening the P-metal through photoetching and electroplating, finally opening a chip light outlet through wet etching, making a cutting channel for photoetching and etching, and finally grinding and shearing a thin wafer to make a back metal N-metal to complete the whole processing process. The VCSEL chip manufacturing process by the method is complicated in flow, 5-6 steps are needed for photoetching, the overall process is small, the process steps are about 70 steps in a large summary, a large amount of time is needed in the overall process, and more devices need to be purchased, so that the production cost is high.

Disclosure of Invention

In view of the above problems, the present invention is directed to a method for manufacturing a VCSEL chip without Mesa, which omits a conventional oxidation or ion implantation process in the whole production process, reduces the equipment investment in the VCSEL chip preparation process, shortens the whole process flow, effectively shortens the production time, improves the production efficiency, and reduces the production cost.

Specifically, according to the manufacturing method of the VCSEL chip without the Mesa, a photoelectric limiting layer is deposited on the surface of the quantum well after the quantum well grows, and then photoetching and etching are carried out on the photoelectric limiting layer to define a light emitting region.

Further, the photoelectric limiting layer is made of aluminum oxide.

Further, the photoelectric limiting layer is obtained by deposition through a magnetron sputtering or atomic layer deposition method.

Further, the thickness of the photoelectric limiting layer is 20-40 nm. Preferably 30 nm.

Further, the preparation method specifically comprises the following steps:

providing a GaAs substrate;

sequentially growing an N-DBR structure and a quantum well on the GaAs substrate;

depositing a photoelectric limiting layer on the surface of the quantum well to obtain a pattern, etching a through hole by using the etching photoelectric limiting layer, and defining a light emitting area;

growing a P-DBR structure on the surface of the photoelectric limiting layer by using MOCVD;

depositing and covering a silicon nitride layer on the surface of the P-DBR structure to be used as a protective film;

etching an electrode position on the SiNx layer;

evaporating P-contact on the P surface;

bonding and binding the P surface of the wafer and the sapphire, and grinding and thinning the N surface;

and (4) evaporating and plating an N-metal electrode on the N surface of the wafer, annealing and unbinding, and scribing to obtain the VCSEL chip.

Further, the step S3 is specifically operated as: and (2) feeding the wafer with the quantum well grown in the step S2 into an RF magnetron sputtering machine, vacuumizing the RF magnetron sputtering machine, introducing argon and oxygen into the machine, controlling the sputtering pressure and sputtering power of the machine to deposit on the surface of the quantum well to obtain a photoelectric limiting layer, coating photoresist on the surface of the photoelectric limiting layer in a spinning mode, baking, exposing and developing to obtain a luminous zone pattern, etching the photoelectric limiting layer according to the luminous zone pattern by utilizing ICP (inductively coupled plasma) etching, etching a plurality of through holes on the photoelectric limiting layer, and cleaning and removing redundant photoresist after etching is finished.

Further, the flow rate of the argon is 40-60ml/min, the flow rate of the oxygen is 1-10ml/min, the sputtering pressure during sputtering is 0.5-5pa, and the sputtering power is 70W.

Further, when a luminous zone pattern is formed on the photoelectric limiting layer, positive photoresist is spin-coated, and during gluing, glue is uniformly coated at the rotation speed of 800 plus one square meter/min and the rotation speed of 1200r/min for 20-60s, the baking temperature is 80-120 ℃, the time is 60-120s, the exposure energy is 80mj/c square meter, and the exposure time is 15-45 s.

Further, the diameter of the through hole is 8-12 μm.

Further, the N-DBR structure comprises 30 pairs of Ga materials_0.1Al_0.9As/Ga_0.9Al_0.1A DBR layer of As, the P-DBR structure comprises 22 pairs of Ga_0.1Al_0.9As/Ga_0.9Al_0.1DBR layer of As.

The invention has the beneficial effects that:

1. the invention discloses a method for manufacturing a VCSEL chip without a Mesa, wherein aluminum oxide is directly deposited to form a photoelectric limiting layer in the process of substrate growth.

2. The method for manufacturing the VCSEL chip does not need to be oxidized, so that the core particles do not need to be manufactured into a mesa structure, and the surface of the whole wafer is flat because the mesa structure is not arranged, so that the whole wafer is relatively easy to process, and the requirements on a machine table are lower than those of the traditional process.

3. The VCSEL chip prepared by the preparation method of the invention has no mesa structure, so that the electrical parasitic parameters of the whole core particles can be reduced, and the electrical parasitic parameters are also the main limiting factors of VCSEL high-speed modulation, so that the VCSEL chip processed by the process has higher modulation frequency, and the high-speed VCSEL chip can be manufactured.

Drawings

Fig. 1-6 are schematic structural diagrams corresponding to steps in a method for manufacturing a VCSEL chip without Mesa according to the present invention;

FIG. 7 is an SEM image of a VCSEL chip prepared according to an embodiment of the present invention;

FIG. 8 is an SEM image of a VCSEL chip prepared by a conventional method in a comparative example;

the semiconductor structure comprises a GaAs substrate 1, an N-DBR structure 2, a quantum well 3, a photoelectric limiting layer 4, a through hole 5, a P-DBR structure 6, a silicon nitride layer 7, a groove 8, a P-contact 9 and an N-metal electrode 10.

Detailed Description

The present invention will be described in detail with reference to specific examples below:

examples

S1: providing a GaAs substrate 1;

s2: using MOCVD to overgrow 30 pairs of Ga on the GaAs substrate 1 by a conventional method_0.1Al_0.9As/Ga_0.9Al_0.1Obtaining N-DBR structures 2 by using the DBR layers of As, wherein the thickness of each DBR layer is 1/4 lasing wavelength, and quantum wells 3 made of InGaAs/AlGaAs are obtained by growing on the surfaces of the N-DBR structures 2;

s3: directly feeding the wafer with quantum well grown in the step S2 into RF radio frequency magnetControlling the sputtering machine, using alpha-Al 2O3 as a target material, and pumping the vacuum degree in the machine to 10 × E^-3pa, introducing argon gas at a flow rate of 40-60ml/min into an RF (radio frequency) magnetron sputtering machine, introducing oxygen at a flow rate of 1-10ml/min, controlling the sputtering pressure of the machine to be 0.5-5pa, and obtaining a photoelectric limiting layer 4 which is 30nm thick and is made of aluminum oxide on the surface of the quantum well 3 by magnetron sputtering with sputtering power of 70W, as shown in figure 1;

spin-coating positive photoresist on the surface of the photoelectric limiting layer 4 obtained by sputtering, spin-coating at the rotation speed of 800-1200r/min for 20-60s, baking at the temperature of 80-120 ℃ for 60-120s, exposing at the exposure energy of 80mj/c for 15-45s, spin-coating developing solution at the rotation speed of 800-1000r/min for developing to obtain light emitting region patterns, wherein the diameter of each small light emitting region is 8-12 μm, each 100 light emitting regions are formed into an array, performing ICP etching, selecting BCl3 as process gas, the flow rate is 50-100sccm, the process pressure is 0.5pa, the ICP power is 800-1200W, and the bias power is 200-400W, etching a plurality of through holes 5 with the diameter of 8-12 μm on the photoelectric limiting layer 4, and (3) immediately etching a light emitting region to realize the intercommunication of P-surface and N-surface circuits and define the light emitting region, timely finding an etching end point by monitoring the change of Ai element closing lines during etching to prevent over-etching, and cleaning by using an organic solvent to remove redundant photoresist after the etching is finished to obtain the photoresist shown in figure 2.

S4: using MOCVD, 22 pairs of Ga are grown on the surface of the photoelectric confinement layer 4 in an overlapping manner by the conventional method_0.1Al_0.9As/Ga_0.9Al_0.1The DBR layer of As to obtain a P-DBR structure 6, wherein the thickness of each DBR layer is 1/4 lasing wavelength, and a highly carbon-doped GaAs layer is grown on the uppermost layer, and the doping concentration can reach 1 × 10²⁰/㎝³So as to facilitate the subsequent ohmic contact of the electrode, as shown in FIG. 3;

s5: depositing and covering a silicon nitride layer 7 on the surface of the P-DBR structure 6 by using a PECVD (plasma enhanced chemical vapor deposition) method by adopting a conventional method as a protective film so as to protect the whole wafer;

s6: patterning the silicon nitride layer 7 by photolithography, etching an annular groove 8 in the silicon nitride layer by etching, and removing photoresist after etching is completed, as shown in fig. 4;

s7: and photoetching again, making photoresist shielding on a light-emitting region, then evaporating P-metal on a P surface by electron beam evaporation, and stripping the excessive photoresist and the metal by using Lift-off to form P-contact 9, as shown in FIG. 5.

S8: bonding and binding the P surface of the wafer and the sapphire, grinding and thinning the N surface, wherein the specific thickness can be selected according to actual needs;

s9: and (3) evaporating and plating an N-metal electrode 10 on the N surface of the wafer, annealing and unbinding, and scribing to obtain the VCSEL chip.

Comparative example

The comparative example adopts the existing preparation method of the Vcsel chip, and specifically comprises the following steps:

s1: providing a GaAs substrate;

s2: sequentially growing an N-DBR structure, a quantum well, an oxide layer and a P-DBR structure in an overlapping manner on the GaAs substrate;

s3: p-metal photoetching is carried out on the wafer, then metal is deposited through electron beam evaporation to form P-contact, and the wafer is sent to a metal stripping cleaning machine to strip redundant metal.

S4: the wafer is sent to a PECVD machine to deposit a silicon nitride protection layer.

S5: and continuing to send the wafer to yellow light for mesa photoetching.

S6: etching the P-DBR structure to expose the oxide layer, oxidizing the oxide layer by wet oxidation process to reach photoelectric limit effect and define light emitting region,

s7: the wafer is again fed into the PECVD to deposit silicon nitride.

S8: and (3) sending the wafer to yellow light again, finishing the planarization of the wafer in the yellow light, spin-coating BCB on the wafer, exposing and developing the BCB to enable the surface of the wafer to be relatively flat, and finally baking and hardening the film to finish the planarization of the BCB.

S9: and after the VIA photoetching of the channel above the electrode ring is completed by photoetching again, conveying the wafer to an etching room, and etching silicon nitride above the P-contact metal.

S10: and magnetron sputtering to form a seed layer of Au metal on the whole wafer.

S11: and (4) carrying out photoetching on the wafer, continuing to carry out metal thickening photoetching, keeping the photoresist in the light-emitting area, and exposing the rest parts.

S12: plating Au thickened wafer connecting metal on the wafer, then adopting organic photoresist removal, and then etching the seed layer metal in the light emitting region by a wet method.

S13: the wafer is again photo-etched and then etched, and each core grain on the surface of the wafer is etched and separated.

S14: bonding and binding the P surface of the wafer and the sapphire, grinding and thinning the N surface, wherein the specific thickness can be selected according to actual needs;

s15: and (4) evaporating and plating an N-metal electrode on the N surface of the wafer, annealing and unbinding, and scribing to obtain the VCSEL chip.

Through comparison between the comparative example and the embodiment, it is obvious that the operation steps of the preparation method are greatly reduced, the whole process does not use oxidation or ion implantation process, the whole process of the preparation method only needs 3 times of photoetching, 2 times of etching, 1 time of PECVD coating, 2 times of metal coating, 1 time of magnetron sputtering or atomic deposition coating to complete the whole process, while the preparation of the VCSEL chip with the traditional Mesa structure in the comparative example usually needs 5-6 times of photoetching, 4-5 times of etching, 2-4 times of PECVD coating and 3 times of metal coating, so that the preparation method can greatly shorten the chip processing process flow, save the manufacturing time and reduce the production cost, and the VCSEL chip prepared by the preparation method disclosed by the invention has a flat surface and no Mesa Mesa can be seen through figures 7 and 8.

Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims. The techniques, shapes, and configurations not described in detail in the present invention are all known techniques.