阅读说明：本技术 一种半导体芯片的制作方法及激光器 (Manufacturing method of semiconductor chip and laser ) 是由 郑兆祯 吴阳烽 焦旺 王菊 廖桂波 丁新琪 涂庆明 于 2020-05-22 设计创作，主要内容包括：本申请公开了一种半导体芯片的制作方法以及激光器,该方法包括：提供一具有初步锌扩散的外延片；在外延片的至少部分表面沉积应变层,以使得半导体芯片的发射光谱发生蓝移,其中,至少部分表面包括窗口区；对外延片与应变层进行加热,以提高锌在窗口区的扩散；其中,在加热后应变层的薄膜应变大于加热前的薄膜应变。通过上述方式,本申请能够加速锌的扩散,提升生产效率,提高抗灾变性光学镜面损伤的能力。(The application discloses a manufacturing method of a semiconductor chip and a laser, wherein the method comprises the following steps: providing an epitaxial wafer with preliminary zinc diffusion; depositing a strain layer on at least part of the surface of the epitaxial wafer to enable the emission spectrum of the semiconductor chip to generate blue shift, wherein at least part of the surface comprises a window region; heating the epitaxial wafer and the strain layer to improve the diffusion of zinc in the window region; wherein the film strain of the strained layer after heating is greater than the film strain before heating. By means of the mode, the diffusion of zinc can be accelerated, the production efficiency is improved, and the capability of resisting damage of the optical mirror surface is improved.)

1. A method for manufacturing a semiconductor chip, comprising:

providing an epitaxial wafer with preliminary zinc diffusion;

depositing a strain layer on at least part of the surface of the epitaxial wafer to enable the emission spectrum of the semiconductor chip to generate blue shift, wherein the at least part of the surface comprises a window region;

heating the epitaxial wafer and the strain layer to improve the diffusion of zinc in a window region;

wherein the film strain of the strained layer after heating is greater than the film strain before heating.

2. The method of claim 1, wherein the step of depositing a strain layer on at least a portion of the surface of the epitaxial wafer is preceded by the steps of:

preparing an undoped epitaxial wafer;

forming a mask layer on a non-window area of the epitaxial wafer;

and sequentially forming an active layer and a silicon dioxide layer on the mask layer and the epitaxial wafer which is not covered by the mask layer, and heating at a preset temperature or carrying out rapid thermal annealing for a preset time.

3. The method of fabricating a semiconductor chip according to claim 2, further comprising:

heating the epitaxial wafer, the mask layer, the active layer and the silicon dioxide layer to perform preliminary zinc diffusion;

and removing the silicon dioxide layer, the active layer and the mask layer in sequence to form an epitaxial structure with preliminary zinc diffusion.

4. The method of manufacturing a semiconductor chip according to claim 2,

the preset temperature is 580-620 ℃, the preset time is 25-30 minutes, and the thickness of the active layer is 150-250 nm; the thickness of the strain layer is 450-550 nm, and the material of the strain layer comprises silicon dioxide or silicon nitride.

5. The method of manufacturing a semiconductor chip according to claim 1,

and depositing the strain layer on at least part of the window area by adopting a plasma enhanced chemical vapor deposition method.

6. The method of claim 1, wherein the step of providing an epitaxial wafer comprises:

providing an N-type substrate;

sequentially epitaxially growing an N-type covering layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a P-type covering layer and a P-type contact layer on the N-type substrate to form the epitaxial wafer;

wherein, the material of the active layer comprises silicon dioxide and zinc oxide.

7. The method for manufacturing the semiconductor chip as claimed in claim 6, wherein the step of epitaxially growing an N-type cladding layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a P-type cladding layer and a P-type contact layer on the N-type substrate in sequence to form the epitaxial wafer comprises:

epitaxially growing the N-type cladding layer, the first waveguide layer, the quantum well layer, the second waveguide layer and the P-type cladding layer on the N-type substrate in sequence;

and doping zinc in the second waveguide layer and the P-type covering layer to obtain a new second waveguide layer and a new P-type covering layer, and forming the P-type contact layer on the new P-type covering layer.

8. The method of manufacturing a semiconductor chip according to claim 6,

the N-type substrate, the N-type covering layer, the quantum well layer, the P-type covering layer and the P-type contact layer are made of N-type gallium arsenide, N-type aluminum indium phosphide, gallium indium phosphide, P-type aluminum indium phosphide and P-type gallium arsenide respectively, and the first waveguide layer and the second waveguide layer are made of aluminum gallium indium phosphide.

9. The method of manufacturing a semiconductor chip according to claim 8,

the thickness of the N-type covering layer is 500-5000 nm; the thickness of the first waveguide layer is 50-250 nm; the thickness of the quantum well layer is 2-200 nm; the thickness of the second waveguide layer is 50-250 nm; the thickness of the P-type covering layer is 500-5000 nm; the thickness of the P-type contact layer is 100-500 nm.

10. A laser comprising a semiconductor chip manufactured by the manufacturing method according to any one of claims 1 to 9.

Technical Field

The application relates to the technical field of laser, in particular to a manufacturing method of a semiconductor chip and a laser.

Background

The research focus of semiconductor lasers includes increasing Optical output power, reliability, and operating life, etc., and Catastrophic Optical mirror Damage (COD) is an important factor affecting the maximum output power and reliability of semiconductor lasers.

At present, the mainstream method adopted for increasing the COD threshold is to reduce the light absorption of the cavity surface, and the basic method is to increase the band gap width of the cavity surface region, that is, the commonly-known window structure, and the specific implementation method includes the following steps: firstly, epitaxial regrowth is carried out, materials in the area near the cavity surface are corroded, then a wide-band-gap material is epitaxially grown again, a transparent window for outputting light is formed, and light absorption is reduced, and the defects that the process is complex, the cost is high, and poor crystal quality of a joint part and reduction of the working efficiency of a device are possibly caused, so that the performance of the device is influenced; and secondly, quantum well intermixing, because each layer of the epitaxial wafer is a metastable state interface, the quantum well component atoms in the cavity surface region can be diffused mutually by the quantum intermixing technology, so that the band gap width of the corresponding non-window region is increased.

However, the problems that the existing zinc atom diffusion improves the band gap width of a window region are as follows: although the diffusion of zinc atoms to the quantum well layer requires a short time (about 30 minutes), the thickness of the quantum well layer is about 10nm, and the completion of atomic mixing by only depending on zinc induction requires 1-3 hours, so the total doping time is long, and the process production is not facilitated; in addition, doping needs to be carried out in a high-temperature environment all the time, and long-time high-temperature treatment can increase the transverse or longitudinal diffusion of zinc, seriously affect the atomic purity of an active region and reduce the light-emitting efficiency of the laser.

Disclosure of Invention

The application provides a manufacturing method of a semiconductor chip and a laser, which can accelerate the diffusion of zinc, improve the production efficiency and improve the capability of resisting the damage of a disaster-resistant optical mirror surface.

In order to solve the technical problem, the technical scheme adopted by the application is as follows: provided is a method for manufacturing a semiconductor chip, the method including: providing an epitaxial wafer with preliminary zinc diffusion; depositing a strain layer on at least part of the surface of the epitaxial wafer to enable the emission spectrum of the semiconductor chip to generate blue shift, wherein at least part of the surface comprises a window region; heating the epitaxial wafer and the strain layer to improve the diffusion of zinc in the window region; wherein the film strain of the strained layer after heating is greater than the film strain before heating.

In order to solve the technical problem, the technical scheme adopted by the application is as follows: the laser comprises a semiconductor chip, and the semiconductor chip is manufactured by the manufacturing method.

Through the scheme, the beneficial effects of the application are that: the strain layer capable of increasing the diffusion of zinc atoms is deposited on the epitaxial wafer, the diffusion of the zinc atoms is accelerated by heating the epitaxial wafer and the strain layer, the strain layer can generate film strain at high temperature, the film strain can accelerate the diffusion of the zinc atoms, the diffusion time of the zinc atoms can be shortened, the production efficiency is promoted, and the energy band gap of a window region after the diffusion is enlarged, so that the blue shift of the light-emitting wavelength of the semiconductor chip is realized, and the anti-COD capability of the semiconductor chip can be further improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor chip according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of the structure of the semiconductor chip in the embodiment shown in FIG. 1;

FIG. 3 is a schematic flow diagram of the preliminary zinc diffusion carried out in the embodiment shown in FIG. 1;

FIG. 4 is a schematic diagram of the structure corresponding to step 22 in the embodiment shown in FIG. 3;

FIG. 5 is a schematic structural diagram corresponding to step 23 in the embodiment shown in FIG. 3;

FIG. 6 is a schematic structural diagram corresponding to step 12 in the embodiment shown in FIG. 1;

FIG. 7 is another schematic diagram of the embodiment shown in FIG. 1 corresponding to step 12;

FIG. 8 is a schematic diagram of another structure corresponding to step 12 in the embodiment shown in FIG. 1;

FIG. 9 is a schematic wavelength diagram of a semiconductor chip during fabrication in the embodiment shown in FIG. 1;

fig. 10 is a schematic structural diagram of an embodiment of a laser provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1 to fig. 3, fig. 1 is a schematic flow chart illustrating a manufacturing method of a semiconductor chip according to an embodiment of the present disclosure, the method including:

step 11: an epitaxial wafer with preliminary zinc diffusion is provided.

As shown in fig. 2, the epitaxial wafer 11 includes an N-type substrate 111, an N-type cladding layer 112, a first waveguide layer 113, a quantum well layer 114, a second waveguide layer 115, a P-type cladding layer 116, and a P-type contact layer 117, which are sequentially arranged, the N-type cladding layer 112 and the P-type cladding layer 116 may be N-type aluminum indium phosphide and P-type aluminum indium phosphide, respectively, the quantum well layer 114 may be indium gallium phosphide, the P-type contact layer 117 may be P-type gallium arsenide, and the first waveguide layer 112 and the second waveguide layer 115 may be indium aluminum gallium phosphide.

In order to realize the diffusion of the zinc atoms into the epitaxial wafer 11, the fabricated epitaxial wafer 11 may be utilized to diffuse the zinc atoms into the epitaxial wafer 11 by means of ion implantation, atom doping or diffusion, or directly fabricate the epitaxial wafer 11 with zinc atom diffusion, specifically, an N-type substrate 111 may be provided first, and then an N-type cladding layer 112, a first waveguide layer 113, a quantum well layer 114, a second waveguide layer 115, a P-type cladding layer 116 and a P-type contact layer 117 are sequentially epitaxially grown on the N-type substrate 111 to form the epitaxial wafer 11, the material of the N-type substrate 111 may be N-type gallium arsenide, which may play a role in support.

It should be noted that the epitaxial wafer may be prepared by a process well-established in the art, and will not be described herein.

Step 12: and depositing a strain layer on at least part of the surface of the epitaxial wafer so as to enable the emission spectrum of the semiconductor chip to generate blue shift.

The at least part of the surface comprises a window area, wherein the window area is an area needing to increase the band gap width and is generally arranged at the light-emitting end of the semiconductor chip; as shown in fig. 2, after forming the epitaxial wafer 11, in order to further enhance the zinc diffusion, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method may be used to deposit a strained layer 12 on at least a portion of the surface of the epitaxial wafer 11, the thickness of the strained layer 12 may be 450 to 550nm, and the material of the strained layer 12 may include silicon dioxide or silicon nitride.

Because the strain layer 12 capable of increasing the diffusion of zinc atoms is deposited in the window area with the band gap width needing to be increased, the strain layer 12 generates film strain at high temperature, and the film strain can accelerate the mixing of the zinc atoms in the window area, so that the blue shift of the light-emitting wavelength can be realized after the optimal deposition process of the strain layer 12 is finished, the band gap of the window area is widened, and the anti-COD capability of the cavity surface of the semiconductor chip is further improved; specifically, impurities are diffused to an active layer near the end face of the semiconductor chip to form a disorder area, the disorder area is used as a window area, exciting light is used for irradiating the window area, the wavelength of photoluminescence of the window area is measured, the difference between the wavelength of the photoluminescence generated when the active layer without the window area is irradiated by the light and the wavelength of the photoluminescence of the window area is defined as a blue shift amount, the COD level of a product is predicted according to the blue shift amount of each stage in the technological process, and the larger the blue shift amount is, the more obvious the improvement of the anti-COD capability of the semiconductor chip is.

Step 13: and heating the epitaxial wafer and the strain layer to improve the diffusion of zinc in the window area.

Although there is some diffusion of zinc atoms already during the deposition of the strained layer 12, complete diffusion mixing of the source layer has not yet been achieved, so in order to allow faster complete diffusion of zinc atoms, the epitaxial wafer 11 on which the strained layer 12 is deposited may be heated; specifically, due to the difference of the thermal expansion coefficients between the strain layer 12 and the epitaxial wafer 11, the film strain of the strain layer 12 is increased by heating the composite structure of the semiconductor chip (including the epitaxial wafer 11 and the strain layer 12), so that the film strain of the strain layer 12 after heating is larger than that before heating, and the film strain can accelerate the diffusion of zinc atoms in the active layer of the window region, thereby maximally saving the process time; in addition, due to the rapid induction effect of the film strain, the atom mixing of the active layer in the window region can be completed in a short time, the transverse and longitudinal ineffective diffusion of zinc atoms in the heating process can be further reduced, and the influence of zinc impurities on the luminous efficiency is further reduced.

This embodiment provides a novel processing technology, plates strain layer 12 on the at least partial surface of epitaxial wafer 11, and strain layer 12 can accelerate the induced atomic mixture who accomplishes the window district of zinc, reduces semiconductor chip's preparation time, improves production efficiency, moreover because the blue-shift of luminous wavelength, can improve semiconductor chip's anti COD ability.

In a specific embodiment, illustrated in FIG. 3, preliminary zinc diffusion may also be performed prior to the deposition of strained layer 12 using steps 21-24, as described below with respect to the specific embodiment:

step 21: an undoped epitaxial wafer was prepared.

The epitaxial wafer includes an N-type substrate 111, an N-type cladding layer 112, a first waveguide layer 113, a quantum well layer 114, a second waveguide layer 115, a P-type cladding layer 116, and a P-type contact layer 117.

Further, the N-type substrate 111 is an N-type GaAs single crystal wafer; the N-type cladding layer 112 is N-type undoped Al matched with N-type GaAs_xIn_1-xP, the thickness of which is 500-5000 nm; the first waveguide layer 113 is N-type undoped (Al)_yGa_1-y)_xIn_1-xP, the thickness of which is 50-250 nm; the quantum well layer 114 is Ga_zIn_1-zP, the thickness of which is 2-200 nm, and the lasing wavelength is 620-670 nm; the second waveguide layer 115 is P-type (Al)_yGa_1-y)_xIn_1-xP, the thickness of which is 50-250 nm; the P-type cladding layer 116 is P-type Al_xIn_1-xP, the thickness of which is 500-5000 nm; the P-type contact layer 117 is P-type undoped GaAs with a thickness of 100-500 nm.

Step 22: and forming a mask layer on the non-window area of the epitaxial wafer.

As shown in fig. 4, after forming the epitaxial wafer 11, a mask layer 13 may be formed in the window region, and the mask layer 13 may be made of silicon nitride and may have a thickness of 250 nm.

Step 23: and sequentially forming an active layer and a silicon dioxide layer on the mask layer and the epitaxial wafer which is not covered by the mask layer, and heating at a preset temperature or carrying out rapid thermal annealing for a preset time.

As shown in fig. 5, after the mask layer 13 is formed, an active layer 14 may be formed on the entire surface of the current structure, and then a silicon dioxide layer 15 may be formed on the active layer 14, where the material of the active layer 14 includes silicon dioxide and zinc oxide, the thickness of the active layer 14 may be 150 to 250nm, such as 200nm, the preset temperature may be 580 to 620 ℃, and the preset time may be 25 to 30 minutes, for example, the active layer may be heated in a 600 ℃ furnace or subjected to preliminary zinc atom diffusion for 30 minutes under RTA (Rapid Thermal Annealing).

Specifically, in order to accelerate the diffusion of zinc atoms preliminarily, the manufactured structure (including the epitaxial wafer 11, the mask layer 13, the active layer 14 and the silicon dioxide layer 15) can be subjected to heating treatment, so that the preliminary zinc diffusion process is completed, and the zinc atoms can be diffused into the epitaxial wafer 11 through the window region due to the rapid diffusion of the zinc atoms, so that the band gap width of the non-window region is increased, but the zinc atoms cannot completely enter the quantum well layer 114 due to the fact that the zinc atoms cannot completely enter the quantum well layer in a short time due to the diffusion, so that the zinc atoms need to be diffused for the second time, namely, the strain layer 12 is deposited to further diffuse the zinc atoms, so that the zinc atoms can fully enter the quantum well layer 114.

Step 24: and removing the silicon dioxide layer, the active layer and the mask layer in sequence to form an epitaxial structure with preliminary zinc diffusion.

After heating, the mask layer 13, the active layer 14 and the silicon dioxide layer 15 are removed, and the epitaxial structure 11 'after preliminary diffusion is obtained, wherein zinc atoms in the epitaxial structure 11' do not enter the quantum well layer 114 or do not completely enter the quantum well layer 114.

In a specific embodiment, the preliminary zinc diffusion may be performed in the manner shown in fig. 3, and then the strained layer 12 may be deposited on the entire surface of the epitaxial structure 11', as shown in fig. 6, and the thickness of the strained layer 12 may be 500 nm. Complete diffusion of zinc atoms is accomplished by heating the epitaxial structure 11' on which the strained layer 12 is deposited; specifically, due to the difference of the thermal expansion coefficients between the strain layer 12 and the epitaxial structure 11', the film strain of the strain layer 12 is increased by heating the composite structure (including the epitaxial structure 11' and the strain layer 12) of the semiconductor chip, so that the film strain of the strain layer 12 after heating is larger than that before heating, and the film strain can accelerate the diffusion of zinc atoms in the active layer of the window region, thereby maximally saving the process time; in addition, due to the rapid induction effect of the film strain, the atom mixing of the active layer in the window region can be completed in a short time, the transverse and longitudinal ineffective diffusion of zinc atoms in the heating process can be further reduced, and the influence of zinc impurities on the luminous efficiency is further reduced.

Compared with the prior art, the accumulation layer (comprising the mask layer 13, the active layer 14 and the silicon dioxide layer 15) is removed after the preliminary diffusion, and the strain layer 12 capable of increasing the diffusion of zinc atoms is deposited, so that the COD resistance of the cavity surface of the semiconductor chip is improved, and the influence of zinc on the luminous efficiency of the semiconductor chip can be maximally reduced on the basis of further reducing the mixing time of the zinc atoms.

In another specific embodiment, as shown in fig. 7, unlike the embodiment shown in fig. 6, there are: the present embodiment deposits the strained layer 12 on the surface of the epitaxial wafer corresponding to at least a portion of the window region, and specifically, may deposit the strained layer 12 on the surface corresponding to the window region having the preliminary zinc diffusion. In this embodiment, the band gap width can be increased by depositing the strained layer 12 in the window region of the epitaxial structure 11', that is, increasing the diffusion of zinc atoms in the active layer of the window region during the heating process, thereby increasing the disorder of the active layer.

In the above embodiment, in the process of preparing the epitaxial wafer, a material process with an undoped layer structure is adopted, but it can be understood that, in the epitaxial wafer of the present application, the epitaxial structure 11' with zinc atoms can also be directly prepared in a pre-doping manner, and a specific process flow is described, that is, in the process of preparing the epitaxial wafer, zinc doping is performed on the P-type cap layer 116, and leakage of electrons can be improved by doping, so that photoelectric conversion efficiency is provided, but the doped zinc atoms exist in a non-window region at this time, and in order to increase mixing of zinc atoms in the window region in the quantum well layer 114, the strain layer 12 is deposited in a region where a band gap width needs to be increased, so that zinc atoms in the P-type cap layer 116 are rapidly diffused, and atoms in the window region are sufficiently mixed.

Further, an N-type cladding layer 112, a first waveguide layer 113, a quantum well layer 114, a second waveguide layer 115, and a P-type cladding layer 116 may be epitaxially grown on the N-type substrate 111 in sequence; then zinc is doped into the second waveguide layer 115 and the P-type cladding layer 116 to obtain a new second waveguide layer 115' with doped characteristics and a new P-type cladding layer 116', and a P-type contact layer 117 is formed on the new P-type cladding layer 116', as shown in fig. 8, and then a strained layer 12 is deposited on at least part of the window region on the P-type contact layer 117.

Further, in the present embodiment, the N-type substrate 111 is an N-type GaAs single crystal wafer; the N-type cladding layer 112 is N-type undoped Al matched with N-type GaAs_xIn_1-xP, the thickness of which is 500-5000 nm; the first waveguide layer 113 is N-type undoped (Al)_yGa_1-y)_xIn_1-xP, the thickness of which is 50-250 nm; the quantum well layer 114 is Ga_zIn_1-zP, the thickness of which is 2-200 nm, and the lasing wavelength is 620-670 nm; the second waveguide layer 115 is P-type (Al)_yGa_1-y)_xIn_1-xP with a thickness of 50-250 nm, the new second waveguide layer 115' being doped with a dopant material, ZnThe concentration is 5X 10¹⁷cm^-3(ii) a The new P-type cladding layer 116' is P-type Al_xIn_1-xP with a thickness of 500-5000 nm, the new P-type cladding layer 116' has a doping material, the doping material is Zn with a doping concentration of 3 × 10¹⁸cm^-3(ii) a The P-type contact layer 117 is P-type undoped GaAs with a thickness of 100-500 nm.

Compared with the prior art, the new second waveguide layer 115 'and the new P-type cladding layer 116' are subjected to zinc atom doping treatment, the strain layer 12 capable of increasing zinc atom diffusion is deposited in the window region where the band gap width needs to be increased, and the film strain is generated at high temperature in the strain layer 12, so that the mixing of zinc atoms in the window region can be accelerated by the film strain, and the anti-COD capability of the cavity surface of the semiconductor chip is further improved.

For a high-power semiconductor chip, a wide bandgap window region can be manufactured by using a wavelength blue shift effect, which can reduce the absorption of cavity surface light, so that the wavelength blue shift is also used for judging the anti-COD capability of the semiconductor chip to a certain extent, the difference between the wavelength of photoluminescence emitted when laser irradiates an unordered (non-doped) active layer and the wavelength of photoluminescence with the window region is defined as a blue shift amount, and the relationship shown in fig. 9 is obtained after summarizing and collating the test data of different samples.

Fig. 9 shows a blue shift of the wavelength of the semiconductor chip of this embodiment during the manufacturing process, wherein the curve (i), the curve (ii), and the curve (iii) correspond to the semiconductor chips having the same structure, respectively, but only the samples with partially changed manufacturing conditions; the curve I is the wavelength distribution of the window area measured when the semiconductor chip is not subjected to zinc diffusion treatment, the curve II is the wavelength distribution of the window area measured after the semiconductor chip is subjected to primary short-time zinc diffusion, the blue shift of the wavelength of about 10-15 nm is carried out compared with the curve I, the band gap of the window area of the semiconductor chip is widened, the semiconductor chip has certain COD resistance, the curve III is the wavelength distribution of the window area measured after the semiconductor chip is added with the strain layer 12 and subjected to thermal strain treatment, the blue shift of the wavelength of about 25-30 nm is carried out compared with the curve 1, the COD resistance of the semiconductor chip is obviously improved, and in sum, in the same set of samples, the shorter the wavelength of photoluminescence, the higher the COD level, which can be explained by the fact that after the window region has been disordered, the band gap is widened and the light absorbed near the end face of the resonator is reduced.

In fig. 9, when COD level is denoted as Pcod (mw) and photoluminescence wavelength of the window region is denoted as λ, then Pcod and λ have a linear proportional relationship, that is:

Pcod＝f*λ

in the above formula, f is a linear function.

From the above, it is understood that the photoluminescence wavelength λ of the semiconductor chip having Pcod is selected, and the value is used as an index, and whether the semiconductor chip is good or not can be discriminated by the COD level at the time of forming the window region. Further, by measuring the wavelength λ of photoluminescence of the window region, a highly reliable semiconductor chip resistant to COD degradation by the effect of the window region is manufactured with small dispersibility and high yield.

Further referring to fig. 9, a semiconductor chip having a window region such that a wavelength of photoluminescence is 600nm or less can be obtained by forming a semiconductor chip having a window region in a semiconductor chip having an active layer with a lasing wavelength of 590nm to 630nm, with a photoluminescence curve of a window region of a sample of the same semiconductor structure by a different process, and a COD level can be improved at least by the function of the window region.

Referring to fig. 10, fig. 10 is a schematic structural diagram of an embodiment of a laser provided in the present application, in which the laser 20 includes a semiconductor chip 21, and the semiconductor chip 21 is a semiconductor chip manufactured by the manufacturing method in the above embodiment.

The semiconductor chip 21 of the present embodiment is manufactured by accelerating the diffusion of zinc atoms in the window region, and can improve the COD resistance of the cavity surface of the semiconductor chip 21.

The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.