阅读说明：本技术 数字调制雷达发射器模块、系统和方法 (Digital modulation radar transmitter module, system and method ) 是由 加思特沃·A·G·阿里斯蒂贾巴尔 拉尔夫·罗伊特 迈克·布雷特 于 2020-10-28 设计创作，主要内容包括：本发明公开一种数字调制雷达DMR发射器模块,包括：序列产生器,其被配置成基于相对低频时钟信号产生重复数字序列信号；混频器,其被配置成组合所述数字序列信号与所述数字序列信号的至少一个相位延迟副本,以提供组合信号；以及调制器,其被配置成取决于所述组合信号而调制相对高频载波信号以提供调制信号。本发明还公开了对应的系统和方法。(The invention discloses a digital modulation radar DMR transmitter module, comprising: a sequence generator configured to generate a repeating digital sequence signal based on a relatively low frequency clock signal; a mixer configured to combine the digital sequence signal with at least one phase-delayed copy of the digital sequence signal to provide a combined signal; and a modulator configured to modulate a relatively high frequency carrier signal dependent on the combined signal to provide a modulated signal. The invention also discloses a corresponding system and a corresponding method.)

1. A digital modulated radar DMR transmitter module, comprising:

a sequence generator configured to generate a repeating digital sequence signal based on a relatively low frequency clock signal;

a mixer configured to combine the digital sequence signal with at least one phase-delayed copy of the digital sequence signal to provide a combined signal; and

a modulator configured to modulate a relatively high frequency carrier signal dependent on the combined signal to provide a modulated signal.

2. The DMR transmitter module of claim 1, further comprising:

one or more phase delay circuits, each phase delay circuit configured to receive the digital sequence signal as an input and to provide a respective one of the at least one phase delayed copies of the digital sequence signal to the mixer, the respective one of the at least one phase delayed copies being delayed in phase by a respective predetermined phase shift.

3. The DMR transmitter module of claim 1, further comprising:

one or more phase delay circuits, each phase delay circuit configured to receive the clock signal as an input and to output a respective copy of the clock signal, the respective copy being delayed in phase by a respective predetermined phase shift; and

one or more further sequence generators, each further sequence generator configured to generate a digital sequence signal based on a respective one of the at least one phase-delayed copy of the clock signal to provide a respective phase-delayed copy of the digital sequence signal to the mixer.

4. The DMR transmitter module of any one of the preceding claims, wherein the modulator is a Phase Shift Keying (PSK) modulator and the modulated signal is a PSK modulated signal.

5. The DMR transmitter module of claim 4, wherein the PSK modulated signal is a Binary Phase Shift Keying (BPSK) signal.

6. The DMR transmitter module of any one of the preceding claims, wherein said modulator is an amplitude modulator and said modulation signal is an amplitude modulation signal.

7. The DMR transmitter module of any one of the preceding claims, wherein the relatively high frequency carrier signal is derived from a local oscillator and one of the clock signals is derived from the local oscillator, or the local oscillator is derived from the clock signal.

8. A DMR system comprising a DMR transmitter module according to any one of the preceding claims and additionally comprising a receiver module, wherein said receiver module comprises:

a down converter configured to down convert the received signal to a reference frequency;

a track and hold circuit;

and an analog-to-digital converter (ADC) configured to digitize a portion of the down-converted received signal.

9. The DMR system of claim 8, wherein said receiver module additionally comprises

A cross-correlation unit configured to cross-correlate the portion of the down-converted received signal with the digital sequence signal.

10. A method of generating a digitally modulated radar signal, the method comprising:

generating a digital sequence and a repeating digital sequence signal based on the digital sequence and a relatively low frequency clock signal;

generating at least one phase-delayed copy of the digital sequence signal;

combining the digital sequence signal with at least one phase-delayed copy of the digital sequence signal in a mixer to provide a combined signal; and

modulating a relatively high frequency carrier signal dependent on the combined signal to provide the digitally modulated radar signal.

Technical Field

The present disclosure relates to digitally modulated radar DMR, and in particular to digitally modulated radar DMR transmitter modules, DMR systems, and to methods of generating DMR signals.

Background

In a conventional radar system, a pulsed signal is transmitted from a transceiver and a reflected signal is received back at the transceiver. The reflected signal is analyzed by analyzing time of flight and doppler to provide distance and velocity information about the source of reflection. The limitations of dead time between pulses and the problem of distinguishing between multiple interfering signals can be addressed by using a digitally modulated radar DMR. In digitally modulated radars, a carrier signal is modulated according to a digital signal, rather than transmitting a simple high frequency carrier signal. The digital signal provides an identification code that can distinguish reflections of the transmitted signal from interfering signals and introduces time domain variations such that dead time does not have to be included in order to determine the total time of flight of the transmitted and reflected signals.

However, modulating the carrier signal according to the digital signal introduces side lobes in the frequency domain. These side lobes can carry significant power and in some regulatory environments, for example, for applications such as 77GHz automotive radar, this may be undesirable, or even unacceptable. The power or magnitude of these side lobes needs to be reduced.

Disclosure of Invention

According to a first aspect of the present disclosure, there is provided a digital modulation radar DMR transmitter module, comprising: a sequence generator configured to generate a repeating digital sequence signal based on a relatively low frequency clock signal; a mixer configured to combine the digital sequence signal with at least one phase-delayed copy of the digital sequence signal to provide a combined signal; and a modulator configured to modulate a relatively high frequency carrier signal dependent on the combined signal to provide a modulated signal. Combining the original repeated digital sequence signal changes the location of and power in the side lobes associated with the transmitted modulated high frequency signal and can reduce power in any single side lobe. There may be one, two or more phase delayed copies. The side lobes may be evenly spaced in phase, or the side lobes may be irregularly spaced. Irregular phase spacing may further reduce power in the side lobes.

In one or more embodiments, the DMR transmitter module additionally includes one or more phase delay circuits, each phase delay circuit configured to receive the digital sequence signal as an input and to provide a respective one of the at least one phase delayed copies of the digital sequence signal to the mixer, the respective one of the at least one phase delayed copies being delayed in phase by a respective predetermined phase shift.

In one or more other embodiments, the DMR transmitter module additionally includes one or more phase delay circuits, each phase delay circuit configured to receive the clock signal as an input and to output a respective copy of the clock signal, the respective copy of the clock signal being delayed in phase by a respective predetermined phase shift; and one or more further sequence generators, each further sequence generator configured to generate a digital sequence signal based on a respective one of the at least one phase-delayed copy of the clock signal to provide a respective phase-delayed copy of the digital sequence signal to the mixer. Such modules in which a phase delay is applied to a clock signal may be easier to implement than those modules that apply a phase delay to a digital sequence signal.

The modulator may be a phase shift keying, PSK, modulator, and the modulated signal is a PSK modulated signal. The PSK modulated signal may be a binary phase shift keying BPSK signal. Phase shift keying modulated signals, and in particular binary phase shift keying modulated signals, have proven to be particularly effective for use as transmit radar signals.

However, in one or more other embodiments, the modulator is an amplitude modulator and the modulated signal is an amplitude modulated signal, or the modulator is a frequency modulator and the modulated signal is a frequency modulated signal.

In one or more embodiments, the relatively high frequency carrier signal is derived from a local oscillator and one of the clock signals is derived from the local oscillator, or the local oscillator is derived from the clock signal. In general, it is much easier to multiply the frequency of a clock signal operating between, for example, 500MHz and 4GHz to generate a higher, relatively high frequency carrier signal operating at, for example, 77GHz or 140GHz, rather than directly generating the relatively high frequency signal.

According to another aspect of the present disclosure, there is provided a DMR system comprising a DMR transmitter module as described above, and further comprising a receiver module, wherein the receiver module comprises: a down converter configured to down convert the received signal to a reference frequency; a track and hold circuit; and an analog-to-digital converter (ADC) configured to digitize a portion of the down-converted received signal.

The receiver module may additionally comprise a cross-correlation unit configured to cross-correlate the portion of the down-converted received signal with the digital sequence signal.

According to yet a further aspect, there is provided a method of generating a digitally modulated radar signal, the method comprising: generating a digital sequence and a repeating digital sequence signal based on the digital sequence and a relatively low frequency clock signal; generating at least one phase-delayed copy of the digital sequence signal; combining the digital sequence signal with at least one phase-delayed copy of the digital sequence signal in a mixer to provide a combined signal; and modulating a relatively high frequency carrier signal dependent on the combined signal to provide the digitally modulated radar signal.

In one or more embodiments, generating one of the at least one phase-delayed copy of the digital sequence signal comprises: receiving the repeated digital sequence signals in respective phase delay circuits; delaying the phase by a respective predetermined phase shift; and providing a respective one of the at least one phase-delayed copy of the digital sequence signal to the mixer.

In one embodiment or in other embodiments, generating one of the at least one phase-delayed copy of the digital sequence signal comprises: receiving the clock signal in a respective phase delay circuit, delaying the phase by a respective predetermined phase shift, and outputting a phase delayed copy of the clock signal; and generating a digital sequence signal based on the digital sequence and the phase delayed copy of the clock signal to provide the one of the at least one phase delayed copy of the digital sequence signal to the mixer.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

Drawings

Embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which

FIG. 1 shows an example of a sequence of numbers;

FIG. 2 shows the frequency spectrum of a digital signal for a 77GHz automotive radar application;

FIG. 3a illustrates a repeating binary digital sequence signal with signal shaping in accordance with one or more embodiments;

FIG. 3b shows a repeating 3-3 digital sequence signal with signal shaping in accordance with one or more other embodiments;

fig. 4 shows a frequency spectrum of a carrier signal modulated by a combined signal;

FIG. 5 illustrates a reference frequency portion of a module in accordance with one or more embodiments.

FIG. 6 shows a reference frequency portion of a module according to other embodiments;

FIG. 7 illustrates a DMR system in accordance with one or more embodiments; and

fig. 8 illustrates a MIMO DMR system in accordance with one or more embodiments.

It should be noted that the drawings are diagrammatic and not necessarily drawn to scale. Relative dimensions and proportions of parts of these figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments.

Detailed Description

Fig. 1 shows an example of a number sequence, such as those used for DMR. In this case, the example number sequence shown: {0, 1, 0, 1, 0, 0, 1, 1. } is binary, but the skilled person will appreciate that higher clustering or other forms of sequences are possible, so that other values than 0 or 1 may be used. In typical radar applications, the digital sequence may comprise 2^12 or 4k bits; however, other sequence lengths may be used.

The sequence is applied to a clock to generate a digital sequence signal 120. The clock may operate at a so-called reference frequency, which may typically be, but is not limited to, about 500MHz to 4 GHz. At a clock frequency of 4GHz, the sequence of 4k bits shown at 130 thus lasts about 1 ms. The sequence is repeated to produce a repeated digital sequence signal 140.

As will be familiar to those skilled in the DMR art, this repeated digital sequence signal 140 may be used to modulate a carrier signal to produce a radar transmission signal. The carrier signal has a frequency relatively higher than a reference frequency. In the case of automotive radar, the regulatory body has allocated a frequency band centered at 77GHz, and therefore this frequency band is typically used. However, the present disclosure is not limited thereto: for example, also in the automotive field, another frequency band of about 140GHz is considered to be available.

The repeated digital sequence signal 140 is used to modulate a carrier signal. Most commonly, the modulation is phase modulation, but the skilled person will appreciate that other forms of modulation, such as amplitude modulation, frequency modulation, are equally suitable. In the case of phase modulation, also known as Phase Shift Keying (PSK), Binary Phase Shift Keying (BPSK) is generated using a binary digital signal such as that described above; in the case of multi-level signals or high combining, alternative forms of phase shift keying, e.g., quaternary phase shift keying QPSK or n-QSPK, are equally suitable.

Also, as the skilled person will be familiar, modulating a carrier signal by a digital signal produces side lobes when viewed in the frequency domain. Fig. 2 shows a spectrum 230 of a digital signal for a 77Ghz automotive radar application. The diagram shows the Effective Isotropic Radiated Power (EIRP) on the ordinate or y-axis 210 plotted against the bandwidth on the abscissa or x-axis. As expected, the power is highest at the carrier frequency, as shown by the main power spike 232, however, there is considerable power in the side lobes, as shown at 234, 236 and 238, which are located at about 3GHz, 5GHz and 7GHz from the center frequency.

An example of a power mask 240 is also shown in fig. 2. The power mask shows power limits that may be recommended or imposed by a regulatory body, such as the ETSI (european telecommunications standards institute). As shown, the power mask may impose the requirement that the transmit power outside of a narrow bandwidth (e.g., ± 2GHz as shown) be limited to a relatively low level (e.g., at least 30dB below the peak signal as shown). Applying a spectral mask generally aims to reduce adjacent channel interference by limiting excessive radiation at frequencies outside the required bandwidth. As can be seen from the figure, the side lobes of the DMR transmit signal may exceed this limit.

It is known to attenuate these side lobes by using a band pass filter tuned to allow the correct center frequency of the carrier together with the necessary sidebands to properly transmit the digital signal. The bandpass filter may be implemented with passive components; however, this may not be feasible in some applications where monolithic integration is desired or required.

An alternative solution is to implement the band pass filter in the digital domain. This can be done by applying a Finite Impulse Response (FIR) filter in the signal generation chain. However, to implement this, the signal must be generated by a high speed digital to analog converter (DAC) that operates at a higher speed than the bit rate of the signal to be generated. This in turn requires space on the silicon chip to implement the DAC and FIR filter, and considerable processing power and effort to operate those IP blocks.

Fig. 3a illustrates a repeating digital sequence signal with signal shaping in accordance with one or more embodiments. The repeated digital sequence signal 140 is the same as the repeated digital sequence signal shown in fig. 1. This signal is combined with one or more copies of the signal. Three copies 310, 320, 330 are shown in this non-limiting example. The "decomposed" signals are shown at the top of the figure, and each signal is overlaid at the second portion of the figure. As shown, the signal is a phase delayed or phase shifted replica of the original repeating digital sequence signal. That is, the signals are identical except for the fact that their clocks have a relative phase difference. In the example shown, and with reference to the original repeating digital sequence signal, the phase delay is 60 ° for the first copy 310, 180 ° for the second copy 320, and 240 ° for the third copy 330.

The signals are then combined to provide a combined signal, which may be plotted as amplitude versus time in the third portion of the figure, as shown at 340. In the case of binary signals, the combination is made such that whenever any one or more of the individual signals is "high" or "1" the combined signal is "high" or "1", whereas when all of the individual signals are "low" or "0", the combined signal is only "low" or "0". Thus, a single "0" bit in the original signal produces a much shorter "0" time in the combined signal, as shown at 342, and a single "1" bit in the original signal produces a longer "1" time in the combined signal, as shown at 344. It will be observed that in the case of another bit following the bit that is the same parity (e.g., two "0" s shown at 346), one of the bits is unaffected. In the case of two consecutive "0" s, this is the second bit. In the case of two consecutive "1" s, this will be the first bit unaffected.

Finally, the bottom part of the figure shows the signal 345 after smoothing. It should be appreciated that the "square wave" digital signal shown at the top of the figure is idealized. In any practical circuit, it is shown in the upper part of the figure that transient sharp transitions between high and low states do not occur, and signal transitions are rounded. By including a phase delayed copy of the signal, the irregularity of the transition interval is increased and the effect is to smooth the transition between levels. This will increase the slope of the transition and round the square signal in such a way that the spectral components are reduced.

Fig. 3a illustrates a repeating digital sequence signal with signal shaping in accordance with one or more other embodiments. The original three-level signal 360 is combined with a phase-delayed copy, in this example, 3 such copies 362, 364 and 368. In this particular non-limiting example, the phase delays are 60 °, 180 °, and 240 °, respectively. As shown by idealized signal 370, the irregularity of the composite signal between level transitions increases. Also, the composite signal that is actually obtained after unavoidable and indeed desirable transition smoothing is shown at 375.

Fig. 4 shows the frequency spectrum of a carrier signal modulated by a combined signal 340. The spectrum 230 of the original digital signal is shown as well as the spectrum of the combined signal 430. As can be seen, the shape of the main peak 432 of the combined signal is invariant with respect to the original signal; however, the side lobes 434, 436, 438, 439 have different center frequencies and have lower magnitudes relative to the side lobes of the original signal.

The degree of accuracy of the power reduction in the side lobes depends on the digital sequence, the number of phase delayed copies of the repeated digital sequence signal that are combined with the original repeated digital sequence signal, and the choice of phase delay. At present, it is not possible to mathematically calculate the optimum phase delay for a given number of copies and range of digital sequences.

It will be appreciated that the choice of the number sequence used in the system depends on several criteria. In addition to the sequence lengths already mentioned above, two important factors are auto-and cross-correlation. In general, for radar applications, it is desirable to have minimal and preferably zero cross-correlation between two sequences in the same system, or in two systems that are expected to operate in the same physical space and therefore potentially interfere. As used in the radar art, cross-correlation is a mathematical function that corresponds to the result of convolving two sequences or signals. If the sequences are identical, a full cross-correlation corresponding to a correlation level of "1" is generated; conversely, if the sequences are not completely correlated, a zero cross-correlation corresponding to a correlation level of "0" is produced. The lower the cross-correlation, the lower the probability that a receiver will incorrectly identify a signal carrying one sequence as a signal carrying another sequence or a reflected version of the signal. For two sequences with zero cross-correlation, they must be perfectly orthogonal, and it should be understood that this is only the case in an infinitely long sequence. The shorter the sequence, the higher the cross-correlation with any other sequence. The choice of sequence length is thus a compromise on the extent of cross-correlation that can be tolerated.

Considering now the autocorrelation, the sequence should be infinitely long for a complete autocorrelation. Conceptually, autocorrelation refers to the extent to which a sequence corresponds to a time-shifted copy of itself. If the sequence matches the time-shifted sequence exactly, then a complete auto-correlation corresponding to a correlation level of "1" is generated, yielding an absolute confidence that the time-shifted sequence originated from the original sequence (e.g., a reflection from the original sequence); conversely, if the sequence and the time-shifted sequence are not all correlated, a zero autocorrelation corresponding to a correlation level of "0" is produced, whereby it can be concluded that the time-shifted sequence does not originate from the original sequence, and thus from the interfering signal. In the field of radar, the autocorrelation function is not a discrete signal: if there is a match in the autocorrelation due to a reflected signal that is delayed relative to the transmitted signal but has the same sequence, the level of Dirac (delta Dirac) Dirac that will produce the autocorrelation will depend on the magnitude of the reflected signal.

It will therefore be appreciated that the phase delayed copy of the original sequence has a very high level of autocorrelation with the original sequence. This is important because it greatly simplifies the processing requirements of the signals received by the radar receiver in order to identify and analyze reflections of the transmitted signals, as will be discussed in more detail below.

Returning now to the problem of selecting the number of phase delayed copies of the repeated digital sequence signal and the phase delay, as already mentioned, it is likely that the optimal number and phase delay cannot be mathematically calculated. However, it has been found experimentally that, in general, an increase in the number of copies results in a reduction in side lobes, as well as a reduction in the irregular spacing of the phase delays. Conceptually, this can be explained as follows: pure square wave signals are known to have very high harmonic components, especially when compared to sine wave signals having only fundamental frequency components. The original repeating digital sequence signal closely corresponds to the square wave signal and it has a high harmonic content. By combining the sequence with a phase-delayed version of the sequence, it is made less similar to a square wave and this results in a reduced harmonic content.

Turning now to fig. 5 and 6, according to a first aspect of the present disclosure, there is provided a digitally modulated radar DMR transmitter module, comprising: a sequence generator 510, 610 configured to generate a repeating digital sequence signal 515, 615 based on a relatively low frequency clock signal 520, 620. The modules additionally comprise mixers 530, 630 configured to combine the digital sequence signal with at least one phase delayed copy of the digital sequence signal to provide combined signals 560, 660; and a modulator (not shown in fig. 5 and 6) configured to modulate the relatively high frequency carrier signal dependent on the combined signal to provide a modulated signal.

Considering now, in particular, fig. 5, this figure shows an example of a reference frequency portion 500 of a module, in which there are one or more phase delay circuits 542, 544, 546, each configured to receive as input a digital sequence signal 515, and to provide to the mixer a respective one of at least one phase delayed copy 552, 554, 556 of the digital sequence signal, the at least one phase delayed copy being delayed in phase by a respective predetermined phase shiftThe mixer may be implemented as an exclusive or gate. Thus, in this embodiment, a single code generator is used and a shifted version is generated by delaying the original signal with a phase shifter. While there are a variety of known methods of implementing the phase shifters required for such embodiments, the skilled person will appreciate that this may be challenging or consume a significant amount of silicon chip space and/or power to implement such phase shifters at the frequencies involved (which, as mentioned above, may be on the order of 4 GHz): applying a digital sequence to a clock signal produces an ultra-wideband or UWB signal and the skilled person will appreciate that it is important to phase shift the UWB signal.

Turning now to fig. 6, this figure shows an example of a reference frequency portion 600 of a module, which additionally comprises: one or more phase delay circuits 642, 644, 646, each configured to receive a clock signal as an input and to output a respective copy of the clock signal, the respective copy being delayed in phase by a respective predetermined phase shiftAndthe skilled person will appreciate that the phase shift is givenThe illustrated phase delay circuit 640 is optional. Includes the circuit productGenerating matching paths of all signals; can be combined withIs set to 0. However, this may be omitted, in which case the phase shifts of phase delay circuits 642, 644 and 646, respectively, would beAndthis embodiment also includes one or more additional sequence generators 612, 614, 616 (in addition to sequence generator 610), each configured to generate a digital sequence signal based on a respective one of the at least one phase-delayed copy of the clock signal to provide a respective phase-delayed copy of the digital sequence signal to the mixer. That is, each signal generated is triggered by its own separate clock signal. The phase shift may be achieved by shifting the phase of each clock. Thus, for example, the phase shifter in an embodiment may have a low complexity relative to the phase shifter shown in fig. 5.

Turning now to fig. 7, this figure generally illustrates a DMR system 700 that includes a DMR transmitter 720 and a receiver module 740, wherein the receiver module includes: a down converter configured to down convert the received signal to a reference frequency; a track and hold circuit; and an analog-to-digital converter (ADC) configured to digitize a portion of the down-converted received signal, and a digital signal processing module.

The DMR transmitter 720 includes a transmitter module 710 having one or more phase delay circuits, in this example three phase delay circuits 642, 644, and 646, the phase delay circuits 642, 644, and 646 configured to delay the phase of the clock signal 620. The transmitter module 600 includes a sequence generator 610 that applies a digital sequence to an incoming clock signal, and sequence generators 612, 614, and 616 that apply the digital sequence to respective phase-delayed versions of the clock signal to generate an original repeated digital sequence signal, and three phase-delayed versions of the repeated digital sequence signal, as discussed above with respect to fig. 6. The original repeated digital sequence signal is combined by mixer 630 with three phase delayed versions as also discussed above. This combined reference signal is then used to modulate a relatively high frequency carrier signal 715. The modulated carrier signal output from the transmitter module 710 is amplified by a variable gain amplifier 725 and transmitted by way of an antenna 728.

A relatively high frequency carrier signal 715 may be provided by means of a local oscillator 717. In a non-limiting example, the local oscillator may operate at a relatively high frequency (which may be, for example, 77 GHz). The output from the local oscillator may be divided in divider 718 to a reference frequency (which may be, for example, between 500MHz and 4 GHz). The frequency divider may include or be associated with a fractional divider 719. As will be appreciated by the skilled person, in other embodiments the relatively high frequency carrier signal may be provided by multiplying the clock signal frequency. The clock signal may operate at a reference signal, which may be between 500MHz and 4GHz in another non-limiting example.

Reflections from the transmitted modulated carrier signal, as well as other interfering or spurious signals, are received at an antenna 738 forming part of a receiver 730. Along with an antenna 738, the receiver 730 includes a receiver module 740 and a Digital Signal Processing (DSP) unit 760.

The receiver module 740 receives incoming signals from the antenna 738 and processes the incoming signals in a conventional manner. Specifically, after being amplified by the variable gain amplifier 744, the signal is down-converted into a real component and a quadrature component having a phase difference of 90 ° therebetween by the down-converter 446. The down-converter utilizes a relatively high frequency carrier signal 715. The real and quadrature components of the downconverter signal may be amplified in a variable gain amplifier 748 and filtered in a low pass filter 752. The filtered baseband signal may be digitized with an effective sampling frequency of twice the signal bandwidth. To do this, the track-and-hold amplifier 754 may be driven in a normal sampling fashion using a divided LO signal, for example. Alternatively, the frequency of the divided LO signal may be further divided by a factor K (to provide a signal with a frequency K times lower than the reference frequency): in this way, the signal is sub-sampled: in other words, the signal is sampled at an instantaneous sampling frequency that is lower than the instantaneous sampling frequency indicated by the Nyquist theorem (Nyquist theorem), but the signal will be repeated k times to sample a portion of the signal in each repetition.

The receiver also includes a DSP block 760. The DSP block 760 may be part of a microcontroller. (Note that in one or more other embodiments, the DSP module and/or microcontroller may be separate from the receiver; it may be part of the central processing unit).

The DSP block 760 performs the functions required for DMR signal processing. In particular, after the signal has been digitized, the signal can be averaged by using a coherent summer 762 in order to increase the SNR of the system, and then the signal will be cross-correlated with the original digital sequence used at transmitter 764. If there are multiple transmitters, each transmitter may use a different orthogonal digital signal, and therefore at each receiver, the same amount of cross-correlator must be implemented. In this way, a MIMO system is constructed and all transmitters can transmit simultaneously, allowing the response of each TX channel on each RX channel to be reconstructed, which has the advantage of increasing the angular resolution of the radar system by using the same amount of physical TX/RX, but allowing the reconstruction of virtual RX channels with cross-correlators. This is shown in fig. 7 as MIMO synthesis 766. The cross-correlation function shows the range of all objects. It should be noted that for each TX, a spectral shaping system is constructed. Finally, as will be familiar to those skilled in the art, a fast fourier transform technique is applied as shown in 768 to obtain spectral information from which the velocity of the target can be estimated using a doppler technique.

It should be appreciated that in accordance with embodiments of the present disclosure, the received baseband signal for radar processing is not a simple copy of the original digital sequence signal, and not only may there be a doppler effect as with conventional DMR radar, but in accordance with embodiments the received signal is a combination of multiple phase-delayed versions of the original digital sequence signal. While this may be considered to add additional complexity to the process, in practice this is not the case: since the received signal is based on multiple copies of the same digital sequence, these are only presented to the correlator as additional time-shifted copies of the original signal that are easily identifiable. The correlator may be implemented as a matched filter to the incoming signal, in the form of a finite impulse response (FI filter).

Turning now to fig. 8, this figure generally illustrates a multiple-input multiple-output (MIMO) DMR system 800 in accordance with one or more embodiments. In a MIMO DMR system, there are multiple transmitter modules 710, four shown in this particular example. The resulting 4 repeated digital sequence signals, each having a separate orthogonal digital sequence associated therewith, are each used to modulate a carrier signal 715 and, after amplification in a respective variable gain amplifier 725, are transmitted from separate antennas 728.

The reflected signal, as well as any interfering signals, are received by two or more antennas 738, four being shown in this particular example. The combination of N transmitters and M receivers results in N × M combinations, which in the example shown is 4 × 4, resulting in 16 combinations. As shown, each receiver includes a receiver module, such as that shown at 740 in fig. 7. The DSP block 860 is also substantially similar to the block shown in fig. 7. The correlator may be based on, but not limited to, a Fast Hadamard Transform (FHT)864 or other techniques such as will be well known to those skilled in the art of radar processing. Additional processing features provided by MIMO are features of digital beamforming 870 in order to provide angle-of-arrival information to improve positioning of a single target, as will also be well known to those skilled in the radar processing art.

Other variations and modifications will be apparent to persons skilled in the art upon reading the present disclosure. Such variations and modifications may involve equivalent and other features which are already known in the DMR art and which may be used instead of or in addition to features already described herein.

As used herein, the term "phase-delayed copy of a signal" (or in general "phase-shifted copy of a signal") refers to a signal that has the same content as the original signal but is delayed in time (or shifted accordingly). Thus, if the signal has a fundamental frequency of, for example, 1GHz, it has a dominant period of 1 ns. A phase-delayed copy of the signal with a 90 ° phase delay would therefore lag the original signal by (90 °/360 °) × 1ns, that is to say 250ps, and a phase-delayed copy of the signal with a 270 ° phase delay would lag the original signal by (270 °/360 °) × 1ns or 750 ps.

Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

For the sake of completeness it is also stated that the term "comprising" does not exclude other elements or steps, the terms "a" or "an" do not exclude a plurality, a single processor or other unit may fulfil the functions of several means recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims.