Distance sensor and distance measuring device
阅读说明：本技术 距离传感器和距离测量装置 (Distance sensor and distance measuring device ) 是由 森山祐介 于 2019-02-26 设计创作，主要内容包括：提供了一种飞行时间传感器。飞行时间传感器包括光接收元件PD；第一信号线TRGO和第二信号线TRG180；与光接收元件电连通的第一晶体管TGA,第一晶体管包括与第一信号线TRGO电连通的第一栅极；与光接收元件电连通的第二晶体管TGB,第二晶体管包括与第二信号线TRG180电连通的第二栅极；以及包括至少一个比较器102A、102B的控制电路P200,其中,控制电路与第一信号线TRGO和第二信号线TRG180电连通。像素电路P100的晶体管TGA和TGB导通和断开,使得晶体管TGA和TGB中的任一个导通,并且由光电二极管PD生成的电荷选择性地累积在浮动扩散FDA和浮动扩散FDB中。分别取决于第一浮动扩散FDA和第二浮动扩散FDB处的电压的第一电压VSLA和第二电压VSLB与参考电压VREF进行比较。第一信号TRGO是时钟信号SCK和比较器输出QO的逻辑积,第二信号TRG180是反相的时钟信号SCK和比较器输出QO的逻辑积。距离测量装置具有成像单元,其包括以矩阵形式排列的多个成像像素P的像素阵列。为一个像素电路P100提供一个控制电路P200。控制电路P200控制像素电路P100中的曝光时间。像素电路P100将电压VSLA和VSLB提供给控制电路P200,并且控制电路P200基于电压VSLA和VSLB生成信号TRGO和TRG180,并且将这些信号TRGO和TRG180提供给像素电路P100。因此,由于可以在多个成像像素中的每一个中单独设置曝光时间,所以可以提高距离测量的测量精度。(A time-of-flight sensor is provided. The time-of-flight sensor includes a light receiving element PD; a first signal line TRGO and a second signal line TRG 180; a first transistor TGA in electrical communication with the light receiving element, the first transistor including a first gate electrode in electrical communication with a first signal line TRGO; a second transistor TGB in electrical communication with the light receiving element, the second transistor including a second gate electrode in electrical communication with a second signal line TRG 180; and a control circuit P200 including at least one comparator 102A, 102B, wherein the control circuit is in electrical communication with the first signal line TRGO and the second signal line TRG 180. The transistors TGA and TGB of the pixel circuit P100 are turned on and off, so that either one of the transistors TGA and TGB is turned on, and charges generated by the photodiode PD are selectively accumulated in the floating diffusion FDA and the floating diffusion FDB. The first and second voltages VSLA and VSLB, which depend on the voltages at the first and second floating diffusions FDA and FDB, respectively, are compared with the reference voltage VREF. The first signal TRGO is the logical product of the clock signal SCK and the comparator output QO, and the second signal TRG180 is the logical product of the inverted clock signal SCK and the comparator output QO. The distance measuring device has an imaging unit including a pixel array of a plurality of imaging pixels P arranged in a matrix form. A control circuit P200 is provided for one pixel circuit P100. The control circuit P200 controls the exposure time in the pixel circuit P100. The pixel circuit P100 supplies the voltages VSLA and VSLB to the control circuit P200, and the control circuit P200 generates signals TRGO and TRG180 based on the voltages VSLA and VSLB, and supplies these signals TRGO and TRG180 to the pixel circuit P100. Therefore, since the exposure time can be set individually in each of the plurality of imaging pixels, the measurement accuracy of the distance measurement can be improved.)
1. A time-of-flight sensor, comprising:
a light receiving element;
a first signal line and a second signal line;
a first transistor in electrical communication with the light-receiving element, the first transistor including a first gate in electrical communication with the first signal line;
A second transistor in electrical communication with the light receiving element, the second transistor including a second gate in electrical communication with the second signal line; and
a control circuit comprising at least one comparator, wherein the control circuit is in electrical communication with the first signal line and the second signal line.
2. The time of flight sensor of claim 1, in which the at least one comparator comprises a first comparator and a second comparator, in which the first and second comparators are configured to receive a reference voltage.
3. The time of flight sensor of claim 2, wherein the control circuit further comprises:
a NAND circuit in electrical communication with the first comparator and the second comparator;
a latch in electrical communication with the NAND circuit, a first AND circuit, AND a second AND circuit, wherein the first AND circuit is in electrical communication with the first signal line AND the second AND circuit is in electrical communication with the second signal line.
4. The time-of-flight sensor of claim 1, further comprising:
a first capacitor in electrical communication with the light receiving element via the first transistor; and
a second capacitor in electrical communication with the light receiving element via the second transistor.
5. The time-of-flight sensor of claim 1, further comprising:
a first semiconductor substrate on which the light receiving element, the first transistor, and the second transistor are formed; and
a second semiconductor substrate, wherein the control circuit is formed on the second semiconductor substrate.
6. The time of flight sensor of claim 5, in which the first semiconductor substrate is stacked on the second semiconductor substrate.
7. The time-of-flight sensor of claim 1, further comprising:
a first capacitor in electrical communication with the light receiving element;
a third signal line configured to supply a first voltage based on an amount of charge stored by the first capacitive element; and
a first analog-to-digital converter in electrical communication with the third signal line.
8. The time of flight sensor of claim 7, further comprising:
a second capacitor in electrical communication with the light receiving element, wherein the first capacitor is in electrical communication with the light receiving element via the first transistor, and the second capacitor is in electrical communication with the light receiving element via the second transistor;
A fourth signal line configured to supply a second voltage based on the amount of charge stored by the second capacitive element; and
a second analog-to-digital converter in electrical communication with the fourth signal line.
9. The time-of-flight sensor of claim 1, further comprising:
a second light receiving element;
a third signal line and a fourth signal line;
a third transistor in electrical communication with the second light receiving element, the third transistor including a third gate in electrical communication with the third signal line;
a fourth transistor in electrical communication with the second light-receiving element, the fourth transistor including a fourth gate in electrical communication with the fourth signal line; and is
The control circuit is in electrical communication with the third signal line and the fourth signal line.
10. The time of flight sensor of claim 9, in which the control circuit comprises a second comparator and a third comparator, in which the second comparator and the third comparator are configured to receive a reference voltage.
11. The time of flight sensor of claim 9, in which the control circuit comprises a voltage selector in communication with the first, second, third and fourth signal lines.
12. A distance measuring device comprising:
a light source and a light source control unit in communication with the light source;
an imaging unit comprising:
a light receiving element;
a first signal line and a second signal line;
a first transistor in electrical communication with the light-receiving element, the first transistor including a first gate in electrical communication with the first signal line;
a second transistor in electrical communication with the light receiving element, the second transistor including a second gate in electrical communication with the second signal line; and
a control circuit comprising at least one comparator, wherein the control circuit is in electrical communication with the first signal line and the second signal line; and
a control unit in communication with the light source control unit and the imaging unit.
13. The distance measurement device of claim 12, wherein the at least one comparator comprises a first comparator and a second comparator, wherein the first comparator and the second comparator are configured to receive a reference voltage.
14. The distance measurement device of claim 13, wherein the control circuit further comprises:
a NAND circuit in electrical communication with the first comparator and the second comparator;
A latch in electrical communication with the NAND circuit, a first AND circuit, AND a second AND circuit, wherein the first AND circuit is in electrical communication with the first signal line AND the second AND circuit is in electrical communication with the second signal line.
15. The distance measuring device according to claim 12, further comprising:
a first capacitor in electrical communication with the light receiving element via the first transistor; and
a second capacitor in electrical communication with the light receiving element via the second transistor.
16. The distance measuring device according to claim 12, further comprising:
a first semiconductor substrate on which the light receiving element, the first transistor, and the second transistor are formed; and
a second semiconductor substrate, wherein the control circuit is formed on the second semiconductor substrate.
17. The distance measurement device according to claim 16, wherein the first semiconductor substrate is stacked on the second semiconductor substrate.
18. The distance measuring device according to claim 12, further comprising:
a first capacitor in electrical communication with the light receiving element;
a third signal line configured to supply a first voltage based on an amount of charge stored by the first capacitive element; and
A first analog-to-digital converter in electrical communication with the third signal line.
19. The distance measuring device of claim 18, further comprising:
a second capacitor in electrical communication with the light receiving element, wherein the first capacitor is in electrical communication with the light receiving element via the first transistor, and the second capacitor is in electrical communication with the light receiving element via the second transistor;
a fourth signal line configured to supply a second voltage based on the amount of charge stored by the second capacitive element; and
a second analog-to-digital converter in electrical communication with the fourth signal line.
20. The distance measuring device according to claim 12, further comprising:
a second light receiving element;
a third signal line and a fourth signal line;
a third transistor in electrical communication with the second light receiving element, the third transistor including a third gate in electrical communication with the third signal line;
a fourth transistor in electrical communication with the second light-receiving element, the fourth transistor including a fourth gate in electrical communication with the fourth signal line; and is
The control circuit is in electrical communication with the third signal line and the fourth signal line.
21. The distance measurement device of claim 20, wherein the control circuit comprises a second comparator and a third comparator, wherein the second comparator and the third comparator are configured to receive a reference voltage.
22. The distance measurement device of claim 20, wherein the control circuit includes a voltage selector in communication with the first signal line, the second signal line, the third signal line, and the fourth signal line.
Technical Field
The present disclosure relates to a distance sensor that detects a distance and a distance measuring device using such a distance sensor.
Background
In order to measure the distance to the object to be measured, a time of flight (TOF) method is often used. A distance measuring device using the TOF method emits light and detects reflected light reflected by an object to be measured. Then, the distance measuring device detects a time difference between the emission time of the emitted light and the detection time of the reflected light, thereby measuring the distance to the object to be measured (for example, patent document 1).
Reference list
Patent document
PTL 1: international publication No. 2014-207983
Disclosure of Invention
Technical problem
Now, the distance measuring device is desired to have high measurement accuracy, and the measurement accuracy is desired to be further improved.
It is desirable to provide a distance sensor and a distance measuring device capable of improving the measurement accuracy.
Solution to the problem
In accordance with the present disclosure, a time-of-flight sensor is provided. The time-of-flight sensor includes: a light receiving element; a first signal line and a second signal line; a first transistor in electrical communication with the light receiving element, the first transistor including a first gate in electrical communication with a first signal line; a second transistor in electrical communication with the light receiving element, the second transistor including a second gate in electrical communication with a second signal line; and a control circuit comprising at least one comparator, wherein the control circuit is in electrical communication with the first signal line and the second signal line.
According to the present disclosure, a distance measuring device is provided. The distance measuring device includes a light source and a light source control unit in communication with the light source. The distance measuring apparatus includes an imaging unit including: a light receiving element; a first signal line and a second signal line; a first transistor in electrical communication with the light receiving element, the first transistor including a first gate in electrical communication with a first signal line; a second transistor in electrical communication with the light receiving element, the second transistor including a second gate in electrical communication with a second signal line; and a control circuit comprising at least one comparator, wherein the control circuit is in electrical communication with the first signal line and the second signal line. The distance measuring device includes a control unit in communication with the light source control unit and the imaging unit.
Advantageous effects of the invention
The distance sensor and the distance measuring device according to one embodiment of the present disclosure are adapted to control the on/off operations of the plurality of first transistors based on the plurality of first detection voltages depending on the voltages in the plurality of first accumulation units, thereby making it possible to improve the measurement accuracy. Note that the advantageous effects described herein are not considered to be necessarily limited thereto, and any advantageous effects described in the present disclosure may be achieved.
Drawings
Fig. 1 is a block diagram showing a configuration example of a distance measuring apparatus according to an embodiment of the present disclosure;
fig. 2 is a block diagram showing a configuration example of the imaging unit shown in fig. 1;
fig. 3 is a circuit diagram showing a configuration example of the pixel array shown in fig. 2;
fig. 4 is an explanatory view showing a configuration example of the distance measuring device shown in fig. 1;
fig. 5 is a circuit diagram showing a configuration example of the reading unit shown in fig. 2;
fig. 6 is a timing chart showing an operation example of the distance measuring apparatus shown in fig. 1;
fig. 7A to 7L are timing waveform diagrams showing an example of an exposure operation according to the first embodiment;
fig. 8A to 8D are another timing waveform diagram showing an example of an exposure operation according to the first embodiment;
fig. 9 is an explanatory diagram showing an example of an exposure operation according to the first embodiment;
fig. 10A to 10H are another timing waveform diagrams showing an example of an exposure operation according to the first embodiment;
fig. 11A to 11G are another timing waveform diagram showing an example of a read operation according to an embodiment;
fig. 12 is a circuit diagram showing a configuration example of a pixel array according to a modified example of the first embodiment;
Fig. 13A to 13M are timing waveform diagrams showing an example of an exposure operation according to a modified example of the first embodiment;
fig. 14A to 14J are another timing waveform diagram showing an example of an exposure operation according to a modified example of the first embodiment;
fig. 15 is a circuit diagram showing a configuration example of a pixel array according to a second embodiment;
fig. 16A to 16L are timing waveform diagrams showing an example of an exposure operation according to the second embodiment;
fig. 17A to 17F are another timing waveform diagram showing an example of an exposure operation according to the second embodiment;
fig. 18 is an explanatory diagram showing an example of an exposure operation according to the second embodiment;
fig. 19 is another explanatory diagram showing an example of an exposure operation according to the second embodiment;
fig. 20 is a circuit diagram showing a configuration example of a control circuit according to a modified example of the second embodiment;
fig. 21 is a circuit diagram showing a configuration example of a control circuit according to another modified example of the second embodiment;
fig. 22 is a circuit diagram showing a configuration example of a pixel array according to a third embodiment;
fig. 23A to 23K are timing waveform diagrams showing an example of an exposure operation according to the third embodiment;
Fig. 24A to 24F are another timing waveform diagram showing an example of an exposure operation according to the third embodiment;
fig. 25A to 25E are explanatory views showing an example of an exposure operation according to the third embodiment;
fig. 26 is a circuit diagram showing a configuration example of a pixel array according to a modified example of the third embodiment;
fig. 27A to 27L are timing waveform diagrams showing an example of an exposure operation according to a modified example of the third embodiment;
fig. 28A to 28D are another timing waveform diagrams showing an example of an exposure operation according to a modified example of the third embodiment;
fig. 29A to 29D are another timing waveform diagram showing an example of an exposure operation according to a modified example of the third embodiment;
fig. 30 is a block diagram showing a configuration example of a main part of a distance measuring apparatus according to the first embodiment;
fig. 31 is a block diagram showing a configuration example of a main part of a distance measuring apparatus according to a second embodiment;
fig. 32 is a block diagram showing a configuration example of a main portion of a distance measuring apparatus according to a modified example;
fig. 33 is a block diagram showing a configuration example of a main portion of a distance measuring apparatus according to another modified example;
Fig. 34 is a block diagram showing a configuration example of a main part of a distance measuring apparatus according to a third embodiment;
fig. 35 is a block diagram showing a configuration example of a main portion of a distance measuring apparatus according to another modified example.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the description will be given in the following order.
1. First embodiment
2. Second embodiment
3. Third embodiment
<1 > first embodiment >
Example of configuration
Fig. 1 shows a configuration example of a distance measuring device (distance measuring device 1) according to an embodiment. The
The light source 11 is adapted to emit light pulses L1 toward the object to be measured and is configured with, for example, a light emitting diode (LED; light emitting diode). The light source control unit 12 is adapted to control the operation of the light source 11 based on instructions from the control unit 14. The light source 11 is adapted to perform a light emission operation of alternately repeating light emission and non-light emission based on an instruction from the light source control unit 12, thereby emitting a light pulse L1.
The optical system 13 includes a lens that forms an image on the imaging surface S1 of the imaging unit 20. The light pulse emitted from the light source 11 and reflected by the object to be measured (reflected light pulse L2) is incident on the optical system 13.
The imaging unit 20 is adapted to receive the reflected light pulses L2 based on instructions from the control unit 14, thereby generating a range image PIC. Each of the plurality of pixel values included in the distance image PIC is adapted to indicate a value (distance signal value) regarding the distance D to the object to be measured. Then, the imaging unit 20 is adapted to output the acquired distance image PIC as an image signal DATA.
The control unit 14 is adapted to provide control signals to the light source control unit 12 and the imaging unit 20 and to control the operation of these circuits and thus the operation of the
Fig. 2 shows a configuration example of the imaging unit 20. The imaging unit 20 includes a pixel array 21, a driving
The pixel array 21 has a plurality of imaging pixels P arranged in a matrix. Each imaging pixel P is adapted to output a pixel signal SIG corresponding to the amount of received light.
Fig. 3 shows a configuration example of the imaging pixel P. The pixel array 21 includes a plurality of control lines RSTL, a plurality of control lines SELL, a plurality of control lines SELCL, a plurality of control lines SETL, a plurality of clock signal lines CKL, a plurality of signal lines SGLA, and a plurality of signal lines SGLB. The control line RSTL is adapted to extend in a horizontal direction (a lateral direction in fig. 2 and 3), and the driving
The imaging pixel P includes a pixel circuit P100 and a control circuit P200. The pixel circuit P100 is adapted to accumulate charge from the reflected light pulses L2. The control circuit P200 is adapted to control the exposure time in the pixel circuit P100.
The pixel circuit P100 has a photodiode PD, transistors TGA and TGB, floating diffusions FDA and FDB, transistors RST, RSTA and RSTB, transistors AMPA and AMPB, and transistors SELA and SELB. In this example, the transistors TGA, TGB, RST, RSTA, RSTB, AMPA, AMPB, SELA, and SELB are N-type Metal Oxide Semiconductor (MOS) transistors.
The photodiode PD is a photoelectric conversion element that generates electric charges according to the amount of received light. The anode of the photodiode PD is grounded, and the cathode thereof is connected to the sources of the transistors TGA, TGB, and RST.
The gate of the transistor TGA is supplied with a signal TRG0, the source of which is connected to the cathode of the photodiode PD and the sources of the transistors TGB and RST, and the drain of which is connected to the floating diffusion FDA, the source of the transistor RSTA and the gate of the transistor AMPA. The floating diffusion FDA is adapted to accumulate charges provided from the photodiode PD via the transistor TGA and convert the accumulated charges into a voltage. The floating diffusion FDA is configured by using, for example, a diffusion layer formed on the surface of a semiconductor substrate. In fig. 3, the floating diffusion FDA is shown with a symbol of a capacitive element. The transistor AMPA has a gate connected to the floating diffusion FDA, the drain of the transistor TGA, and the source of the transistor RSTA, the drain thereof being supplied with the power supply voltage VDD, the source thereof being connected to the drain of the transistor SELA and the control circuit P200. The transistor SELA has a gate connected to the control line SELL, a drain connected to the source of the transistor AMPA and the control circuit P200, and a source connected to the signal line SGLA.
In the case where a transistor SELA2 (described later) in the control circuit P200 is in an on state and a transistor SELA in the pixel circuit P100 is in an off state, the source of the transistor AMPA is connected to a
The gate of the transistor TGB is supplied with a signal TRG180, the source thereof is connected to the cathode of the photodiode PD and the sources of the transistors TGA and RST, and the drain thereof is connected to the floating diffusion FDB, the source of the transistor RSTB, and the gate of the transistor AMPB. The floating diffusion FDB is adapted to accumulate charges supplied from the photodiode PD via the transistor TGB and convert the accumulated charges into a voltage. The floating diffusion FDB is configured by using, for example, a diffusion layer formed on the surface of the semiconductor substrate. In fig. 3, the floating diffusion FDB is shown by a symbol of a capacitive element. The transistor AMPB has a gate connected to the floating diffusion FDB, a drain of the transistor TGB, and a source of the transistor RSTB, a drain supplied with the power supply voltage VDD, and a source connected to a drain of the transistor SELB and the control circuit P200. The transistor SELB has a gate connected to the control line SELL, a drain connected to the source of the transistor AMPB and the control circuit P200, and a source connected to the signal line SGLB.
In the case where a transistor SELB2 (described later) in the control circuit P200 is in an on state and a transistor SELB in the pixel circuit P100 is in an off state, the source of the transistor AMPB is connected to a
The gate of the transistor RST is connected to the control line RSTL, the drain thereof is supplied with the voltage VRSTX, and the source thereof is connected to the cathode of the photodiode PD and the sources of the transistors TGA and TGB. The gate of the transistor RSTA is connected to the control line RSTL, its drain is supplied with the voltage VRST, and its source is connected to the floating diffusion FDA, the drain of the transistor TGA and the gate of the transistor AMPA. The gate of the transistor RSTB is connected to the control line RSTL, the drain thereof is supplied with the voltage VRST, and the source thereof is connected to the floating diffusion FDB, the drain of the transistor TGB and the gate of the transistor AMPB.
The control circuit P200 includes transistors SELA2 AND SELB2,
The gate of the transistor SELA2 is connected to a control line SELCL, the drain thereof is connected to the source of the transistor AMPA in the pixel circuit P100 and the drain of the transistor SELA therein, and the source thereof is connected to the
The gate of the transistor SELB2 is connected to a control line SELCL, the drain thereof is connected to the source of the transistor AMPB in the pixel circuit P100 and the drain of the transistor SELB therein, and the source thereof is connected to the
The
The
The AND
In the imaging pixel P thus configured, in the exposure operation D1, the control circuit P200 supplies signals TRG0 and TRG180 to the transistors TGA and TGB, respectively, in accordance with the clock signal SCK. Accordingly, the transistors TGA and TGB of the pixel circuit P100 are turned on and off, so that any one of the transistors TGA and TGB is turned on, and the charges generated by the photodiode PD are selectively accumulated in the floating diffusion FDA and the floating diffusion FDB. The pixel circuit P100 provides a voltage VSLA to the control circuit P200 according to the voltage at the floating diffusion FDA and provides a voltage VSLB to the control circuit P200 according to the voltage at the floating diffusion FDB. In the case where at least one of the voltages VSLA or VSLB reaches the predetermined voltage (voltage VREF), the control circuit P200 sets both the signals TRG0 and TRG180 to the low level. Accordingly, the transistors TGA and TGB of the pixel circuit P100 are turned off, and subsequently, the photodiode PD and the floating diffusions FDA and FDB are electrically turned off. In this way, the
Fig. 4 shows a configuration example of the
The driving unit 22 (fig. 2) is adapted to drive the plurality of imaging pixels P based on an instruction from the
The
Fig. 4 shows a configuration example of the
The AD conversion unit ADC is adapted to perform AD conversion based on the pixel signal SIG supplied from the pixel array 21, thereby converting the voltage of the pixel signal SIG into a digital CODE. The plurality of AD conversion units ADC are provided to correspond to the plurality of signal lines SGL. Specifically, the 0 th AD conversion unit ADC [0] is set to correspond to the 0 th signal line SGL [0], the 1 st AD conversion unit ADC [1] is set to correspond to the 1 st signal line SGL [1], and the 2 nd AD conversion unit ADC [2] is set to correspond to the 2 nd signal line SGL [2 ].
The AD conversion unit ADC includes
The switching unit SW supplies the digital CODE output from the AD conversion unit ADC to the BUS wiring BUS based on the control signal SSW supplied from the
In this example, the switching unit SW is configured using the same number of transistors as the bit length of the digital CODE. These transistors perform on-off control based on each bit of the control signal SSW (control signals SSW [0], SSW [1], SSW [2],) supplied from the
The BUS wiring BUS includes a plurality of lines adapted to transmit digital codes output from the AD conversion unit ADC. The
The
The imaging control unit 25 (fig. 2) is adapted to provide control signals to the
The
The control unit 14 (fig. 1) supplies control signals to the light source control unit 12 and the imaging unit 20, and controls the operations of these circuits to control the operation of the
Here, the photodiode PD corresponds to a specific example of "first light receiving element" according to the present disclosure. The floating diffusions FDA and FDB correspond to a specific example of "a plurality of first accumulation units" according to the present disclosure. The transistors TGA and TGB correspond to specific examples of "a plurality of first transistors" according to the present disclosure. The transistors AMPA, SELA, AMPB, and SELB correspond to specific examples of "a plurality of first output units" according to the present disclosure. The control circuit P200 corresponds to a specific example of "first control unit" according to the present disclosure. The
Operations and Activities
Next, the operation and activity of the
(overview of the Overall operation)
First, an overview of the overall operation of the
(detailed operation)
The
Fig. 6 shows an example of the exposure operation D1 and the reading operation D2 in the
The
Then, the
Thereafter, the
(Exposure operation D1)
Next, the exposure operation D1 in the
Fig. 7A to 7L show examples of the exposure operation D1, in which fig. 7A shows a waveform of a light pulse L1 emitted from the light source 11, fig. 7B shows a waveform of the control signal SRST, fig. 7C shows a waveform of the voltage VSLA, fig. 7D shows a waveform of the voltage VSLB, fig. 7E shows a waveform of the signal COA, fig. 7F shows a waveform of the signal COB, fig. 7G shows a waveform of the control signal SSET, fig. 7H shows a waveform of the control signal SRESET, fig. 7I shows a waveform of the signal QO, fig. 7J shows a waveform of the clock signal SCK, fig. 7K shows a waveform of the signal TRG0, and fig. 7L shows a waveform of the signal TRG 180.
In this exposure operation D1, the
Before time t12, the
Next, at time t11, the
Next, at time t12, the
In this way, the exposure period TB starts at this time t 12. In this exposure period TB, the photodiode PD generates electric charges based on the reflected light pulse L2 that depends on the light pulse L1. The transistor TGA of the pixel circuit P100 is turned on and off based on the signal TRG0, and the transistor TGB is turned on and off based on the signal TRG 180. In other words, one of the transistors TRA and TRB is on. Accordingly, the electric charges generated by the photodiode PD are selectively accumulated in the floating diffusion FDA and the floating diffusion FDB.
Fig. 8A to 8D show operation examples of the imaging pixel P1, in which fig. 8A shows a waveform of the light pulse L1, fig. 8B shows a waveform of the reflected light pulse L2, fig. 8C shows a waveform of the signal TRG0, and fig. 8D shows a waveform of the signal TRG 180. In this example, at time t21, the light pulse L1 rises, the signal TRG0 rises, and the signal TRG180 falls. Then, at time t23 where the phase is delayed from time t21 by "pi", the optical pulse L1 falls, the signal TRG0 falls, and the signal TRG180 rises. Similarly, at time t25 where the phase is delayed by "π" from time t23, the light pulse L1 rises, the signal TRG0 rises, and the signal TRG180 falls. Then, at time t26 where the phase is delayed from time t25 by "pi", the optical pulse L1 falls, the signal TRG0 falls, and the signal TRG180 rises.
The phase of the reflected optical pulse L2 is shifted from the phase of the optical pulse L1 by the phase
The transistor TGA transfers the charge generated by the photodiode PD to the floating diffusion FDA in a period in which the signal TRG0 is at a high level, and the transistor TGB transfers the charge generated by the photodiode PD to the floating diffusion FDB in a period in which the signal TRG180 is at a high level. In other words, the transistor TGA transfers the charge generated by the photodiode PD to the floating diffusion FDA in the period from time t22 to time t23, and the transistor TGB transfers the charge generated by the photodiode PD to the floating diffusion FDB in the period from time t23 to
Signal I as the difference between charge S0 and charge S180According to phase (S0-S180)
FIG. 9 shows a signal IExamples of (2). Here, the signal I
As shown in fig. 7A to 7L and fig. 8A to 8D, the imaging pixel P1 repeats the operation at time t21 to
Since the voltages VSLA and VSLB are higher than the voltage VREF in the period until the time t13, the comparator 103A holds the voltage of the signal COA at a high level (fig. 7E), and the comparator 103B holds the voltage of the signal COB at a high level (fig. 7F). Therefore, the
Then, at time t13, voltage VSLA reaches voltage VREF. Therefore, the
In this example, at time t13, the voltage VSLA reaches the voltage VREF, and the exposure period TB ends, but in the case where the degree of variation of the voltages VSLA and VSLB is lower than the examples in fig. 7A to 7L, the exposure period TB ends at a later time. In the
Then, at time t14, the light source 11 terminates the lighting operation (fig. 7A).
Next, the operation of two imaging pixels P1 and P2 among the plurality of imaging pixels P will be described. The imaging pixel P1 receives the reflected light pulse L2 reflected at a position close to the
Fig. 10A to 10H show examples of operations in two imaging pixels P1 and P2, in which fig. 10A shows waveforms of a control signal SRST supplied to imaging pixels P1 and P2, fig. 10B shows waveforms of a control signal SSET supplied to imaging pixels P1 and P2, fig. 10C shows a waveform of a voltage VSLA (voltage VSLA1) at imaging pixel P1, fig. 10D shows a waveform of a voltage VSLB (voltage VSLB1) at imaging pixel P1, fig. 10E shows a waveform of a control signal SRESET (control signal SRESET1) at imaging pixel P1, fig. 10F shows a waveform of a voltage VSLA (voltage VSLA2) at imaging pixel P2, fig. 10G shows a waveform of a voltage VSLB (voltage VSLB2) at imaging pixel P2, and fig. 10H shows a waveform of a
At time t12, the exposure period TB1 in the imaging pixel P1 starts, and the exposure period TB2 in the imaging pixel P2 starts.
Then, in this example, at time t18, voltage VSLA1 at imaging pixel P1 reaches voltage VREF, and at time t19 after time t18, voltage VSLA2 at imaging pixel P2 reaches voltage VREF. In other words, since the imaging pixel P1 receives the reflected light pulse L2 reflected at a position close to the
In this way, the exposure period TB1 at the imaging pixel P1 ends at time t18, and the exposure period TB2 at the imaging pixel P2 ends at time t 19. As described above, in the
As described above, in the
(read operation D2)
Next, the reading operation D2 in the
Fig. 11A to 11G show examples of the exposure operation D1, in which fig. 11A shows a waveform of the control signal SSEL, fig. 11B shows a waveform of the control signal SRST, fig. 11C shows a waveform of the reference signal REF, fig. 11D shows a waveform of the pixel signal SIG (voltage VSLA), fig. 11E shows a waveform of the signal CMP output from the
In this read operation D2, the driving
First, at time t31, the
Next, in a period from time T32 to time T34 (conversion period T1), the AD conversion unit ADC performs AD conversion based on the pixel signal SIG. Specifically, at time t32, the
Then, at time t33, the voltage of the reference signal REF falls below the voltage of the pixel signal SIG (fig. 11C and 11D). Accordingly, the
Next, at time T34, the
Next, at time t36, the
Next, at time t37, the
Next, at time t37, the
Next, in a period from time T39 to time T41 (conversion period T2), the AD conversion unit ADC performs AD conversion based on the pixel signal SIG. Specifically, at time t39, the
Then, at time t40, the voltage of the reference signal REF falls below the voltage of the pixel signal SIG (fig. 11C and 11D). Accordingly, the
Next, at time T41, the
Then, at time t43, the
As described above, the
The
The
In other words, since the voltage VSLA is a voltage corresponding to the charge S0 shown in fig. 8A to 8D, the digital code CODEA is a code corresponding to the charge S0. Similarly, since the voltage VSLB is a voltage corresponding to the charge S180 shown in fig. 8A to 8D, the digital code CODEB is a code corresponding to the charge S180. Therefore, a value obtained by subtracting the value indicated by the digital code CODEB from the value indicated by the digital code CODEA corresponds to the signal I
The
Advantageous effects
As described above, according to the present embodiment, the control circuit is provided for each of the plurality of imaging pixels, and based on the voltages VSLA and VSLB supplied from the pixel circuit, the control circuit generates the signals TRG0 and TRG180 supplied to the pixel circuit. Therefore, since the exposure time can be set individually in each of the plurality of imaging pixels, the measurement accuracy of the distance measurement can be improved.
Modified example 1
According to the above-described embodiment, the pixel circuit P100 is configured as shown in fig. 3, but the present disclosure should not be considered to be limited to such a configuration. The distance measuring device 1A according to the present modified example will be described below. The distance measuring apparatus 1A includes an imaging unit 20A. The imaging unit 20A includes a pixel array 21A and a driving unit 22A.
Fig. 12 shows a configuration example of the imaging pixel P in the pixel array 21A. The pixel array 21A includes a plurality of control lines CMRL, a plurality of control lines ISWL, a plurality of control lines OFGL, and a plurality of control lines CTLL. The control line CMRL is adapted to extend in the horizontal direction (lateral direction in fig. 12), and the control signal SCMR is applied to the control line CMRL by the drive unit 22A. The control line ISWL is adapted to extend in the horizontal direction (lateral direction in fig. 12), and the control signal SISW is applied to the control line ISWL by the drive unit 22A. The control line OFGL is adapted to extend in the horizontal direction (lateral direction in fig. 12), and the control signal SOFG is applied to the control line OFGL by the driving unit 22A. The control line CTLL is adapted to extend in the horizontal direction (lateral direction in fig. 12), and the control signal SCTL is applied to the control line CTLL by the driving unit 22A. The imaging pixel P includes a pixel circuit P100A and a control circuit P200A.
The pixel circuit P100A includes transistors CMR, RSTA, RSTB, OFG, ISWA, and ISWB and capacitive elements CAPA and CAPB. In this example, the transistors CMR, RSTA, RSTB, OFG, ISWA, and ISWB are N-type MOS transistors.
The drain of the transistor CMR is supplied with a voltage VDDX, its gate is connected to the control line CMRL, and its source is connected to the node FDO. The drain of the transistor RSTA is supplied with the voltage FBL, the gate thereof is connected to the control line RSTL, and the source thereof is connected to the drain of the transistor ISWA and one end of the capacitive element CAPA. The drain of the transistor RSTB is supplied with a voltage FBL, the gate thereof is connected to the control line RSTL, and the source thereof is connected to the drain of the transistor ISWB and one end of the capacitive element CAPB. The drain of the transistor OFG is connected to the node FDO, the gate thereof is connected to the control line OFGL, and the source thereof is connected to the photodiode PD and the sources of the transistors TGA and TGB. The drain of the transistor ISWA is connected to the source of the transistor RSTA and to one end of the capacitor CAPA, its gate is connected to the control line ISWL, and its source is connected to the floating diffusion FDA, the drain of the transistor TGA and the gate of the transistor AMPA. The drain of the transistor ISWB is connected to the source of the transistor RSTB and one end of the capacitor CAPB, the gate thereof is connected to the control line ISWL, and the source thereof is connected to the floating diffusion FDB, the drain of the transistor TGB, and the gate of the transistor AMPB.
One end of the capacitor element CAPA is connected to the source of the transistor RSTA and the drain of the transistor ISWA, and the other end is connected to the node FDO. One end of the capacitive element CAPB is connected to the source of the transistor RSTB and the drain of the transistor ISWB, and the other end is connected to the node FDO.
The control circuit P200A has AND
As with the driving
Here, the transistor TGA corresponds to a specific example of "first switching transistor" according to the present disclosure. The transistor TGB corresponds to a specific example of the "second switching transistor" according to the present disclosure. The floating diffusion FDA corresponds to a specific example of the "first charge accumulation unit" according to the present disclosure. The floating diffusion FDB corresponds to a specific example of the "second charge accumulation unit" according to the present disclosure. The transistor OFG corresponds to a specific example of "a seventh transistor" according to the present disclosure. The transistor ISWA corresponds to a specific example of "an eighth transistor" according to the present disclosure. The transistor ISWB corresponds to a specific example of "ninth transistor" according to the present disclosure. The transistor CMR corresponds to a specific example of "tenth transistor" according to the present disclosure. The transistor RSTA corresponds to a specific example of the "eleventh transistor" according to the present disclosure. The transistor RSTB corresponds to a specific example of "twelfth transistor" according to the present disclosure. The drive unit 22A corresponds to one specific example of the "second control unit" according to the present disclosure.
Fig. 13A to 13M show an example of the exposure operation D1 in the distance measuring apparatus 1A, in which fig. 13A shows a waveform of a light pulse L1 emitted from the light source 11, fig. 13B shows a waveform of the control signal SISW, fig. 13C shows a waveform of the control signal SCMR, fig. 13D shows a waveform of the control signal SRST, fig. 13E shows a waveform of the control signal SOFG, fig. 13F shows a waveform of the voltage VSLA, fig. 13G shows a waveform of the voltage VSLB, fig. 13H shows a waveform of the control signal SSET, fig. 13I shows a waveform of the control signal SRESET, fig. 13J shows a waveform of the signal QO, fig. 13K shows a waveform of the control signal SCTL, fig. 13L shows a waveform of the signal TRG0, and fig. 13M shows a waveform of the signal TRG 180.
Before time t52, the drive unit 22A sets the voltages of the control signals SISW, SCMR, SRST, and SOFG to a high level (fig. 13B to 13E). Accordingly, the transistors CMR, RSTA, RSTB, OFG, ISWA, and ISWB of the pixel circuit P100A are turned on, the voltage VDDX is supplied to the cathode of the photodiode PD, and the voltage FBL is supplied to the floating diffusions FDA and FDB. The voltages VSLA and VSLB output by the pixel circuit P100A are set to the voltage V1 (fig. 13F and 13G) that depends on the voltage FBL.
Next, at time t51, the drive unit 22A changes the voltage of the control signal SSET from the low level to the high level (fig. 13H). Accordingly, the
In the period from the time t52 to the time t53, the drive unit 22A holds the voltage of the control signal SCTL at a low level (fig. 13K). Therefore, the AND
Next, at time t53, the drive unit 22A changes the voltage of the control signal SCTL from the low level to the high level (fig. 13K). Therefore, in a period (exposure period TB) from time t53 to time t54, the AND
Next, at time t54, the drive unit 22A changes the voltage of the control signal SCTL from a high level to a low level (fig. 13K). Therefore, in the period from the time t54 to the time t55, the AND
Next, at time t55, the drive unit 22A changes the voltage of the control signal SCTL from the low level to the high level (fig. 13K). Therefore, in the period (exposure period TB) from time t55 to time t56, the AND
Subsequently, the distance measuring device 1A alternately repeats the operation in the period from the time t54 to the time t55 and the operation in the period from the time t55 to the time t56 (exposure period TB).
At time t57, the drive unit 22A changes the voltage of the control signal SCTL from the low level to the high level (fig. 13K). Accordingly, the AND
Then, at time t58, voltage VSLA reaches voltage VREF. Accordingly, the
Fig. 14A to 14J show examples of operations in a period from time t54 to time t56 shown in fig. 13A to 13M, in which fig. 14A shows a waveform of a light pulse L1 emitted from the light source 11, fig. 14B shows a waveform of a control signal SISW, fig. 14C shows a waveform of a control signal SCMR, fig. 14D shows a waveform of a control signal SRST, fig. 14E shows a waveform of a control signal SOFG, fig. 14F shows a waveform of a voltage VFDO at a node FDO, fig. 14G shows a waveform of a voltage VSLA, fig. 14H shows a waveform of a voltage VSLB, fig. 14I shows a waveform of a signal TRG0, and fig. 14J shows a waveform of a signal TRG 180.
At time t54, the driving unit 22A changes the voltage of the control signals SCMR, SRST, and SOFG from the low level to the high level (fig. 14C to 14E). Therefore, the transistors CMR, RSTA, RSTB, and OFG are all turned on. Therefore, the voltage VDDX is supplied to the cathode of the photodiode PD via the transistors CMR and OFG. Therefore, the voltage VFDO of the node FDO is set to the voltage VDDX. Further, the voltage across capacitive element CAPA is set to a voltage depending on the voltage difference between voltages FBL and VDDX, and the voltage across capacitive element CAPB is set to a voltage depending on the voltage difference between voltages FBL and VDDX.
Next, at time t61, the drive unit 22A changes the voltage of the control signal SCMR from the high level to the low level (fig. 14C). Thus, transistor CMR is off.
In the period from the time t61 to the time t62, the photodiode PD generates electric charges based on background light. Since the transistor OFG is turned on, the voltage VFDO at the node FDO gradually decreases in accordance with the electric charge generated by the photodiode PD. Therefore, the voltage across the capacitive element CAPA changes, and similarly, the voltage across the capacitive element CAPB changes.
Then, at time t62, the drive unit 22A changes the voltage of the control signal SOFG from the high level to the low level (fig. 14E). Therefore, the transistor OFG is turned off. Therefore, the node FDO becomes a floating state, and subsequently, the voltage across the capacitive element CAPA and the voltage across the capacitive element CAPB are held.
Then, at time t63, the drive unit 22A changes the voltage of the control signal SRST from the high level to the low level (fig. 14D). Thus, both transistors RSTA and RSTB are off.
Next, at time t64, the drive unit 22A changes the voltage of the control signal SCMR from the low level to the high level (fig. 14C). Accordingly, the transistor CMR is turned on, the voltage VDDX is supplied to the node FDO, and the voltage VFDO is set to the voltage VDDX (fig. 14F). In this case, the voltage across the capacitive element CAPA and the voltage across the capacitive element CAPB are held, thereby increasing the voltage across one end of the capacitive element CAPA and the voltage across one end of the capacitive element CAPB.
Next, at time t65, the drive unit 22A changes the voltage of the control signal SISW from the low level to the high level (fig. 14B). Thus, both transistors ISWA and ISWB are turned on, and the voltage at the floating diffusions FDA and FDB increases. Accordingly, the voltages VSLA and VSLB increase (fig. 14F and 14G). The increases in voltages VSLA and VSLB correspond to the amount of change in voltage VDO with respect to voltage VDDX at time t 62. In other words, the increase of the voltages VSLA and VSLB depends on the intensity of the background light.
Next, at time t66, the drive unit 22A changes the voltage of the control signal SISW from the high level to the low level (fig. 14B), and at time t55, the drive unit 22A changes the voltage of the control signal SCMR from the high level to the low level (fig. 14C).
Then, during a subsequent period from the time t55 to the time t56, the light source 11 performs a light emission operation of alternately repeating light emission AND non-light emission (fig. 14A), AND the AND
As described above, in the distance measuring device 1A, the photodiode PD accumulates electric charges based on the background light in the period (background-light exposure period TC) from time t61 to t 62. Then, the pixel circuit P100A increases the voltages of the voltages VSLA and VSLB according to the amount of charge accumulated in the background-light exposure period TC. The time length of the period from the time t61 to the time t62 (background light exposure period TC) is set to the same length as the time length of the period from the time t55 to the time t56 (exposure period TB). Therefore, in the distance measuring device 1A, the component based on the background light, which is included in the voltages VSLA and VSLB obtained in the period from the time t55 to the time t56, can be subtracted. Therefore, the distance measuring device 1A can improve the measurement accuracy of the measurement distance D
<2 > second embodiment
Next, a
The
Fig. 15 shows a configuration example of the pixel array 41. The pixel array 41 includes a plurality of control lines RSTL1, a plurality of control lines RSTL2, a plurality of control lines SELL1, a plurality of control lines SELL2, a plurality of control lines SELCL, a plurality of control lines SETL, a plurality of clock signal lines CKIL, and a plurality of clock signal lines CKQL. The control line RSTL1 is adapted to extend in the horizontal direction (lateral direction in fig. 15), and the control signal SRST1 is applied to the control line RSTL1 by the
The pixel array 41 includes pixel circuits Q110 and Q120 and a control circuit Q200. The pixel circuits Q110 and Q120 and the control circuit Q200 correspond to two imaging pixels Q in the pixel array 41. The pixel circuits Q110 and Q120 have the same circuit configuration as the pixel circuit P100 according to the first embodiment described above.
The pixel circuit Q110 has a photodiode PD1, transistors TGA and TGB, floating diffusions FDA and FDB, transistors RST1, RSTA and RSTB, transistors AMPA and AMPB, and transistors SELA and SELB. The gate of transistor TGA is supplied with signal TRG0 and the gate of transistor TGB is supplied with signal TRG 180. With the transistor SELA2 in the control circuit Q200 on and the transistor SELA1 off, the transistor AMPA provides the voltage VSLA to the control circuit Q200 according to the voltage at the floating diffusion FDA. Further, in the case where the transistor SELB2 in the control circuit Q200 is on and the transistor SELB is off, the transistor AMPB supplies the voltage VSLB to the control circuit Q200 in accordance with the voltage at the floating diffusion FDB.
The pixel circuit Q120 has a photodiode PD2, transistors TGC and TGD, floating diffusions FDC and FDD, a transistor RST2, RSTC and RSTD, transistors AMPC and AMPD, and transistors SELC and SELD. The gate of the transistor TGC is supplied with a signal TRG90 and the gate of the transistor TGD is supplied with a signal TRG 270. In the case where the transistor SELC2 (described later) in the control circuit Q200 is turned on and the transistor SELC is turned off, the transistor AMPC supplies the voltage VSLC to the control circuit Q200 in accordance with the voltage at the floating diffusion FDC. Further, in the case where a transistor SELD2 (described later) in the control circuit Q200 is turned on and the transistor SELD is turned off, the transistor AMPD supplies the control circuit Q200 with the voltage VSLD according to the voltage at the floating diffusion FDD.
The control circuit Q200 has transistors SELA2, SELB2, SELC2, AND SELD2,
The gate of the transistor SELA2 is connected to a control line SELCL, and the drain thereof is connected to the source of the transistor AMPA in the pixel circuit Q110 and the drain of the transistor SELA therein.
A gate of the transistor SELB2 is connected to a control line SELCL, and a drain thereof is connected to a source of the transistor AMPB in the pixel circuit Q110 and a drain of the transistor SELB therein.
The transistor SELC2 has a gate connected to a control line SELCL, a drain connected to the source of the transistor AMPC in the pixel circuit Q120 and the drain of the transistor SELC therein, and a source connected to the current source 101C and the
The gate of the transistor SELD2 is connected to a control line SELCL, the drain thereof is connected to the source of the transistor AMPD in the pixel circuit Q120 and the drain of the transistor SELD therein, and the source thereof is connected to the
The
The
The AND
The driving
The processing unit 44 is adapted to generate a distance image PIC, in which each pixel value indicates the value of the distance D, based on the image signal DATA0, and output the distance image PIC as the image signal DATA.
Here, the photodiode PD1 corresponds to a specific example of "first light receiving element" according to the present disclosure. The photodiode PD2 corresponds to a specific example of "second light receiving element" according to the present disclosure. The floating diffusions FDC and FDD correspond to specific examples of "a plurality of second accumulation units" according to the present disclosure. The transistors TGC and TGD correspond to a specific example of "a plurality of second transistors" according to the present disclosure. The transistors AMPC, SELC, AMPD, and SELD correspond to specific examples of "a plurality of second output units" according to the present disclosure. The control circuit Q200 corresponds to a specific example of "first control unit" according to the present disclosure. The
Next, the exposure operation D1 in the
Fig. 16A to 16L show examples of the exposure operation D1 in the
Before time t72, the
Next, at time t71, the
Next, at time t72, the
In this way, the exposure period TB starts at this time t 72. In this exposure period TB, the photodiodes PD1 and PD2 generate electric charges based on the light pulse L2 that depends on the reflection of the light pulse L1. In the pixel circuit Q110, the transistor TGA is turned on and off based on the signal TRG0, and the transistor TGB is turned on and off based on the signal TRG 180. In other words, one of the transistors TRA and TRB is on. Accordingly, the electric charges generated by the photodiode PD1 are selectively accumulated in the floating diffusion FDA and the floating diffusion FDB. Similarly, in the pixel circuit Q120, the transistor TGC is turned on and off based on the signal TRG90, and the transistor TGD is turned on and off based on the signal TRG 270. In other words, one of the transistors TRC and TRD is on. Accordingly, the electric charges generated by the photodiode PD2 are selectively accumulated in the floating diffusion FDC and the floating diffusion FDD.
Fig. 17A to 17F show operation examples of the imaging pixels Q1 and Q2, in which fig. 17A shows a waveform of a light pulse L1, fig. 17B shows a waveform of a reflected light pulse L2 received by the photodiodes PD1 and PD2, fig. 17C shows a waveform of a signal TRG0, fig. 17D shows a waveform of a signal TRG180, fig. 17E shows a waveform of a signal TRG90, and fig. 17F shows a waveform of a signal TRG 270. In this example, the photodiode PD1 of the pixel circuit Q110 and the photodiode PD2 of the pixel circuit Q120 receive substantially the same reflected light pulse L2 (fig. 17B). In this example, at time t81, the light pulse L1 rises, the signal TRG0 rises, and the signal TRG180 falls. Then, at time t83 where the phase is delayed from time t81 by "pi/2", the signal TRG90 rises and the signal TRG270 falls. Then, at time t84 where the phase is delayed from time t83 by "pi/2", the optical pulse L1 falls, the signal TRG0 falls, and the signal TRG180 rises. Then, at time t86 where the phase is delayed from time t84 by "pi/2", the signal TRG90 falls and the signal TRG270 rises.
In this example, the transistor TGA transfers the charge generated by the photodiode PD1 to the floating diffusion FDA in a period from time t82 to time t84, and the transistor TGB transfers the charge generated by the photodiode PD1 to the floating diffusion FDB in a period from time t84 to time t 85. Therefore, in the period from the time t82 to the time t84, the charge S0 is accumulated in the floating diffusion FDA, and in the period from the time t84 to the time t85, the charge S180 is accumulated in the floating diffusion FDB.
Further, in a period from time t82 to time t83, the transistor TGD transfers the electric charge generated by the photodiode PD2 to the floating diffusion FDD, and in a period from time t83 to time t85, the transistor TGC transfers the electric charge generated by the photodiode PD2 to the floating diffusion FDC. Therefore, in the period from time t82 to time t83, the charge S270 is accumulated in the floating diffusion FDD, and in the period from time t83 to time t85, the charge S90 is accumulated in the floating diffusion FDC.
Signal I as the difference between charge S0 and charge S180(S0-S180) according to phase
FIGS. 18 and 19 show the signal IAnd Q
In phaseIn the case of "0" (zero), the signal IIs "1". Then, when the phase is changedWhen changing from "0" (zero) to "pi", the signal IDecreases in a linear fashion, changing from "1" to "-1". Then, when the phase is changed
In addition, in phaseIn the case of "0" (zero), the signal Q
As shown in fig. 19, signal QAnd signal IRatio (Q) between
As shown in fig. 16A to 16L and fig. 17A to 17F, the imaging pixels Q1 and Q2 repeat the operation at time t81 to time t 87. Accordingly, the charge S0 is repeatedly accumulated in the floating diffusion FDA, the charge S180 is repeatedly accumulated in the floating diffusion FDB, the charge S90 is repeatedly accumulated in the floating diffusion FDC, and the charge S270 is repeatedly accumulated in the floating diffusion FDD. Therefore, the voltages of the floating diffusions FDA, FDB, FDC, and FDD gradually decrease. Therefore, the voltages VSLA, VSLB, VSLC, and VSLD also gradually decrease (fig. 16C). In this example, voltage VSLA varies to a higher degree than voltages VSLB, VSLC, and VSLD.
Then, at time t73, voltage VSLA reaches voltage VREF. Therefore, the
Then, at time t74, the light source 11 terminates the light emitting operation (fig. 16A).
The
The processing unit 44 obtains pixel values in the imaging pixels Q1 and Q2 based on the digital codes CODEA, CODEB, CODEC, and CODED included in the
As described above, the
Further, in the
Further, in the
As described above, according to the present embodiment, the four signals TRG0, TRG90, TRG180, and TRG270 are used, and thus the measurable distance can be extended.
According to the present embodiment, the exposure time in the pixel circuit operated based on the signals TRG0 and TRG180 and the exposure time in the pixel circuit operated based on the signals TRG90 and TRG270 are equal to each other, and therefore the measurement accuracy in distance measurement can be improved.
According to this embodiment mode, one control circuit is provided for two pixel circuits, and thus the circuit scale can be reduced.
Modified example 2
According to the above embodiment, as shown in fig. 15, four
Fig. 20 shows a configuration example of a main portion of the control circuit Q200A according to the present modified example. Fig. 20 shows a part of the control circuit Q200 shown in fig. 15, corresponding to the four
The control circuit Q200A includes transistors 111A through 111D, current sources 112A through 112D, and a comparator 120. The comparator 120 includes capacitance elements 121 and 122, transistors 123 to 126, switches 127 and 128, and a current source 129. The transistors 111A to 111D, 123, and 124 are P-type MOS transistors, and the transistors 125 and 126 are N-type MOS transistors.
The gate of transistor 111A is supplied with voltage VSLA, its source is connected to node N1, and its drain is connected to ground. The gate of transistor 111A is connected to, for example, the source of
The gate of the transistor 111B is supplied with the voltage VSLB, the source thereof is connected to the node N1, and the drain thereof is grounded. The gate of transistor 111B is connected to, for example, the source of
The gate of transistor 111C is supplied with voltage VSLC, its source is connected to node N1, and its drain is grounded. The gate of transistor 111C is connected to, for example, the source of
The gate of transistor 111D is supplied with voltage VSLD, its source is connected to node N1, and its drain is grounded. The gate of transistor 111D is connected to, for example, the source of
One end of the capacitive element 121 is connected to the node N1, and the other end is connected to the gate of the transistor 125 and one end of the switch 127. One terminal of the capacitance element 122 is supplied with a voltage VREF, and the other terminal is connected to a gate of the transistor 126 and one terminal of the switch 128.
A gate of the transistor 123 is connected to a gate of the transistor 124, drains of the transistors 124 and 126, and the other end of the switch 128, a source thereof is supplied with the power supply voltage VDD, and a drain thereof is connected to a drain of the transistor 125, the other end of the switch 127, and the
A gate of the transistor 125 is connected to the other end of the capacitive element 121 and one end of the switch 127, a drain thereof is connected to the drain of the transistor 123, the other end of the switch 127, and the
One end of the switch 127 is connected to the other end of the capacitor element 121 and the gate of the transistor 125, and the other end is connected to the drains of the transistors 123 and 125 and the
The reset terminal of
As shown in fig. 20, sources of the four transistors 111A to 111D are connected to each other. Therefore, a voltage corresponding to the lowest voltage of the four voltages VSLA to VSLD appears at the node N1. Then, the comparator 120 compares the voltage at the node N1 with the voltage VREF, thereby generating the control signal SRESET. The control circuit Q200A is configured as just described, thereby making it possible to reduce the number of comparators.
Fig. 21 shows a configuration example of a main portion of another control circuit Q200B according to the present modified example. Fig. 21 shows a part of the control circuit Q200 shown in fig. 15, corresponding to the four
The control circuit Q200B includes a comparator 130. The comparator 130 includes capacitance elements 131A to 131D, transistors 132A to 132D and 133A to 133D, switches 134A to 134D, a current source CS, a capacitance element 135, a transistor 136, a switch 137, and transistors 138 and 139. The transistors 132A to 132D and 133A to 133D and 136 are P-type MOS transistors, and the transistors 138 and 139 are N-type MOS transistors.
One end of the capacitor 131A is supplied with the voltage VSLA, and the other end thereof is connected to the gate of the transistor 132A and one end of the switch 134A. One end of the capacitance element 131A is connected to, for example, a source of the
One end of the capacitor 131B is supplied with a voltage VSLB, and the other end thereof is connected to the gate of the transistor 132B and one end of the switch 134B. One end of the capacitance element 131B is connected to, for example, a source of the
One end of the capacitor element 131C is supplied with a voltage VSLC, and the other end thereof is connected to the gate of the transistor 132C and one end of the switch 134C. One end of the capacitance element 131C is connected to, for example, a source of the
One end of the capacitor element 131D is supplied with a voltage VSLD, and the other end thereof is connected to the gate of the transistor 132D and one end of the switch 134D. One end of the capacitor element 131D is connected to, for example, a source of the
The transistors 133A to 133D are provided so that a voltage for setting the exposure time can be selected from the four voltages VSLA to VSLD. For example, by setting the voltages of the signals SWA and SWB to a low level (active) and setting the voltages of the signals SWC and SWD to a high level (inactive), the exposure time can be set based on the voltages VSLA and VSLB supplied from the pixel circuit Q110.
One terminal of the current source CS is supplied with the power supply voltage VDD, and the other terminal thereof is connected to the sources of the transistors 132A to 123D and the source of the transistor 136.
One end of the capacitance element 135 is supplied with a voltage VREF, and the other end thereof is connected to a gate of the transistor 136 and one end of the switch 137. A gate of the transistor 136 is connected to the other end of the capacitive element 135 and one end of the switch 137, a source thereof is connected to the sources of the transistors 132A to 132D and the other end of the current source CS, and a drain thereof is connected to a drain of the transistor 139, gates of the transistors 138 and 139, and the other end of the switch 137. One end of the switch 137 is connected to the other end of the capacitive element 135 and the gate of the transistor 136, and the other end thereof is connected to the drains of the transistors 136 and 139 and the gates of the transistors 138 and 139.
A gate of the transistor 138 is connected to a gate of the transistor 139, drains of the transistors 136 and 139, and the other end of the switch 137, a drain thereof is connected to the node N2, and a source thereof is grounded. A gate of the transistor 139 is connected to the gate of the transistor 138, the drains of the transistors 136 and 139, and the other end of the switch 137, a drain thereof is connected to the gates of the transistors 138 and 139, the drain of the transistor 136, and the other end of the switch 137, and a source thereof is grounded.
For example, in the exposure operation D1, the switches 134A to 134D and 137 are turned on during a period in which the control signal SRST (control signals SRST1, SRST2) is at a high level, and are turned off in other periods in which the control signal SRST (control signals SRST1, SRST2) is at a low level.
Here, the transistors 132A, 132B, 132C, and 132D correspond to a specific example of "a plurality of third transistors" according to the present disclosure. The transistor 136 corresponds to a specific example of "a sixth transistor" according to the present disclosure. The capacitive elements 131A, 131B, 131C, and 131D correspond to specific examples of "a plurality of third capacitive elements" according to the present disclosure. The capacitive element 135 corresponds to a specific example of "fourth capacitive element" according to the present disclosure.
As shown in fig. 21, the sources of the four transistors 132A to 132D are connected to each other. Accordingly, the comparator 130 compares the lowest voltage of the four voltages VSLA to VSLD with the voltage VREF, thereby generating the control signal SRESET. The control circuit Q200B is configured as just described, thereby making it possible to reduce the number of comparators.
Other modified examples
The modified example of the first embodiment can be applied to the
<3 > third embodiment
Next, the distance measuring device 3 according to the third embodiment will be described. The present embodiment is adapted to set the exposure time in the imaging pixel based on the four voltages VSLA, VSLB, VSLC, and VSLD supplied from one pixel circuit. Note that substantially the same configurations as those in the
The distance measuring device 3 includes an imaging unit 50 as shown in fig. 1. As shown in fig. 2, the imaging unit 50 includes a pixel array 51, a driving unit 52, and a processing unit 54.
Fig. 22 shows a configuration example of the pixel array 51. The pixel array 51 includes a plurality of control lines RSTL1, a plurality of control lines RSTL2, a plurality of control lines SELL1, a plurality of control lines SELL2, a plurality of control lines SELCL, a plurality of control lines SETL, a plurality of clock signal lines CKAL, a plurality of clock signal lines CKBL, a plurality of clock signal lines CKCL, and a plurality of clock signal lines CKDL. The clock signal line CKAL is adapted to extend in the horizontal direction (lateral direction in fig. 22), and the driving unit 52 applies the clock signal SCKA to the clock signal line CKAL. The clock signal line CKBL is adapted to extend in the horizontal direction (lateral direction in fig. 22), and the driving unit 52 applies the clock signal SCKB to the clock signal line CKBL. The clock signal line CKCL is adapted to extend in the horizontal direction (the lateral direction in fig. 22), and the driving unit 52 applies the clock signal SCKC to the clock signal line CKCL. The clock signal line CKDL is adapted to extend in the horizontal direction (the lateral direction in fig. 22), and the drive unit 52 applies the clock signal SCKD to the clock signal line CKDL. The clock signals SCKA to SCKD are signals having a duty ratio of 25%. The clock signal SCKC is a signal phase-delayed by 90 ° from the clock signal SCKA, the clock signal SCKB is a signal phase-delayed by 90 ° from the clock signal SCKC, and the clock signal SCKD is a signal phase-delayed by 90 ° from the clock signal SCKB.
The pixel array 51 includes a pixel circuit R100 and a control circuit R200. The pixel circuit R100 and the control circuit R200 correspond to an imaging pixel R in the pixel array 51.
The pixel circuit R100 has a photodiode PD, transistors TGA, TGB, TGC, and TGD, floating diffusions FDA, FDB, FDC, and FDD, transistors RST, RSTA, RSTB, RSTC, and RSTD, transistors AMPA, AMPB, AMPC, and AMPD, and transistors SELA, SELB, SELC, and SELD.
The gate of the transistor TGA is supplied with a signal TRG0, the source of which is connected to the cathode of the photodiode PD and the sources of the transistors TGB, TGC, TGD and RST, and the drain of which is connected to the floating diffusion FDA, the source of the transistor RSTA and the gate of the transistor AMPA.
The gate of the transistor TGB is supplied with a signal TRG180, the source thereof is connected to the cathode of the photodiode PD and the sources of the transistors TGA, TGC, TGD and RST, and the drain thereof is connected to the floating diffusion FDB, the source of the transistor RSTB and the gate of the transistor AMPB.
The gate of the transistor TGC is supplied with a signal TRG90, the source thereof is connected to the cathode of the photodiode PD and the sources of the transistors TGA, TGB, TGD and RST, and the drain thereof is connected to the floating diffusion FDC, the source of the transistor RSTC and the gate of the transistor AMPC.
The gate of the transistor TGD is supplied with a signal TRG270, the source thereof is connected to the cathode of the photodiode PD and the sources of the transistors TGA, TGB, TGC and RST, and the drain thereof is connected to the source of the floating diffusion FDD, the transistor RSTD and the gate of the transistor AMPD.
The control circuit R200 has transistors SELA2, SELB2, SELC2, AND SELD2,
The AND circuit 115A is adapted to obtain a logical product of the signal QO AND the clock signal SCKA, thereby generating a
The driving unit 52 is adapted to drive the plurality of imaging pixels R based on an instruction from the
The processing unit 54 is adapted to generate a distance image PIC, in which each pixel value indicates a value of the distance D, based on the image signal DATA0, and the processing unit 54 outputs the distance image PIC as the image signal DATA.
Here, the photodiode PD corresponds to a specific example of "first light receiving element" according to the present disclosure. The floating diffusions FDA, FDB, FDC, and FDD correspond to specific examples of "a plurality of first accumulation units" according to the present disclosure. The transistors TGA, TGB, TGC, and TGD correspond to specific examples of "a plurality of first transistors" according to the present disclosure. The transistors AMPA, SELA, AMPB, SELB, AMPC, SELC, AMPD, and SELD correspond to specific examples of the "plurality of first output units" according to the present disclosure. The control circuit R200 corresponds to a specific example of "first control unit" according to the present disclosure. The AND circuits 115A, 115B, 115C, AND 115D correspond to specific examples of "driving units" according to the present disclosure.
Next, the exposure operation D1 in the distance measuring device 3 will be described in detail. Focusing on a certain imaging pixel R1 among the plurality of imaging pixels R, the exposure operation D1 associated with the imaging pixel R1 will be described in detail below.
Fig. 23A to 23K show examples of the exposure operation D1 in the distance measuring device 3, in which fig. 23A shows a waveform of the light pulse L1 emitted from the light source 11, fig. 23B shows waveforms of the control signals SRST (control signals SRST1, SRST2), fig. 23C shows waveforms of the voltages VSLA, VSLB, VSLC, and VSLD, fig. 23D shows a waveform of the control signal SSET, fig. 23E shows a waveform of the control signal SRESET, fig. 23F shows a waveform of the signal QO, fig. 23G shows a waveform of the clock signal SCKA, fig. 23H shows a waveform of the signal TRG0, fig. 23I shows a waveform of the signal TRG90, fig. 23J shows a waveform of the signal TRG180, and fig. 23K shows a waveform of the signal TRG 270.
Before time t92, the drive unit 52 sets the voltages of the control signals SRST1 and SRST2 to the high level (fig. 23B). Accordingly, the transistors RST, RSTA, RSTB, RSTC, and RSTD of the pixel circuit R100 are turned on, the voltage VRSTX is supplied to the cathode of the photodiode PD, and the voltage VRST is supplied to the floating diffusions FDA, FDB, FDC, and FDD. Therefore, the voltages VSLA, VSLB, VSLC, and VSLD output by the pixel circuit R100 are each set to the voltage V1 (fig. 23C) according to the voltage VRST.
Next, at time t91, the driving unit 52 changes the voltage of the control signal SSET from the low level to the high level (fig. 23D). Accordingly, the
Next, at time t92, the driving unit 52 changes the voltage of the control signal SSET from the high level to the low level (fig. 23D). Further, at time t92, the drive unit 52 changes the voltages of the control signals SRST1 and SRST2 from the high level to the low level (fig. 23B). Accordingly, the transistors RST, RSTA, RSTB, RSTC, and RSTD of the pixel circuit R100 are all turned off. Further, at this time t92, the light source 11 starts the light emission operation of alternately repeating light emission and non-light emission (fig. 23A). As shown in fig. 23A and 23G, the frequency of the light emitting operation of the light source 11 is equal to the frequency of the clock signal SCKA, and the phase of the light pulse L1 and the phase of the clock signal SCKA coincide with each other. As a result, the phase of the optical pulse L1 is synchronized with the phases of the signals TRG0, TRG90, TRG180, and TRG 270.
In this way, the exposure period TB starts at time t 92. In this exposure period TB, the photodiode PD generates electric charges based on the reflected light pulse L2 that depends on the light pulse L1. In the pixel circuit R100, the transistor TGA is turned on and off based on the signal TRG0, the transistor TGB is turned on and off based on the signal TRG180, the transistor TGC is turned on and off based on the signal TRG90, and the transistor TGD is turned on and off based on the signal TRG 270. In other words, any one of the transistors TRA, TRB, TRC, and TRD is turned on. Accordingly, the electric charges generated by the photodiode PD are selectively accumulated in the floating diffusions FDA, FDB, FDC, and FDD.
Fig. 24A to 24F show operation examples of the imaging pixel R1, in which fig. 24A shows a waveform of the light pulse L1, fig. 24B shows a waveform of the reflected light pulse L2 received by the photodiode PD, fig. 24C shows a waveform of the signal TRG0, fig. 24D shows a waveform of the signal TRG180, fig. 24E shows a waveform of the signal TRG90, and fig. 24F shows a waveform of the signal TRG 270. In this example, at time t101, light pulse L1 rises, signal TRG0 rises, and signal TRG270 falls. Then, at time t103 where the phase is delayed by "pi/2" from time t101, the signal TRG0 falls, and the signal TRG90 rises. Then, at time t104 where the phase is delayed from time t103 by "pi/2", the optical pulse L1 falls, the signal TRG90 falls, and the signal TRG180 rises. Then, at time t106 where the phase is delayed by "π/2" from time t104, signal TRG180 falls and signal TRG270 rises.
In this example, the transistor TGA transfers the charge generated by the photodiode PD to the floating diffusion FDA in a period from time t102 to time t103, the transistor TGC transfers the charge generated by the photodiode PD to the floating diffusion FDC in a period from time t103 to time t104, and the transistor TGB transfers the charge generated by the photodiode PD to the floating diffusion FDB in a period from time t104 to time t 105. Therefore, the charge S0 is accumulated in the floating diffusion FDA in the period from the time t102 to the time t103, the charge S90 is accumulated in the floating diffusion FDC in the period from the time t103 to the time t104, and the charge S180 is accumulated in the floating diffusion FDB in the period from the time t104 to the time t 105.
FIGS. 25A-25E show the charges S0, S180, S90, and S270 and the signal I accumulated in the floating diffusions FDA, FDB, FDC, and FDDAnd QWhere fig. 25A shows the charge S0 accumulated in the floating diffusion FDA and fig. 25B shows the charge accumulated in the floating diffusion FDBS180, fig. 25C shows the charge S90 accumulated in the floating diffusion FDC, fig. 25D shows the charge S270 accumulated in the floating diffusion FDD, and fig. 25E shows the signal I And QExamples of (2).
When phase position
When phase position
The processing unit 54 may be based on the signal I
As shown in fig. 23A to 23K and fig. 24A to 24F, the imaging pixel R1 repeats the operation at time t101 to time t 107. Accordingly, the charge S0 is repeatedly accumulated in the floating diffusion FDA, the charge S180 is repeatedly accumulated in the floating diffusion FDB, the charge S90 is repeatedly accumulated in the floating diffusion FDC, and the charge S270 is repeatedly accumulated in the floating diffusion FDD. Therefore, the voltages of the floating diffusions FDA, FDB, FDC, and FDD are gradually decreased. Therefore, the voltages VSLA, VSLB, VSLC, and VSLD also gradually decrease (fig. 23C). In this example, voltage VSLA varies to a higher degree than voltages VSLB, VSLC, and VSLD.
Then, at time t93, voltage VSLA reaches voltage VREF. Therefore, the
Then, at time t94, the light source 11 terminates the light emitting operation (fig. 23A).
The
The processing unit 54 obtains a pixel value in the imaging pixel R1 based on the digital codes CODEA, CODEB, CODEC, and CODED included in the
As described above, the distance measuring device 3 is adapted to set the exposure time in the pixel circuit R100 based on the four voltages VSLA, VSLB, VSLC, and VSLD supplied from one pixel circuit R100. Therefore, the measurement accuracy of the measurement distance D can be improved. In other words, for example, in the
As described above, according to the present embodiment, the exposure time in the pixel circuit is set based on the four voltages supplied from one pixel circuit, so that the measurement accuracy of the measurement distance can be improved.
Modified example 3
The clock signals SCKA to SCKD having a duty ratio of 25% are used in the above embodiment, but the present disclosure is not limited thereto. The distance measuring device 3A according to the present modified example will be described below. The distance measuring device 3A includes an imaging unit 50A. The imaging unit 50A includes a pixel array 51A, a driving unit 52A, and a processing unit 54A.
Fig. 26 shows a configuration example of the pixel array 51A. The pixel array 51A includes a plurality of clock signal lines CKIL, a plurality of clock signal lines CKQL, and a plurality of control lines CTLL. The clock signal line CKIL is adapted to extend in the horizontal direction (lateral direction in fig. 26), and the driving unit 52A applies the clock signal SCKI to the clock signal line CKIL. The clock signal line CKQL is adapted to extend in the horizontal direction (lateral direction in fig. 26), and the driving unit 52A applies the clock signal SCKQ to the clock signal line CKQL. The control line CTLL is adapted to extend in the horizontal direction (lateral direction in fig. 26), and the drive unit 52A applies a control signal SCTL to the control line CTLL. The pixel array 51A includes a pixel circuit R100 and a control circuit R200A.
The control circuit R200A has AND circuits 117A, 117B, 117C, AND 117D. The AND circuit 117A is adapted to obtain a logical product (AND) of the signal QO, the clock signal SCKI, AND the control signal SCTL, thereby generating a
As with the driving unit 52 according to the above-described embodiment, the driving unit 52A is adapted to drive the plurality of imaging pixels R based on an instruction from the
Fig. 27A to 27L show an example of the exposure operation D1 in the distance measuring apparatus 3A, in which fig. 27A shows a waveform of the light pulse L1 emitted from the light source 11, fig. 27B shows waveforms of the control signals SRST (control signals SRST1, SRST2), fig. 27C shows waveforms of the voltages VSLA, VSLB, VSLC, and VSLD, fig. 27D shows a waveform of the control signal SSET, fig. 27E shows a waveform of the control signal SRESET, fig. 27F shows a waveform of the signal QO, fig. 27G shows a waveform of the clock signal SCTL, fig. 27H shows a waveform of the clock signal SCKI, fig. 27I shows a waveform of the signal TRG0, fig. 27J shows a waveform of the signal TRG90, fig. 27K shows a waveform of the signal TRG180, and fig. 27L shows a waveform of the signal TRG 270.
Before time t112, the drive unit 52A sets the voltages of the control signals SRST1 and SRST2 to the high level (fig. 27B). Accordingly, the transistors RST, RSTA, RSTB, RSTC, and RSTD of the pixel circuit R100 are turned on, the voltage VRSTX is supplied to the cathode of the photodiode PD, and the voltage VRST is supplied to the floating diffusions FDA, FDB, FDC, and FDD. The voltages VSLA, VSLB, VSLC, and VSLD output from the pixel circuit R100 are set to the voltage V1 according to the voltage VRST (fig. 27C).
Next, at time t111, the driving unit 52A changes the voltage of the control signal SSET from the low level to the high level (fig. 27D). Accordingly, the
Next, at time t112, the driving unit 52A changes the voltage of the control signal SSET from the high level to the low level (fig. 27D). Further, at time t112, the driving unit 52A changes the voltages of the control signals SRST1 and SRST2 from the high level to the low level (fig. 27B). Accordingly, the transistors RST, RSTA, RSTB, RSTC, and RSTD of the pixel circuit R100 are all turned off. Further, at this time t112, the light source 11 starts a light emission operation of alternately repeating light emission and non-light emission (fig. 27A). As shown in fig. 27A and 27H, the frequency of the light emitting operation of the light source 11 is equal to the frequency of the clock signal SCKA, and the phase of the light pulse L1 and the phase of the clock signal SCKA coincide with each other. In this way, the exposure period TB starts at this time t 112.
At time t112, the driving unit 52A changes the voltage of the control signal SCTL from a low level to a high level. Therefore, in the period from the time t112 to the time t113, the AND circuit 117A outputs the clock signal SCKI as the signal TRG0, AND the AND circuit 117B outputs the inverted signal of the clock signal SCKI as the signal TRG180 (fig. 27I AND 27K). On the other hand, the AND circuit 117C holds the voltage of the signal TRG90 at a low level, AND the AND circuit 117D holds the voltage of the signal TRG270 at a low level (fig. 27J AND 27L). Accordingly, the photodiode PD generates charges based on the reflected light pulse L2, and the floating diffusions FDA and FDB accumulate the charges generated by the photodiode PD. Then, the voltages VSLA and VSLB are varied according to the voltages at the floating diffusions FDA and FDB, respectively (fig. 28C). Voltages VSLC and VSLD maintain almost the same voltage.
Fig. 28A to 28D show an operation example of the imaging pixel R1 in a period from time t112 to time t113, in which fig. 28A shows a waveform of the light pulse L1, fig. 28B shows a waveform of the reflected light pulse L2, fig. 28C shows a waveform of the signal TRG0, and fig. 28D shows a waveform of the signal TRG 180. The charge S0 is accumulated in the floating diffusion FDA in the period from time t122 to time t123, and the charge S180 is accumulated in the floating diffusion FDB in the period from time t123 to time t 124.
At time t113, the driving unit 52A changes the voltage of the control signal SCTL from a high level to a low level. Therefore, in the period from the time t113 to the time t114, the AND circuit 117C outputs the clock signal SCKQ as the signal TRG90, AND the AND circuit 117D outputs the inverted signal of the clock signal SCKQ as the signal TRG270 (fig. 27J AND 27L). On the other hand, the AND circuit 117A holds the voltage of the signal TRG0 at a low level, AND the AND circuit 117B holds the voltage of the signal TRG180 at a low level (fig. 27I AND 27K). Accordingly, the photodiode PD generates charges based on the reflected light pulse L2, and the floating diffusions FDC and FDD accumulate the charges generated by the photodiode PD. Then, voltages VSLC and VSLD change according to the voltages at the floating diffusions FDC and FDD, respectively (fig. 28C). Voltages VSLA and VSLB are maintained at almost the same voltage.
Fig. 29A to 29D show an operation example of the imaging pixel R1 in a period from time t112 to time t113, in which fig. 29A shows a waveform of the light pulse L1, fig. 29B shows a waveform of the reflected light pulse L2, fig. 29C shows a waveform of the signal TRG0, and fig. 29D shows a waveform of the signal TRG 180. In the period from time t132 to time t133, the charge S270 is accumulated in the floating diffusion FDD, and in the period from time t133 to time t135, the charge S90 is accumulated in the floating diffusion FDC.
Subsequently, the distance measuring device 3A alternately repeats the operation in the period from the time t112 to the time t113 and the operation in the period from the time t113 to the time t 114.
At time t116, the driving unit 52A changes the voltage of the control signal SCTL from the low level to the high level (fig. 27G). Accordingly, the AND circuit 117A starts outputting the clock signal SCKI as the signal TRG0, AND the AND circuit 117B starts outputting the inverted signal of the clock signal SCKI as the signal TRG180 (fig. 27I AND fig. 27K). On the other hand, the AND circuit 117C holds the voltage of the signal TRG90 at a low level, AND the AND circuit 117D holds the voltage of the signal TRG270 at a low level (fig. 27J AND 27L). Therefore, the voltages VSLA and VSLB vary according to the voltages at the floating diffusions FDA and FDB, respectively (fig. 13F and 13G). Voltages VSLC and VSLD are maintained at approximately the same voltage.
Then, at time t117, voltage VSLA reaches voltage VREF. Accordingly, the
Even the foregoing configuration can achieve advantageous effects similar to those in the case of the above-described embodiment.
Other modified examples
The modified example of the first embodiment may be applied to the distance measuring device 3 according to the above-described embodiment, or the modified example of the second embodiment may be applied thereto.
Although the present technology has been described above with reference to several embodiments and modification examples, the present technology is not limited to these embodiments and the like, and various modifications may be made thereto.
For example, as shown in fig. 30, the distance measuring apparatus 1 (fig. 3) according to the first embodiment is adapted to provide one control circuit P200 for one pixel circuit P100. Then, the pixel circuit P100 is adapted to supply the voltages VSLA and VSLB to the control circuit P200, and the control circuit P200 is adapted to generate the signals TRG0 and TRG180 based on the voltages VSLA and VSLB, and supply these signals TRG0 and TRG180 to the pixel circuit P100. Further, the distance measuring device 2 (fig. 15) according to the second embodiment is adapted to provide one control circuit Q200 for two pixel circuits Q110, Q120, as shown in fig. 31. Then, the pixel circuit Q110 is adapted to supply the voltages VSLA and VSLB to the control circuit Q200, the pixel circuit Q120 is adapted to supply the voltages VSLC and VSLD to the control circuit Q200, and the control circuit Q200 is adapted to generate the signals TRG0, TRG90, TRG180, and TRG270 based on the voltages VSLA, VSLB, VSLC, and VSLD, supply the signals TRG0 and TRG180 to the pixel circuit Q110, and supply the signals TRG90 and TRG270 to the pixel circuit Q120. The present technology should not be considered to be limited to the foregoing embodiments, but one control circuit may be provided for three or more pixel circuits, for example. For example, in the example of fig. 32, one control circuit Q210 is provided for four pixel circuits Q110, Q120, Q130, and Q140. In this example, the pixel circuits Q110 and Q120 operate based on the signals TRG0 and TRG180, and the pixel circuits Q130 and Q140 operate based on the signals TRG90 and TRG 270. The control circuit Q210 generates signals TRG0, TRG90, TRG180, and TRG270 based on eight voltages supplied from the pixel circuits Q110, Q120, Q130, and Q140. Specifically, the control circuit Q210 sets all of the signals TRG0, TRG90, TRG180, and TRG270 to a low level in the case where at least one of the eight voltages reaches the voltage VREF. The control circuit Q210 may be adapted to have eight comparators 102, for example, as in the case of the second embodiment (fig. 15), or to have one comparator according to the configuration shown in fig. 20 and 21. Further, for example, as shown in fig. 33, the control circuit Q210 is provided with a
Further, for example, as shown in fig. 34, the distance measuring apparatus 3 (fig. 22) according to the third embodiment is adapted to provide one control circuit R200 for one pixel circuit R100. Then, the pixel circuit R100 is adapted to supply the voltages VSLA, VSLB, VSLC, and VSLD to the control circuit R200, and the control circuit R200 is adapted to generate the signals TRG0, TRG180, and TRG270 based on the voltages VSLA, VSLB, VSLC, and VSLD, and supply the signals TRG0, TRG180, and TRG270 to the pixel circuit R100. Even in this case, for example, one control circuit may be provided for two or more pixel circuits. For example, in the example of fig. 35, one control circuit R210 is provided for two pixel circuits R100 and R110. In this example, the pixel circuits R100 and R110 operate based on the signals TRG0, TRG90, TRG180, and TRG 270. The control circuit R210 generates signals TRG0, TRG90, TRG180, and TRG270 based on eight voltages supplied from the pixel circuits R100 and R110. Specifically, the control circuit R210 sets all of the signals TRG0, TRG90, TRG180, and TRG270 to the low level in the case where at least one of the eight voltages reaches the voltage VREF. The control circuit R210 may be adapted to have eight comparators 102 as in the case of the third embodiment (fig. 22), for example, or to have one comparator according to the configuration shown in fig. 20 and 21. Further, for example, like the control circuit Q200 shown in fig. 33, the control circuit R210 is provided with a
Note that the advantageous effects described in this specification are merely examples, should not be considered as limiting, and other effects may be provided.
Note that the present technology can be configured as follows.
(1) A time-of-flight sensor, comprising:
a light receiving element;
a first signal line and a second signal line;
a first transistor in electrical communication with the light receiving element, the first transistor including a first gate in electrical communication with a first signal line;
a second transistor in electrical communication with the light receiving element, the second transistor including a second gate in electrical communication with a second signal line; and
a control circuit comprising at least one comparator, wherein the control circuit is in electrical communication with the first and second signal lines.
(2) The time of flight sensor of (1), wherein the at least one comparator comprises a first comparator and a second comparator, wherein the first and second comparators are configured to receive a reference voltage.
(3) The time-of-flight sensor of (2), wherein the control circuit further comprises:
a NAND circuit in electrical communication with the first and second comparators;
a latch in electrical communication with the NAND circuit, a first AND circuit, AND a second AND circuit, wherein the first AND circuit is in electrical communication with the first signal line AND the second AND circuit is in electrical communication with the second signal line.
(4) The time-of-flight sensor according to (1), further comprising:
a first capacitor in electrical communication with the light receiving element via a first transistor; and
a second capacitor in electrical communication with the light receiving element via the second transistor.
(5) The time-of-flight sensor according to (1), further comprising:
a first semiconductor substrate on which the light receiving element, the first transistor, and the second transistor are formed; and
a second semiconductor substrate, wherein the control circuit is formed on the second semiconductor substrate.
(6) The time-of-flight sensor according to (5), wherein the first semiconductor substrate is stacked on the second semiconductor substrate.
(7) The time-of-flight sensor according to (1), further comprising:
a first capacitor in electrical communication with the light receiving element;
a third signal line configured to supply a first voltage based on an amount of charge stored by the first capacitive element; and
a first analog-to-digital converter in electrical communication with the third signal line.
(8) The time-of-flight sensor according to (7), further comprising:
a second capacitor in electrical communication with the light receiving element, wherein the first capacitor is in electrical communication with the light receiving element via a first transistor, and the second capacitor is in electrical communication with the light receiving element via a second transistor;
A fourth signal line configured to supply a second voltage based on the amount of charge stored by the second capacitive element; and
a second analog-to-digital converter in electrical communication with the fourth signal line.
(9) The time-of-flight sensor according to (1), further comprising:
a second light receiving element;
a third signal line and a fourth signal line;
a third transistor in electrical communication with the second light receiving element, the third transistor including a third gate in electrical communication with a third signal line;
a fourth transistor in electrical communication with the second light-receiving element, the fourth transistor including a fourth gate in electrical communication with a fourth signal line; and is
The control circuit is in electrical communication with the third and fourth signal lines.
(10) The time of flight sensor of (9), wherein the control circuit comprises a second comparator and a third comparator, wherein the second and third comparators are configured to receive a reference voltage.
(11) The time of flight sensor of (9), wherein the control circuit comprises a voltage selector in communication with the first, second, third and fourth signal lines.
(12) A distance measuring device comprising:
a light source and a light source control unit in communication with the light source;
An imaging unit comprising:
a light receiving element;
a first signal line and a second signal line;
a first transistor in electrical communication with the light receiving element, the first transistor including a first gate in electrical communication with a first signal line;
a second transistor in electrical communication with the light receiving element, the second transistor including a second gate in electrical communication with a second signal line; and
a control circuit comprising at least one comparator, wherein the control circuit is in electrical communication with the first and second signal lines; and
a control unit in communication with the light source control unit and the imaging unit.
(13) The distance measurement device of (12), wherein the at least one comparator comprises a first comparator and a second comparator, wherein the first and second comparators are configured to receive a reference voltage.
(14) The distance measuring device according to (13), wherein the control circuit further includes:
a NAND circuit in electrical communication with the first and second comparators;
a latch in electrical communication with the NAND circuit, a first AND circuit, AND a second AND circuit, wherein the first AND circuit is in electrical communication with the first signal line AND the second AND circuit is in electrical communication with the second signal line.
(15) The distance measuring apparatus according to (12), further comprising:
a first capacitor in electrical communication with the light receiving element via a first transistor; and
a second capacitor in electrical communication with the light receiving element via the second transistor.
(16) The distance measuring apparatus according to (12), further comprising:
a first semiconductor substrate on which the light receiving element, the first transistor, and the second transistor are formed; and
a second semiconductor substrate, wherein the control circuit is formed on the second semiconductor substrate.
(17) The distance measurement device according to (16), wherein the first semiconductor substrate is stacked on the second semiconductor substrate.
(18) The distance measuring apparatus according to (12), further comprising:
a first capacitor in electrical communication with the light receiving element;
a third signal line configured to supply a first voltage based on an amount of charge stored by the first capacitive element; and
a first analog-to-digital converter in electrical communication with the third signal line.
(19) The distance measuring apparatus according to (18), further comprising:
a second capacitor in electrical communication with the light receiving element, wherein the first capacitor is in electrical communication with the light receiving element via a first transistor, and the second capacitor is in electrical communication with the light receiving element via a second transistor;
A fourth signal line configured to supply a second voltage based on the amount of charge stored by the second capacitive element; and
a second analog-to-digital converter in electrical communication with the fourth signal line.
(20) The distance measuring apparatus according to (12), further comprising:
a second light receiving element;
a third signal line and a fourth signal line;
a third transistor in electrical communication with the second light receiving element, the third transistor including a third gate in electrical communication with a third signal line;
a fourth transistor in electrical communication with the second light-receiving element, the fourth transistor including a fourth gate in electrical communication with a fourth signal line; and is
The control circuit is in electrical communication with the third and fourth signal lines.
(21) The distance measurement device of (20), wherein the control circuit comprises a second comparator and a third comparator, wherein the second and third comparators are configured to receive a reference voltage.
(22) The distance measurement device of (20), wherein the control circuit includes a voltage selector in communication with the first, second, third, and fourth signal lines.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made in accordance with design requirements and other factors insofar as they come within the scope of the appended claims or the equivalents thereof.
List of reference numerals
1 to 3 distance measuring device
11 light source
12 light source control unit
13 optical system
14 control unit
20. 40, 50 imaging unit
21. 41, 51 pixel array
22. 42, 52 drive unit
24. 44, 54 processing unit
25 imaging control unit
26 reference signal generating unit
30 reading unit
31. 32 capacitance element
33 current source
34 comparator
35 counter
36 latch
101A, 101B, 101C, 101D current source
102A, 102B, 102C, 102D comparators
103. 113 NAND circuit
104 latch
105A, 105B, 105C, 105D, 107A, 107B, 115A, 115B, 115C, 115D, 117A, 117B, 117C, 117CAND circuit
111A, 111B, 111C transistors
112A, 112B, 112C current source
120 comparator
121. 122 capacitive element
123 to 126 transistors
127. 128 switch
129 current source
130 comparator
131A, 131B, 131C, 131D capacitive element
132A, 132B, 132C, 132D, 133A, 133B, 133C, 133D transistors
134A, 134B, 134C, 134D switch
135 capacitor element
136 transistor
137 switch
138. 139 transistor
201. 202 semiconductor substrate
211 selector
AMPA, AMPB, AMPC, AMPD, CMR, ISWA, ISWB, OFG, RST1, RST2, RSTA, RSTB, RSTC, RSTD, SELA2, SELB2, SELC2, SELD2, TGA, TGB, TGC, TGD transistors
BUS BUS routing
CC. SCMR, SCTL, SISW, SOFG, SRESET, SRST, SSEL, SSELC, SSET, SSW control signals
Clock signal lines CKAL, CKBL, CKCL, CKDL, CKIL, CKL and CKQL
CLK, SCK, SCKA, SCKB, SCKC, SCKD, SCKI, SCKQ clock signals
CMP、COA、COB、COC、COD、QO, TRG0, TRG90, TRG180, TRG270 signals
CNT count value
CS current source
CTLL, RSTL, SELL, SELCL, SETL control lines
DATA, DATA0 image signal
D1 Exposure operation
D2 read operation
FDA, FDB, FDC, FDD floating diffusion
L1 light pulse
Light pulse reflected by L2
P, Q, R imaging pixel
PD, PD1, PD2 photodiode
P100、P100A、Q110、Q120、Q130、Q140
R100, R110 pixel circuit
P200, P200A, Q200, Q210, R200A, R210 control circuit
REF reference signal
SGL, SGLA, SGLB signal line
SIG pixel signal
S1 imaging surface
S0, S90, S180, S270 charges
TA Exposure time period
TB exposure period
TC background light Exposure time period
T1, T2 transition periods
VDD Power supply Voltage
VREF, VRST, VRSTX, VSLA, VSLB, VSLC, VSLD voltage
Phase position
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