阅读说明：本技术 一种相控阵雷达系统高精度同步方法 (High-precision synchronization method for phased array radar system ) 是由 王帅 王子彤 李朋 于 2020-07-08 设计创作，主要内容包括：一种相控阵雷达系统高精度同步方法,处理卡上的FPGA芯片Ⅱ通过与TR组件连接的单条同步信号线计算处理卡到不同TR组件的延迟时间可将不同TR组件的发射延迟时差控制到FPGA的最高工作频率的单个时钟周期内,结构简单,TR组件间的延迟可控,降低了板卡间的布线数量。可将处理卡到不同TR组件间的时延精度,控制在FPGA可工作的最小时钟周期内,精度较高且可控,使得处理卡到不同TR组件间的通信线缆,不再局限到等长设计中,降低了开发和布设难度,实用性高。(A high-precision synchronization method for a phased array radar system is characterized in that an FPGA chip II on a processing card calculates delay time from the processing card to different TR components through a single synchronization signal line connected with the TR components, the transmission delay time difference of the different TR components can be controlled to be within a single clock period of the highest working frequency of the FPGA, the structure is simple, the delay among the TR components is controllable, and the wiring quantity among board cards is reduced. The time delay precision from the processing card to different TR components can be controlled in the minimum clock period in which the FPGA can work, the precision is higher and controllable, so that the communication cables from the processing card to the different TR components are not limited to isometric design, the development and layout difficulty is reduced, and the practicability is high.)

1. A high-precision synchronization method for a phased array radar system is characterized by comprising the following steps:

a) the method comprises the following steps that a processing card and a central control machine are arranged, an FPGA chip II, a DDR cache chip II connected with the FPGA chip II and a clock source II are arranged in the processing card, the FPGA chip II is connected with an FPGA chip I of N TR components, the TR components are provided with an FPGA chip I, an AD module, a DA module and the DDR cache chip I connected with the FPGA chip I, N is a positive integer larger than or equal to 2, each TR component is connected with a clock source I, the clock source I provides clock signals with the same source and the same frequency for each TR component, and each TR component is connected with a receiving and transmitting antenna;

b) sending a synchronous pulse signal of a clock period sent by a clock source II to a TR component by using the highest clock frequency of the running of the FPGA chip II in the processing card, starting counting, feeding back a pulse signal of a single clock period to the processing card by the FPGA chip I at the same frequency after the TR component receives the synchronous pulse signal, stopping counting after the FPGA chip II in the processing card receives the fed-back pulse signal, and recording the delay time of the TR component through an internal register of the FPGA chip II;

c) repeating the step b) until the delay time of the N TR components is obtained, and storing and recording the delay time through an internal register of the FPGA chip II;

d) the processing card stores the recorded delay time of each TR component in an internal register of the FPGA chip II and sends the delay time to an FPGA chip I of each TR component, and each TR component records the delay time to an internal register of the FPGA chip I;

e) the central control machine issues a working state control instruction to the processing card, the processing card generates a DDS waveform signal through the FPGA chip II, and the processing card sends the DDS waveform signal to the N TR components and caches the DDS waveform signal through the DDR cache chip I in the TR components;

f) the processing card simultaneously generates and issues synchronous trigger signals of all TR components through the FPGA chip II;

g) after receiving the synchronous trigger signal, the TR component reads a corresponding DDS waveform signal from the DDR cache chip I according to delay time delay recorded in an internal register of the FPGA chip I, the AD module performs digital-to-analog conversion on the read DDS waveform signal and then sends the converted DDS waveform signal to the receiving and sending antenna, and the receiving and sending antenna forms antenna beams by signals sent by the N TR components.

2. The highly accurate synchronized phased array radar system of claim 1, wherein: the FPGA chip I in the processing card and the FPGA chip II in the TR component are chips with the same model.

3. The highly accurate synchronized phased array radar system of claim 1, wherein: GTH interfaces are arranged on the processing card and the TR component, and the GTH interface of the processing card is connected with the GTH interface of the TR component through optical fibers.

4. The highly accurate synchronized phased array radar system of claim 1, wherein: the method comprises the following steps that when echo signals need to be sampled, the processing card sends synchronous trigger signals to the N TR assemblies, the TR assemblies receive the trigger signals and sample signal waveforms through the DA module and send the signal waveforms to the processing card after the trigger signals are delayed according to delay time recorded in the register in the FPGA chip I, and the signal waveforms sampled by the processing card are stored in the DDR cache chip II and then sent to the central control machine.

Technical Field

The invention relates to the technical field of phased array radars, in particular to a high-precision synchronization method for a phased array radar system.

Background

The antenna unit of the phased array radar is composed of a plurality of TR components, and different phase signals transmitted by each TR component influence the finally generated antenna beam. Most of the current TR component synchronization modes are pulse triggering modes with uncontrollable time delay, the requirements on wiring and circuit design are high, and the condition of unstable synchronization exists.

Disclosure of Invention

In order to overcome the defects of the technology, the invention provides a high-precision synchronization method of a phased array radar system.

The technical scheme adopted by the invention for overcoming the technical problems is as follows:

a high-precision synchronization method for a phased array radar system comprises the following steps:

a) the method comprises the following steps that a processing card and a central control machine are arranged, an FPGA chip II, a DDR cache chip II connected with the FPGA chip II and a clock source II are arranged in the processing card, the FPGA chip II is connected with an FPGA chip I of N TR components, the TR components are provided with an FPGA chip I, an AD module, a DA module and the DDR cache chip I connected with the FPGA chip I, N is a positive integer larger than or equal to 2, each TR component is connected with a clock source I, the clock source I provides clock signals with the same source and the same frequency for each TR component, and each TR component is connected with a receiving and transmitting antenna;

b) sending a synchronous pulse signal of a clock period sent by a clock source II to a TR component by using the highest clock frequency of the running of the FPGA chip II in the processing card, starting counting, feeding back a pulse signal of a single clock period to the processing card by the FPGA chip I at the same frequency after the TR component receives the synchronous pulse signal, stopping counting after the FPGA chip II in the processing card receives the fed-back pulse signal, and recording the delay time of the TR component through an internal register of the FPGA chip II;

c) repeating the step b) until the delay time of the N TR components is obtained, and storing and recording the delay time through an internal register of the FPGA chip II;

d) the processing card stores the recorded delay time of each TR component in an internal register of the FPGA chip II and sends the delay time to an FPGA chip I of each TR component, and each TR component records the delay time to an internal register of the FPGA chip I;

e) the central control machine issues a working state control instruction to the processing card, the processing card generates a DDS waveform signal through the FPGA chip II, and the processing card sends the DDS waveform signal to the N TR components and caches the DDS waveform signal through the DDR cache chip I in the TR components;

f) the processing card simultaneously generates and issues synchronous trigger signals of all TR components through the FPGA chip II;

g) after receiving the synchronous trigger signal, the TR component reads a corresponding DDS waveform signal from the DDR cache chip I according to delay time delay recorded in an internal register of the FPGA chip I, the AD module performs digital-to-analog conversion on the read DDS waveform signal and then sends the converted DDS waveform signal to the receiving and sending antenna, and the receiving and sending antenna forms antenna beams by signals sent by the N TR components.

Preferably, the FPGA chip I in the processing card and the FPGA chip II in the TR component are chips with the same model.

Preferably, both the processing card and the TR component are provided with GTH interfaces, and the GTH interface of the processing card and the GTH interface of the TR component are connected by an optical fiber.

And further, the method comprises the following steps that when echo signals need to be sampled, the processing card sends synchronous trigger signals to the N TR components, the TR components receive the trigger signals and sample signal waveforms through the DA module and send the signal waveforms to the processing card after the trigger signals are delayed according to delay time recorded in an internal register of the FPGA chip I, and the signal waveforms sampled by the processing card are stored in the DDR cache chip II and then sent to the central control computer.

The invention has the beneficial effects that: the FPGA chip II on the processing card calculates the delay time from the processing card to different TR components through a single synchronous signal wire connected with the TR components, the transmission delay time difference of the different TR components can be controlled to be within a single clock period of the highest working frequency of the FPGA, the structure is simple, the delay among the TR components is controllable, and the wiring quantity among the board cards is reduced. The time delay precision from the processing card to different TR components can be controlled in the minimum clock period in which the FPGA can work, the precision is higher and controllable, so that the communication cables from the processing card to the different TR components are not limited to isometric design, the development and layout difficulty is reduced, and the practicability is high.

Drawings

FIG. 1 is a system block diagram of the present invention.

Detailed Description

The invention is further described below with reference to fig. 1.

A high-precision synchronization method for a phased array radar system comprises the following steps:

a) the method comprises the following steps that a processing card and a central control machine are arranged, an FPGA chip II, a DDR cache chip II connected with the FPGA chip II and a clock source II are arranged in the processing card, the FPGA chip II is connected with an FPGA chip I of N TR components, the TR components are provided with an FPGA chip I, an AD module, a DA module and the DDR cache chip I connected with the FPGA chip I, N is a positive integer larger than or equal to 2, each TR component is connected with a clock source I, the clock source I provides clock signals with the same source and the same frequency for each TR component, and each TR component is connected with a receiving and transmitting antenna;

b) sending a synchronous pulse signal of a clock period sent by a clock source II to a TR component by using the highest clock frequency of the running of the FPGA chip II in the processing card, starting counting, feeding back a pulse signal of a single clock period to the processing card by the FPGA chip I at the same frequency after the TR component receives the synchronous pulse signal, stopping counting after the FPGA chip II in the processing card receives the fed-back pulse signal, and recording the delay time of the TR component through an internal register of the FPGA chip II;

c) repeating the step b) until the delay time of the N TR components is obtained, and storing and recording the delay time through an internal register of the FPGA chip II;

d) the processing card stores the recorded delay time of each TR component in an internal register of the FPGA chip II and sends the delay time to an FPGA chip I of each TR component, and each TR component records the delay time to an internal register of the FPGA chip I;

e) the central control machine issues a working state control instruction to the processing card, the processing card generates a DDS waveform signal through the FPGA chip II, and the processing card sends the DDS waveform signal to the N TR components and caches the DDS waveform signal through the DDR cache chip I in the TR components;

f) the processing card simultaneously generates and issues synchronous trigger signals of all TR components through the FPGA chip II;

g) after receiving the synchronous trigger signal, the TR component reads a corresponding DDS waveform signal from the DDR cache chip I according to delay time delay recorded in an internal register of the FPGA chip I, the AD module performs digital-to-analog conversion on the read DDS waveform signal and then sends the converted DDS waveform signal to the receiving and sending antenna, and the receiving and sending antenna forms antenna beams by signals sent by the N TR components.

The FPGA chip II on the processing card calculates the delay time from the processing card to different TR components through a single synchronous signal wire connected with the TR components, the transmission delay time difference of the different TR components can be controlled to be within a single clock period of the highest working frequency of the FPGA, the structure is simple, the delay among the TR components is controllable, and the wiring quantity among the board cards is reduced. The time delay precision from the processing card to different TR components can be controlled in the minimum clock period in which the FPGA can work, the precision is higher and controllable, so that the communication cables from the processing card to the different TR components are not limited to isometric design, the development and layout difficulty is reduced, and the practicability is high.

Furthermore, the FPGA chip I in the processing card and the FPGA chip II in the TR component are chips with the same model.

Furthermore, GTH interfaces are arranged on the processing card and the TR component, and the GTH interface of the processing card is connected with the GTH interface of the TR component through an optical fiber.

And further, the method comprises the following steps that when echo signals need to be sampled, the processing card sends synchronous trigger signals to the N TR components, the TR components receive the trigger signals and sample signal waveforms through the DA module and send the signal waveforms to the processing card after the trigger signals are delayed according to delay time recorded in an internal register of the FPGA chip I, and the signal waveforms sampled by the processing card are stored in the DDR cache chip II and then sent to the central control computer.

The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.