阅读说明：本技术 基于射频片上系统rfsoc的小型捷变频相控阵雷达 (Small frequency agility phased array radar based on Radio Frequency System On Chip (RFSOC) ) 是由 肖国尧 吴彬彬 全英汇 邢孟道 别博文 冯伟 柯华锋 于 2020-06-05 设计创作，主要内容包括：本发明公开了一种基于射频片上系统RFSOC的小型捷变频相控阵雷达,主要解决现有雷达体积大、带宽小、发射波形有限的问题。其包含程序加载单元、缓存单元、光通信单元、时钟单元、射频片上系统RFSOC、八个巴伦、四个射频前端模块和四个天线子阵列。RFSOC通过不同的接口分别与程序加载单元、缓存单元、光通信单元、时钟单元、巴伦、射频前端模块连接；每个射频前端模块通过模拟差分接口与一个发射通道的巴伦和一个接收通道的巴伦连接,通过模拟差分接口与时钟单元连接,通过SMP射频接插件与对应的一个天线子阵列连接。本发明减少了雷达体积,提高了信号带宽,并能灵活产生捷变频雷达信号,可用于机载和星载平台上的雷达系统。(The invention discloses a small-sized frequency agile phased array radar based on a Radio Frequency System On Chip (RFSOC), which mainly solves the problems of large volume, small bandwidth and limited transmitting waveform of the conventional radar. The system comprises a program loading unit, a cache unit, an optical communication unit, a clock unit, a Radio Frequency System On Chip (RFSOC), eight baluns, four radio frequency front-end modules and four antenna sub-arrays. The RFSOC is respectively connected with the program loading unit, the cache unit, the optical communication unit, the clock unit, the balun and the radio frequency front end module through different interfaces; each radio frequency front end module is connected with the balun of one transmitting channel and the balun of one receiving channel through an analog differential interface, connected with the clock unit through the analog differential interface and connected with a corresponding antenna sub-array through the SMP radio frequency connector. The invention reduces the volume of the radar, improves the signal bandwidth, can flexibly generate frequency agile radar signals, and can be used for radar systems on airborne and spaceborne platforms.)

1. A small-sized frequency agile phased array radar based on a Radio Frequency System On Chip (RFSOC) comprises a program loading unit (1), a cache unit (2), an optical communication unit (3) and a clock unit (4), and is characterized by further comprising a Radio Frequency System On Chip (RFSOC) (5), eight baluns (6), four radio frequency front-end modules (7) and four antenna sub-arrays (8);

the radio frequency system-on-chip RFSOC (5) is used for digital signal processing, intermediate frequency signal generation and intermediate frequency signal receiving, is bidirectionally connected with the program loading unit (1) through a CFI (computational fluid interface), is bidirectionally connected with the cache unit (2) through a DDR (double data rate) 4 interface, is bidirectionally connected with the optical communication unit (3) through an IIC (inter integrated circuit) interface and a GTH (global GTH) interface, is unidirectionally connected with the clock unit (5) through an analog differential interface, unidirectionally connected with each balun (6) through an analog differential interface, and bidirectionally connected with each radio frequency front-end module (7) through an SPI (serial peripheral interface);

each radio frequency front-end module (7) is respectively connected with the balun (6) of one transmitting channel and the balun (6) of one receiving channel in a single direction through an analog differential interface, is connected with the clock unit (5) in a single direction through the analog differential interface, and is connected with one corresponding antenna sub-array (8) through the SMP radio frequency connector.

2. Radar according to claim 1, characterised in that the optical communication unit (3), used for interconversion of high speed digital electrical and optical signals, enables fibre channel data transmission, of the type HTG8503-MH-T001 YY.

3. Radar according to claim 1, characterised in that the clock unit (4) is adapted to generate a digital-to-analog converter DAC sampling clock for the radio frequency system-on-chip RFSOC (5), an analog-to-digital converter ADC sampling clock for the radio frequency system-on-chip RFSOC (5), a baseband clock for the radio frequency system-on-chip RFSOC (5) and a mixed local oscillator clock for the four radio frequency front end modules (7), the phase difference of these clocks being constant during each radar run.

4. Radar according to claim 1, characterised in that the radio frequency system on chip RFSOC (5) employs model XCZU43DR-2FFVG1517I chip.

5. Radar according to claim 1, characterised in that eight baluns (6) are provided for converting the differential analogue signals of the transmit and receive paths of the intermediate frequency signal into single ended analogue signals, each balun (6) being a balun consisting of a magnetic loop and a cable, of the type TCM1-83X +.

6. Radar according to claim 1, characterised in that the four radio frequency front end modules (7), which are structurally identical, are each used for signal amplification and beam forming; each radio frequency front end module (7) comprises 1 one-to-sixteen power division network, 16 up-converters, 16 down-converters, 16 low-pass filters, 16 band-pass filters, 32 attenuators, 32 phase shifters, 16 power amplifiers, 16 low noise amplifiers and 33 radio frequency switches, the working modes of the modules are divided into a transmitting mode and a receiving mode, and the switching of the working modes is realized by switching the radio frequency switches.

7. Radar according to claim 1, characterised in that the four antenna sub-arrays (8) are identical in structure, each antenna sub-array (8) being composed of 4 x 4 two-dimensional antenna elements.

Technical Field

The invention belongs to the technical field of electronic information, and particularly relates to a frequency agile phased array radar device which can be used for radar systems on airborne and spaceborne platforms.

Background

The phased array radar carries out rapid pointing of the transmitting wave beam and the receiving wave beam by changing the phase and the amplitude of the transmitting and receiving signals of each antenna unit of the antenna array, so that the phased array radar has the advantages of high scanning speed and strong multi-target tracking capability and anti-interference capability. The frequency agility technology enables enemies to difficultly intercept radar signals by agile carrier frequency between transmitted signal pulses, and can also obviously improve the anti-interference capability.

At present, most of the commonly used phased array radar devices are digital intermediate frequency architectures based on a high-speed digital-to-analog converter (DAC) or a direct frequency synthesizer (DDS). And then the up-down frequency conversion from the intermediate frequency to the radio frequency is realized by a mixer in the transmitting and receiving T/R assembly, and the beam control is realized by a phase shifter and an attenuator in the T/R assembly. The phased array radar device has the following disadvantages:

the system has a large volume, needs to be externally connected with a plurality of high-speed digital-to-analog converters (DAC) or direct frequency synthesizers (DDS), increases the number of components and causes the large volume of the system.

And secondly, the signal bandwidth is small and is influenced by the speed of a digital interface, the sampling rates of the high-speed digital-to-analog converter DAC and the high-speed analog-to-digital converter ADC are not high enough, and the intermediate frequency bandwidth is limited.

Thirdly, rapid frequency agility waveform with coherent pulses is difficult to realize, due to limited intermediate frequency bandwidth, frequency agility in a large range is difficult to realize at intermediate frequency, and if frequency agility is realized at a radio frequency part, the complexity of a system is greatly increased.

Disclosure of Invention

The invention aims to provide a small frequency agile phased array radar device based on an RFSOC (radio frequency soc) to reduce the system volume, increase the signal bandwidth and flexibly generate various rapid frequency agile waveforms with coherent pulses in order to overcome the defects of the prior art.

In order to achieve the purpose, the small-sized frequency agile phased array radar device based on the Radio Frequency System On Chip (RFSOC) comprises a program loading unit, a cache unit, an optical communication unit and a clock unit, and is characterized by further comprising the Radio Frequency System On Chip (RFSOC), eight baluns, four radio frequency front-end modules and four antenna sub-arrays;

the RFSOC is bidirectionally connected with the program loading unit through a CFI interface, is bidirectionally connected with the cache unit through a DDR4 interface, is bidirectionally connected with the optical communication unit through an IIC interface and a GTH interface, is unidirectionally connected with the clock unit through an analog differential line, is unidirectionally connected with each balun through an analog differential line, and is bidirectionally connected with each radio frequency front-end module through an SPI interface;

each radio frequency front-end module is respectively connected with the balun of one transmitting channel and the balun of one receiving channel in a unidirectional mode through analog differential interfaces, is connected with the clock unit in a unidirectional mode through analog differential lines, and is connected with one corresponding antenna sub-array through an SMP radio frequency connector.

Compared with the prior art, the invention has the following advantages:

firstly, the volume is small: the invention does not need to be externally connected with an analog-digital converter (ADC), a digital-analog converter (DAC) or a direct frequency synthesizer (DDS), greatly reduces the number of devices and is beneficial to miniaturization design.

Second, the signal bandwidth is large: the invention greatly improves the sampling rate and the bandwidth and enlarges the frequency agility range of the intermediate frequency signal due to the use of the radio frequency system on chip RFSOC integrated with the kilomega data converter.

Thirdly, the flexibility is high: the radio frequency system-on-chip RFSOC used by the invention is integrated with a digital down-conversion DDC unit and a digital up-conversion DUC unit, and can flexibly and rapidly generate and process various coherent radar signals.

Fourthly, the channel utilization rate is high: the invention realizes the expansion of the digital intermediate frequency channel through the power distribution network at the front end of the radio frequency, and then realizes the waveform control of each antenna unit by the attenuator and the phase shifter controlled by software, thereby greatly improving the utilization rate of the digital intermediate frequency channel.

Drawings

FIG. 1 is a block diagram of the overall structure of the present invention;

fig. 2 is a block diagram of an rf front-end module according to the present invention.

Detailed Description

The invention is described in detail below with reference to the following figures and examples:

referring to fig. 1, the small-sized agile frequency conversion phased array radar device based on the radio frequency system on chip RFSOC of the present invention includes a program loading unit 1, a buffer unit 2, an optical communication unit 3, a clock unit 4, a radio frequency system on chip RFSOC 5, eight baluns 6, four radio frequency front end modules 7, and four antenna sub-arrays 8, wherein:

the program loading unit 1 is used for storing a curing program of the radio frequency system on chip RFSOC 5, and the Flash loading chip of the model MT25QU01GBBB8E12 of the magnesium optical Micron company is adopted in this example, but not limited thereto.

The buffer unit 2 is configured to store waveform data, intermediate variables, and digital beam forming weights of the RFSOC 5 on the radio frequency chip, and in this example, but not limited to, 4 sheets of MT40a512M16JY-075E model of magnetrons Micron company are adopted, each chip has a capacity of 512M, and 4 chips constitute a SDRAM buffer unit with a capacity of 1G.

The optical communication unit 3 is used for interconversion between high-speed digital electrical signals and optical signals to realize data transmission of an optical fiber channel, and the model is not limited to the model HTG8503-MH-T001YY of the medium navigation electro-optical company, which is a high-performance 12-channel parallel optical transceiver module, the central wavelength of the optical channel is 850nm, and the single-channel transmission rate is 10.3125 Gbps. The optical communication unit 4 is connected with the radio frequency system on chip RFSOC 5 through the IIC interface and realizes initialization configuration, and is connected with the radio frequency system on chip RFSOC 5 through the Aurora interface and realizes data receiving and transmitting.

The clock unit 4 is configured to generate a DAC sampling clock of the rf system-on-chip RFSOC 5, an ADC sampling clock of the rf system-on-chip RFSOC 5, a baseband clock of the rf system-on-chip RFSOC 5, and a mixing local oscillator clock of the rf front-end module 7, where each of the clocks must be homologous.

The RF system-on-chip RFSOC 5 is used for digital signal processing, intermediate frequency signal generation and intermediate frequency signal reception, and the model of the RF system-on-chip RFSOC is XCZU43DR-2FFVG1517I, but is not limited to the X-ray tube of Xilinx corporation. Four 14-bit-precision digital-to-analog converters (DAC) and four 14-bit-precision analog-to-digital converters (ADC) are integrated in a chip, and a digital up-conversion (DUC) unit and a digital down-conversion (DDC) unit are integrated, wherein each DAC has a sampling rate of 10GSPS and an analog bandwidth of 6GHz, and each ADC has a sampling rate of 5GSPS and an analog bandwidth of 6 GHz. The digital interfaces of the peripheral equipment comprise a common flash memory CFI interface, a double-speed DDR4 interface, an integrated circuit bus IIC interface, a serial peripheral SPI interface and an analog differential interface. The radio frequency system on chip RFSOC 5 is bidirectionally connected with the program loading unit 1 through a CFI interface, is bidirectionally connected with the cache unit 2 through a DDR4 interface, is bidirectionally connected with the optical communication unit 3 through an IIC interface and a GTH interface, is unidirectionally connected with the clock unit 4 through an analog differential interface, is unidirectionally connected with each balun 6 through an analog differential interface, and is bidirectionally connected with each radio frequency front-end module 7 through an SPI interface;

the eight baluns 6 are used for converting differential analog signals of a transmitting channel and a receiving channel of an intermediate frequency signal into a single-ended analog signal, each balun 6 is a balun composed of a magnetic ring and a cable, the embodiment adopts but is not limited to a TCM1-83X + model of Mini-Circuits company, the working frequency range of the balun 6 is 10MHz to 8GHz, and the characteristic impedance is 50 ohms. In a transmitting channel, a digital-to-analog converter DAC (digital-to-analog converter) of a radio frequency system-on-chip (RFSOC 5) outputs a differential analog signal, the differential analog signal is converted into a single-ended analog signal after passing through a balun (6), and the single-ended analog signal is transmitted to an input end of the transmitting channel of a radio frequency front-end module 7; in a receiving channel, a single-ended analog signal is generated at the output end of the receiving channel of the radio frequency front-end module 7, and is converted into a differential analog signal after passing through the balun 6, and then is sent to an analog-to-digital converter ADC of the radio frequency system on chip RFSOC 5.

The four radio frequency front end modules 7 have the same structure and are all used for signal amplification and beam synthesis.

Referring to fig. 2, each rf front-end module 7 includes 1 one-to-sixteen power division network, 16 up-converters, 16 down-converters, 16 low-pass filters, 16 band-pass filters, 32 attenuators, 32 phase shifters, 16 power amplifiers, 16 low noise amplifiers, and 33 rf switches, and the operation modes thereof are divided into a transmission mode and a reception mode, and switching of the operation modes is achieved by switching the rf switches. In a transmitting mode, signals enter a power distribution network from an input end of a transmitting channel to generate 16 signals with equal amplitude and equal phase, then up-conversion, low-pass filtering, attenuation, phase shift and power amplification are sequentially realized, and finally 16 transmitting signals are output; in a receiving mode, signals enter from 16 antenna ports respectively, low-noise amplification, phase shift, attenuation, down-conversion and band-pass filtering are realized respectively, and finally the 16 signals are added in a power division network to synthesize 1-path signal and output. Each radio frequency front-end module 7 is respectively connected with the balun 6 of one transmitting channel and the balun 6 of one receiving channel in a single direction through an analog differential interface, is connected with the clock unit 4 in a single direction through the analog differential interface, and is connected with a corresponding antenna sub-array 8 through an SMP radio frequency connector.

The four antenna sub-arrays 8 have the same structure, are 4 × 4 two-dimensional antenna unit arrays, and respectively correspond to the four radio frequency front-end modules 7.

The working principle of the invention is as follows:

transmitting a radar waveform: the radio frequency system on chip RFSOC 5 receives the baseband data sent from the optical communication unit 3, generates four paths of baseband digital signals after a series of processing, converts the baseband data into digital intermediate frequency signals through a digital up-conversion unit DUC, converts the digital intermediate frequency signals into differential analog intermediate frequency signals through a digital-to-analog converter DAC, and outputs the differential analog intermediate frequency signals through a radio frequency system on chip RFSOC 5 pin; the differential analog intermediate frequency signal is converted into a single-ended analog intermediate frequency signal through a balun 6 and then is sent to the input end of a transmitting channel of a radio frequency front end module 7; the RFSOC 5 switches the four radio frequency front end modules 7 to a transmitting mode through the SPI interface and controls the numerical values of a phase shifter and an attenuator of each radio frequency front end module 7 according to the calculated digital beam forming weight; each single-ended analog intermediate-frequency signal passes through a power division network in the radio frequency front-end module 7 to generate sixteen equiamplitude equal-phase signals, and the sixteen equal-amplitude equal-phase signals are respectively subjected to up-conversion, low-pass filtering, attenuation, phase shifting and power amplification in sequence and finally output sixteen transmitting signals; and finally, outputting the signals to each antenna subarray 8 through an SMP interface, and transmitting the signals to a space to form a transmission beam.

Receiving a radar waveform: the four antenna sub-arrays 8 receive electromagnetic waves from the space and convert the electromagnetic waves into receiving radio frequency analog signals in a current mode; the RFSOC 5 switches the four radio frequency front end modules 7 to a receiving mode through the SPI interface and controls the numerical values of a phase shifter and an attenuator of each radio frequency front end module 7 according to the calculated digital beam forming weight; the received radio frequency analog signals are sent to a corresponding radio frequency front end module 7 through an SMP interface, and sixteen paths of signals are added in the radio frequency front end module 7 through low noise amplification, phase shifting, attenuation, down conversion, band-pass filtering; then, converting the single-end analog signal into a differential analog signal through a balun 6, and inputting the differential analog signal into an analog-to-digital converter ADC of a radio frequency system-on-chip RFSOC 5 to convert the differential analog signal into a digital signal; finally, the radio frequency system on chip RFSOC 5 realizes digital down-conversion DDC, beam direction estimation and receiving beam synthesis according to the digital signals.

The foregoing description is only an example of the present invention and is not intended to limit the invention, so that it will be apparent to those skilled in the art that various changes and modifications in form and detail may be made therein without departing from the spirit and scope of the invention.