阅读说明：本技术 一种多层pcb板内层图形的制作方法 (Method for manufacturing inner layer graph of multilayer PCB ) 是由 刘念 邓威 于 2019-09-30 设计创作，主要内容包括：一种多层PCB板内层图形的制作方法,其特征在于,包括如下步骤：S1,开料制作内层芯板,内层芯板的横排的单元数量或者纵排的单元数量中至少有一排的单元数量为偶数；S2,在菲林上为内层芯板的单元制作PCB板的线路图,所述上菲林的第二层线路图和所述下菲林的第三层线路图的位置相对应,所述上菲林的第五层线路图和所述下菲林的第四层线路图的位置相对应,所述上菲林的第二层线路图和所述上菲林的第五层线路图对称分布于所述上菲林中心线两侧；S3,在所述上菲林和所述下菲林上设计通孔。本发明将制作PCB板所需要的菲林数量减半,节约了物料及菲林制作时间,减少不同内层芯板的涨缩差异,降低压合时的配对难度,缩减生产运转周期,提高了生产效率。(A manufacturing method of an inner layer graph of a multilayer PCB is characterized by comprising the following steps: s1, cutting to manufacture an inner core plate, wherein at least one row of the horizontal row of units or the vertical row of units of the inner core plate is even; s2, manufacturing a circuit diagram of the PCB for the unit of the inner core board on the film, wherein the positions of the second layer circuit diagram of the upper film correspond to the positions of the third layer circuit diagram of the lower film, the positions of the fifth layer circuit diagram of the upper film correspond to the positions of the fourth layer circuit diagram of the lower film, and the second layer circuit diagram of the upper film and the fifth layer circuit diagram of the upper film are symmetrically distributed on the two sides of the central line of the upper film; and S3, designing through holes on the upper film and the lower film. The invention reduces the number of films required for manufacturing the PCB by half, saves materials and the manufacturing time of the films, reduces the harmomegathus difference of different inner-layer core plates, reduces the matching difficulty during compression, shortens the production running period and improves the production efficiency.)

1. A manufacturing method of an inner layer graph of a multilayer PCB is characterized by comprising the following steps:

s1, cutting to manufacture an inner core plate, wherein a plurality of units are spliced in the inner core plate, and the number of at least one row of units in the number of transverse rows or the number of longitudinal rows of the inner core plate is even;

s2, manufacturing a circuit diagram of the PCB for the units of the inner core board on the film, wherein the film comprises an upper film and a lower film, and the circuit diagram of the PCB comprises: the positions of the second layer circuit diagram of the upper film and the third layer circuit diagram of the lower film correspond, the positions of the fifth layer circuit diagram of the upper film and the fourth layer circuit diagram of the lower film correspond, the second layer circuit diagram of the upper film and the fifth layer circuit diagram of the upper film are symmetrically distributed on two sides of the central line of the upper film, and the central line of the upper film is the longitudinal central line of the upper film or the transverse central line of the upper film;

s3, designing through holes on the upper film and the lower film, and symmetrically distributing the holes on the plate edge of the upper film along the central line of the upper film, and symmetrically distributing the holes on the plate edge of the lower film along the central line of the lower film, wherein the positions of the central lines of the upper film and the lower film correspond to each other;

s4, the number of the inner core boards is two, and the first inner core board and the second inner core board are respectively subjected to other inner process treatment and inner AOL treatment;

and S5, overturning the second inner core board along the central line of the second inner core board corresponding to the central line of the upper film, stacking the copper plate, the first inner core board, the second inner core board and the prepreg according to a preset stacking sequence, and pressing to obtain a whole board.

2. The method for fabricating an inner pattern of a multilayer PCB as recited in claim 1, wherein in step S2, when the number of cells in the rows of the inner core is even, the second layer layout pattern of the upper film and the fifth layer layout pattern of the upper film are symmetrically distributed on both sides of the longitudinal centerline of the upper film, and when the number of cells in the rows of the inner core is even, the second layer layout pattern of the upper film and the fifth layer layout pattern of the upper film are symmetrically distributed on both sides of the transverse centerline of the upper film.

3. The method for manufacturing an inner layer pattern of a multilayer PCB as recited in claim 2, wherein in step S3, each hole on the edge of the upper film is divided into a symmetric hole and an asymmetric hole, each symmetric hole of the upper film is symmetrically distributed along the central line of the upper film, and each asymmetric hole of the upper film is asymmetrically distributed along the central line of the upper film; designing through holes in symmetrical positions of the upper film asymmetric holes along the upper film central line; after the through holes are manufactured, all holes on the plate edge of the upper film are symmetrically distributed along the central line of the upper film; the step of designing the through hole by the lower film is the same as the step of designing the through hole by the upper film.

4. The method for fabricating patterns on an inner layer of a multi-layer PCB as recited in claim 3, wherein in step S3, when the number of cells in a vertical row of the upper film is even, the length of the fused block at the edge of the upper film is increased, and correspondingly, the length of the fused block at the edge of the lower film is increased.

5. The method for fabricating patterns on an inner layer of a multi-layer PCB as recited in claim 4, wherein in step S3, the holes on the edge of the upper film include rivet hole tube position optical points for positioning devices during riveting and fool-proof target holes for fool-proof in the punching holes.

6. The method for fabricating patterns on an inner layer of a multi-layer PCB as recited in claim 5, wherein in step S2, the second layer layout of the upper film and the fifth layer layout of the upper film are respectively located at two sides of a center line of the upper film.

7. The method for manufacturing an inner layer pattern of a multilayer PCB as claimed in claim 6, wherein in step S3, layer number identifiers for identifying the number of inner layers of the PCB are respectively arranged at two ends of the upper film and two ends of the lower film.

8. The method of claim 7, wherein the entire board is drilled, and a tail hole for identifying a direction is drilled in the drilled hole.

9. The method of claim 8, wherein after the step S3 and before the step S4, the corresponding positions of the upper film and the lower film are further formed with a fool-proof mark for correctly stacking the core boards.

10. The method of claim 9, further comprising punching, browning, fusing and riveting the first and second inner core boards after step S4 and before step S5.

Technical Field

The invention belongs to the technical field of PCB manufacturing, and particularly relates to a method for manufacturing an inner layer graph of a multilayer PCB.

Background

A Printed Circuit Board (PCB) is an important electronic component, is a support for an electronic component, and is a provider of electrical connection of the electronic component. At present, when inner layer patterns of 6 layers or more than 6 layers of printed circuit boards are manufactured, a plurality of sets of films need to be manufactured, for example, when 6 layers of printed circuit boards are manufactured, 2 pieces of inner layer core boards are needed, and each piece of inner layer core board needs to be manufactured with one set of films. The film manufacturing cost is high, and secondly, the expansion and shrinkage difference between different inner core plates is large due to the fact that the inner core plates are manufactured by different films, the coefficient matching production difficulty is high, the production running period is long, and the efficiency is low.

Therefore, there is a need to provide a new method for forming inner patterns of a multi-layer PCB to solve the above-mentioned problems.

Disclosure of Invention

The invention aims to solve the technical problem of providing a method for manufacturing inner layer patterns of a multilayer PCB, which improves the production efficiency of inner layers, reduces the expansion and contraction difference of different inner layer core plates, reduces the matching difficulty during compression and shortens the production and operation period.

The invention solves the technical problem by adopting the technical scheme that a method for manufacturing an inner layer graph of a multilayer PCB comprises the following steps:

s1, cutting to manufacture an inner core plate, wherein a plurality of units are spliced in the inner core plate, and the number of at least one row of units in the number of transverse rows or the number of longitudinal rows of the inner core plate is even;

s2, manufacturing a circuit diagram of the PCB for the units of the inner core board on the film, wherein the film comprises an upper film and a lower film, and the circuit diagram of the PCB comprises: the positions of the second layer circuit diagram of the upper film and the third layer circuit diagram of the lower film correspond, the positions of the fifth layer circuit diagram of the upper film and the fourth layer circuit diagram of the lower film correspond, the second layer circuit diagram of the upper film and the fifth layer circuit diagram of the upper film are symmetrically distributed on two sides of the central line of the upper film, and the central line of the upper film is the longitudinal central line of the upper film or the transverse central line of the upper film;

s3, designing through holes on the upper film and the lower film, and symmetrically distributing the holes on the plate edge of the upper film along the central line of the upper film, and symmetrically distributing the holes on the plate edge of the lower film along the central line of the lower film, wherein the positions of the central lines of the upper film and the lower film correspond to each other;

s4, the number of the inner core boards is two, and the first inner core board and the second inner core board are respectively subjected to other inner process treatment and inner AOL treatment;

and S5, overturning the second inner core board along the central line of the second inner core board corresponding to the central line of the upper film, stacking the copper plate, the first inner core board, the second inner core board and the prepreg according to a preset stacking sequence, and pressing to obtain a whole board.

Preferably, in step S2, when the number of the units in the horizontal row of the inner core board is an even number, the second layer circuit diagram of the upper film and the fifth layer circuit diagram of the upper film are symmetrically distributed on both sides of the longitudinal center line of the upper film, and when the number of the units in the vertical row of the inner core board is an even number, the second layer circuit diagram of the upper film and the fifth layer circuit diagram of the upper film are symmetrically distributed on both sides of the transverse center line of the upper film.

Preferably, in step S3, dividing each hole on the edge of the upper film into a symmetric hole and an asymmetric hole, where the symmetric holes of the upper film are symmetrically distributed along the central line of the upper film, and the asymmetric holes of the upper film are asymmetrically distributed along the central line of the upper film; designing through holes in symmetrical positions of the upper film asymmetric holes along the upper film central line; after the through holes are manufactured, all holes on the plate edge of the upper film are symmetrically distributed along the central line of the upper film; the step of designing the through hole by the lower film is the same as the step of designing the through hole by the upper film.

Preferably, in step S3, when the number of cells in the longitudinal row of the upper film is an even number, the length of the fused block at the edge of the upper film longitudinal plate is increased, and correspondingly, the length of the fused block at the edge of the lower film longitudinal plate is increased.

Preferably, in step S3, the holes on the upper film plate edge include rivet hole tube position optical points for positioning the device during riveting and fool-proof target holes for fool-proof in the punching target holes.

Preferably, in step S2, the second layer circuit pattern of the upper film and the fifth layer circuit pattern of the upper film are respectively located on two sides of the center line of the upper film.

Preferably, in step S3, layer number identifiers for identifying the number of layers in the PCB are respectively disposed at two ends of the upper film and two ends of the lower film.

Preferably, the entire plate is drilled, and a tail hole for identifying a direction is drilled in the drilled hole.

Preferably, after the step S3 and before the step S4, fool-proof identifiers for correctly stacking the inner core boards are further formed at the corresponding positions of the upper film and the lower film.

Preferably, after step S4 and before step S5, the method further comprises punching, browning, fusing and riveting the first inner core plate and the second inner core plate.

Compared with the prior art, the invention reduces the number of films required for manufacturing the PCB by half, saves the material and the manufacturing time of the films, reduces the harmomegathus difference of different inner-layer core plates, reduces the matching difficulty during compression, reduces the production running period and improves the production efficiency; compared with the traditional respective exposure, the continuous exposure is designed, so that the upper and lower film time and the first measurement time are saved.

Drawings

FIG. 1 is a flow chart of the present invention;

fig. 2 is a schematic view of the stacking of two inner core panels of the present invention.

In the figure:

1. an inner core board.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.