阅读说明：本技术 一种高精度低回踢噪声的时钟再生延迟链 (High-precision low-kickback-noise clock regeneration delay chain ) 是由 朱樟明 张玮 马瑞 刘马良 王夏宇 胡进 于 2019-08-16 设计创作，主要内容包括：本发明公开了一种高精度低回踢噪声的时钟再生延迟链,包括：电压转换模块,连接电压输入端,用于将输入信号转换为第一电压信号和第二电压信号；延迟链模块,连接所述电压转换模块和时钟输入端,用于根据所述第一电压信号和所述第二电压信号控制时钟延迟时间得到第一时钟信号簇和第二时钟信号簇；时钟驱动模块,连接所述延迟链模块,用于接收并处理所述第一时钟信号簇和所述第二时钟信号簇,输出多相位时钟信号簇。本发明提供的时钟再生延迟链具有可干扰能力和时钟再生能力,可以适应高精度系统级的应用。(The invention discloses a high-precision low-kickback noise clock regeneration delay chain, which comprises: the voltage conversion module is connected with the voltage input end and used for converting the input signal into a first voltage signal and a second voltage signal; the delay chain module is connected with the voltage conversion module and the clock input end and used for controlling clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster; and the clock driving module is connected with the delay chain module and is used for receiving and processing the first clock signal cluster and the second clock signal cluster and outputting a multi-phase clock signal cluster. The clock regeneration delay chain provided by the invention has the capability of interference and clock regeneration, and can be suitable for high-precision system-level application.)

1. A high accuracy low kickback noise clock regenerative delay chain, comprising:

the voltage conversion module is connected with the voltage input end and used for converting the input signal into a first voltage signal and a second voltage signal;

the delay chain module is connected with the voltage conversion module and the clock input end and used for controlling clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster;

and the clock driving module is connected with the delay chain module and is used for receiving and processing the first clock signal cluster and the second clock signal cluster and outputting a multi-phase clock signal cluster.

2. The clock regenerative delay chain of claim 1, wherein the delay chain module comprises N cascaded delay chain base units, each of the delay chain base units being connected to the voltage conversion module; wherein N is a positive integer.

3. The clock regenerative delay chain of claim 2, wherein the delay chain basic unit comprises a low-pass filtering subunit, a first delay subunit, a first clock regenerative subunit, a second delay subunit, and a second clock regenerative subunit connected in series in this order.

4. The clock regenerative delay chain of claim 3, wherein the low pass filter subunit comprises a first resistor R1 and a second resistor R2; wherein the content of the first and second substances,

one end of the first resistor R1 is connected with the voltage conversion module, and the other end is connected with the first delay subunit and the second delay subunit;

one end of the second resistor R2 is connected to the voltage conversion module, and the other end is connected to the first delay subunit and the second delay subunit.

5. The clock regenerative delay chain of claim 4, wherein the first delay sub-unit comprises transistors M1, M5, M6, M3 connected in series in sequence to a power supply terminal VDD and a GND terminal; wherein the content of the first and second substances,

the source of the transistor M1 is connected with a power supply VDD terminal, and the source of the transistor M3 is connected with a GND terminal;

the gate of the transistor M1 is connected with the voltage conversion module through the first resistor R1;

the gate of the transistor M3 is connected with the voltage conversion module through the second resistor R2;

the gates of the transistors M5 and M6 are connected to each other and to the clock input.

6. The clock regenerative delay chain of claim 5, wherein the first clock regenerative subunit comprises transistors M7, M8, M9, M10; wherein the content of the first and second substances,

the gate of the transistor M7 is connected with the common drain terminal of the transistors M5 and M6, and the source of the transistor M7 is connected with the VDD terminal;

the gate of the transistor M8 is connected with the gate of the transistor M7 and the common drain terminal of the transistors M5 and M6, the source of the transistor M8 is connected with the GND terminal, and the drain is connected with the drain of the transistor M7;

the gate of the transistor M9 is connected with the common drain terminal of the transistors M7 and M8, and the source of the transistor M9 is connected with the VDD terminal;

the gate of the transistor M10 is connected to the gate of the transistor M9 and to the common drain terminal of the transistors M7 and M8, the source of the transistor M10 is connected to the GND terminal, and the drain of the transistor M10 is connected to the drain of the transistor M9 and outputs the first clock signal as the output terminal of the first clock regeneration subunit.

7. The clock regeneration delay chain of claim 6, wherein the second delay subunit comprises transistors M2, M11, M12, M4 connected in series in sequence to a power supply terminal VDD and a GND terminal; wherein the content of the first and second substances,

the source of the transistor M2 is connected with a power supply VDD terminal, and the source of the transistor M4 is connected with a GND terminal;

the gate of the transistor M2 is connected with the voltage conversion module through the first resistor R1;

the gate of the transistor M4 is connected with the voltage conversion module through the second resistor R2;

the gates of the transistors M11 and M12 are connected to each other and to the output terminal of the first clock regeneration subunit.

8. The clock regenerative delay chain of claim 7, wherein the second clock regenerative subunit comprises transistors M13, M14, M15, M16; wherein the content of the first and second substances,

the gate of the transistor M13 is connected with the common drain terminal of the transistors M11 and M12, and the source of the transistor M13 is connected with the VDD terminal;

the gate of the transistor M14 is connected with the gate of the transistor M13 and the common drain terminal of the transistors M11 and M12, the source of the transistor M14 is connected with the GND terminal, and the drain of the transistor M14 is connected with the drain of the transistor M13;

the gate of the transistor M15 is connected with the common drain terminal of the transistors M13 and M14, and the source of the transistor M15 is connected with the VDD terminal;

the gate of the transistor M16 is connected to the gate of the transistor M15 and to the common drain terminal of the transistors M13 and M14, the source of the transistor M16 is connected to the GND terminal, and the drain of the transistor M16 is connected to the drain of the transistor M15 and outputs the second clock signal as the output terminal of the second clock regeneration subunit.

9. The clock regeneration delay chain of claim 8, wherein the transistors M1, M2, M5, M7, M9, M11, M13 and M15 are all PMOS transistors, and the transistors M3, M4, M6, M8, M10, M12, M14 and M16 are all NMOS transistors.

10. The clock regenerative delay chain of claim 1, wherein the clock driver module comprises N clock driver units, the N clock driver units being sequentially connected to the N delay chain base units.

Technical Field

The invention belongs to the technical field of laser radar signal receiver systems, and particularly relates to a high-precision low-kickback-noise clock regeneration delay chain.

Background

The laser radar utilizes a laser transmitter to emit laser to irradiate on a detected object, laser echo reflected by a target object is received by an avalanche photodiode working in a linear mode and converted into a current signal, a front-end analog receiver linearly converts pulse current generated by the avalanche photodiode into a voltage signal, a time-to-digital conversion circuit is utilized to obtain flight time information of the pulse, or an analog-to-digital converter acquires amplitude of echo pulse, and finally the amplitude is provided for a subsequent digital signal processor to be further processed. In the time-to-digital conversion circuit, the delay chain phase-locked loop has wide application prospect.

The wide application of the delay chain phase-locked loop requires that the precision and the stability of the delay chain outputting the multi-phase clock are higher, and the interference of external environment noise or internal noise of the delay chain on the phase splitting precision is avoided. For some multi-delay chain systems, the consistency of delay time of different delay chains is required to be high under the same voltage, and the weak change of control voltage cannot generate huge interference on the delay chains; under different voltages, the delay chain is required to accurately generate stable delays with different delay times.

However, the conventional voltage-controlled delay unit does not have anti-interference capability and clock regeneration capability, the phase intervals of the output multiphase clocks are inconsistent, the duty ratio consistency is poor, the phase noise is high, the phase splitting precision is low, the voltage division ratio of similar delay time is low, the voltage division ratio is easily influenced by environmental noise, and the voltage-controlled delay unit cannot be applied to high-precision system-level applications such as a multi-line integrated chip and a high-resolution precision chip.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a high-precision and low-kickback noise clock regeneration delay chain. The technical problem to be solved by the invention is realized by the following technical scheme:

a high precision low kickback noise clock regeneration delay chain comprising: the voltage conversion module is connected with the voltage input end and used for converting the input signal into a first voltage signal and a second voltage signal;

the delay chain module is connected with the voltage conversion module and the clock input end and used for controlling clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster;

and the clock driving module is connected with the delay chain module and is used for receiving and processing the first clock signal cluster and the second clock signal cluster and outputting a multi-phase clock signal cluster.

In one embodiment of the present invention, the delay chain module includes N cascaded delay chain basic units, and the delay chain basic units are connected to the voltage conversion module; wherein N is a positive integer.

In one embodiment of the present invention, the delay chain basic unit includes a low-pass filtering unit, a first delay sub-unit, a first clock regeneration sub-unit, a second delay sub-unit, and a second clock regeneration sub-unit, which are connected in series in sequence.

In one embodiment of the present invention, the low pass filtering subunit includes a first resistor R1 and a second resistor R2; wherein the content of the first and second substances,

one end of the first resistor R1 is connected with the voltage conversion module, and the other end is connected with the first delay subunit and the second delay subunit;

one end of the second resistor R2 is connected to the voltage conversion module, and the other end is connected to the first delay subunit and the second delay subunit.

In one embodiment of the present invention, the first delay sub-unit includes transistors M1, M5, M6, M3 connected in series in this order to a power supply terminal VDD and a GND terminal; wherein the content of the first and second substances,

the source of the transistor M1 is connected with a power supply VDD terminal, and the source of the transistor M3 is connected with a GND terminal;

the gate of the transistor M1 is connected with the voltage conversion module through the first resistor R1;

the gate of the transistor M3 is connected with the voltage conversion module through the second resistor R2;

the gates of the transistors M5 and M6 are connected with each other and are connected with a clock input end;

in one embodiment of the present invention, the first clock regeneration subunit includes transistors M7, M8, M9, M10; wherein the content of the first and second substances,

the gate of the transistor M7 is connected with the common drain terminal of the transistors M5 and M6, and the source of the transistor M7 is connected with the VDD terminal;

the gate of the transistor M8 is connected with the gate of the transistor M7 and the common drain terminal of the transistors M5 and M6, the source of the transistor M8 is connected with the GND terminal, and the drain of the transistor M8 is connected with the drain of the transistor M7;

the gate of the transistor M9 is connected with the common drain terminal of the transistors M7 and M8, and the source of the transistor M9 is connected with the VDD terminal;

the gate of the transistor M10 is connected to the gate of the transistor M9 and to the common drain terminal of the transistors M7 and M8, the source of the transistor M10 is connected to the GND terminal, and the drain of the transistor M10 is connected to the drain of the transistor M9 and outputs the first clock signal as the output terminal of the first clock regeneration subunit.

In one embodiment of the present invention, the second delay sub-unit includes transistors M2, M11, M12, M4 connected in series to the power supply terminal VDD and the GND terminal in this order; wherein the content of the first and second substances,

the source of the transistor M2 is connected with a power supply VDD terminal, and the source of the transistor M4 is connected with a GND terminal;

the gate of the transistor M2 is connected with the voltage conversion module through the first resistor R1;

the gate of the transistor M4 is connected with the voltage conversion module through the second resistor R2;

the gates of the transistors M11 and M12 are connected to each other and to the output terminal of the first clock regeneration subunit.

In one embodiment of the present invention, the second clock regeneration subunit includes transistors M13, M14, M15, M16; wherein the content of the first and second substances,

the gate of the transistor M13 is connected with the common drain terminal of the transistors M11 and M12, and the source of the transistor M13 is connected with the VDD terminal;

the gate of the transistor M14 is connected with the gate of the transistor M13 and the common drain terminal of the transistors M11 and M12, the source of the transistor M14 is connected with the GND terminal, and the drain of the transistor M14 is connected with the drain of the transistor M13;

the gate of the transistor M15 is connected with the common drain terminal of the transistors M13 and M14, and the source of the transistor M15 is connected with the VDD terminal;

the gate of the transistor M16 is connected to the gate of the transistor M15 and to the common drain terminal of the transistors M13 and M14, the source of the transistor M16 is connected to the GND terminal, and the drain of the transistor M16 is connected to the drain of the transistor M15 and outputs the second clock signal as the output terminal of the second clock regeneration subunit.

In one embodiment of the invention, the transistors M1, M2, M5, M7, M9, M11, M13 and M15 are all PMOS transistors, and the transistors M3, M4, M6, M8, M10, M12, M14 and M16 are all NMOS transistors.

In an embodiment of the present invention, the clock driving module includes N clock driving units, and the N clock driving units are sequentially connected to the N delay chain basic units.

The invention has the beneficial effects that:

1. the clock regeneration delay chain provided by the invention adopts a method of embedding a low-pass filter, thereby reducing the kickback noise of a high-speed clock to a voltage control line, improving the voltage control capability of the voltage control line and ensuring the phase interval consistency of the generated multiphase clock;

2. according to the clock regeneration delay chain, the clock regeneration unit is adopted to adjust the voltage-controlled delay time and recover the clock duty ratio, so that the output clock of each voltage-controlled delay unit has certain clock delay and has steep rising edges and falling edges, and the duty ratio consistency of the multi-phase clock is ensured;

3. the clock regeneration delay chain provided by the invention is additionally provided with the clock regeneration unit, and the inherent delay of the delay chain unit is increased due to the inherent delay of the clock regeneration unit, so that the adjustment range of the voltage-controlled line can be correspondingly reduced to reach the same delay time, the precision of the voltage-controlled delay is effectively improved, the anti-noise performance of the voltage-controlled delay chain is improved, the voltage-controlled voltage change required by the same delay time difference is increased, and the clock regeneration delay chain is more suitable for a high-precision multi-chain delay chain phase-locked loop and a time digital detection system formed by the same.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic diagram of a high-precision low-kickback-noise clock regenerative delay chain structure according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another high-precision low-kickback noise clock regeneration delay chain structure according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a basic unit structure of a delay chain according to an embodiment of the present invention;

FIG. 4 is an equivalent circuit diagram of a low pass filter provided by an embodiment of the invention;

fig. 5 is a schematic diagram of the delay module building basic delay unit outputting multi-phase clock pulse contraction provided by the embodiment of the invention;

FIG. 6 is a schematic diagram illustrating waveforms of the CLK signal delayed by the basic delay unit according to an embodiment of the present invention;

fig. 7 is a diagram comparing the delay effect of the conventional delay chain and the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.