阅读说明：本技术 一种pcb内层板层间对准度的测试方法 (Method for testing interlayer alignment degree of PCB inner-layer plate ) 是由 胡荫敏 彭卫红 荣孝强 罗练军 于 2019-08-20 设计创作，主要内容包括：本发明涉及电路板生产制造技术领域,具体为一种PCB内层板层间对准度的测试方法。本发明通过在内层板顶层和底层的同一角处设置一对不重合的测试PAD图形,并计算该对测试PAD图形在X方向和Y方向的设计偏差值；蚀刻后在内层板的底层和顶层形成与该对测试PAD图形对应的测试PAD；通过计算测试PAD在X方向和Y方向的实测偏差值,可分别与X方向和Y方向的设计偏差值进行比较,精确计算出内层板顶层与底层的线路之间的偏差；同时本发明方法不涉及测试人员的主观判断,从而可避免因测试人员的主观判断而造成的误差,测试结果重复性好,更客观可靠。(The invention relates to the technical field of circuit board production and manufacturing, in particular to a method for testing interlayer alignment of a PCB inner layer board. The invention sets a pair of non-coincident test PAD patterns at the same angle of the top layer and the bottom layer of the inner layer plate, and calculates the design deviation values of the pair of test PAD patterns in the X direction and the Y direction; forming a test PAD corresponding to the pair of test PAD patterns on the bottom layer and the top layer of the inner layer plate after etching; calculating actual measurement deviation values of the test PAD in the X direction and the Y direction, and comparing the actual measurement deviation values with design deviation values in the X direction and the Y direction respectively to accurately calculate the deviation between the circuits of the top layer and the bottom layer of the inner layer plate; meanwhile, the method does not relate to subjective judgment of testers, so that errors caused by the subjective judgment of the testers can be avoided, and the test result has good repeatability and is more objective and reliable.)

1. A method for testing interlayer alignment of a PCB inner layer board is characterized by comprising the following steps:

s1, respectively aligning the patterns on the top film and the bottom film by exposure and developmentThe pattern is transferred to the top layer and the bottom layer of the inner layer plate, and the pattern at least comprises a test PAD pattern which is respectively arranged at one of four corners of a top layer film and a bottom layer film; coordinates of test PAD pattern on top film as top design coordinates (X)_A，Y_A) The coordinates of the test PAD pattern on the base film are the base design coordinates (X)_B，Y_B)_；

S2, etching and film stripping treatment are carried out according to the patterns of the top layer and the bottom layer of the inner layer plate, and an inner layer circuit and a test PAD corresponding to the test PAD pattern are formed on the top layer and the bottom layer of the inner layer plate;

s3, measuring the coordinates of the test PAD by a Pluritec target drilling machine, wherein the coordinates of the test PAD on the top layer of the inner layer plate are the measured coordinates (X) of the top layer_a，Y_a) The coordinate of the test PAD on the bottom layer of the inner layer board is the measured coordinate (X) of the bottom layer_b，Y_b)；

S4, calculating deviation value DeltaX of the top layer design coordinate and the bottom layer design coordinate in the X direction respectively_sAnd deviation value DeltaY in Y direction_s，△X_s＝X_A-X_B，△Y_s＝Y_A-Y_B；

Respectively calculating the deviation value delta X of the top layer measured coordinate and the bottom layer measured coordinate in the X direction_tAnd deviation value DeltaY in Y direction_t，ΔX_t＝X_a-X_b，ΔY_t＝Y_a-Y_b；

S5, wherein the interlayer alignment degree of the inner layer plate in the X direction is delta X_t-ΔX_s(ii) a The interlayer alignment degree of the inner layer plate in the Y direction is delta Y_t-ΔY_s。

2. The method for testing interlayer alignment of inner layer board of PCB of claim 1, wherein in step S1, each of four corners of said top film and said bottom film is designed with a test PAD pattern.

3. The method for testing interlayer alignment of inner layer board of PCB of claim 2, wherein said test PAD pattern is circular with a diameter greater than or equal to 0.5 mm.

4. The method for testing the interlayer alignment of the inner layer board of the PCB as claimed in claim 3, wherein the distance between the test PAD on the top layer and the test PAD on the bottom layer projected in the direction perpendicular to the board surface at the same corner of the inner layer board is greater than or equal to 3 mm.

Technical Field

The invention relates to the technical field of circuit board production and manufacturing, in particular to a method for testing interlayer alignment of a PCB (printed circuit board) inner layer board.

Background

In the production of the PCB, in each process step of fabricating the inner layer circuit on the inner layer board, the circuit formed on the inner layer board may be deviated due to an error in pattern transfer, expansion and contraction of the board, and the like, so that the circuits on the front and back sides of the inner layer board have alignment deviation, and therefore, the interlayer alignment degree of the patterns/circuits on the upper and lower sides of the inner layer board needs to be monitored in the production process, so as to ensure the smooth proceeding of the subsequent processes and the quality of the PCB finished product. In the prior art, the principle of a vernier caliper is adopted when the interlayer alignment of an inner layer plate is tested, and the deviation degree is judged visually, for example, the deviation amount with the precision within the range of 5 μm can only be estimated by applying the principle of a testing method disclosed in a method for detecting the deviation degree of a drilling hole in a PCB (printed Circuit Board) in Chinese patent document CN 201510250510.9. The slice measurement based on the vernier caliper principle cannot accurately measure the interlayer offset data of the inner-layer plate, and the grinding and slicing of the thin plate are inaccurate; the principle of the vernier caliper is applied to a film exposure machine, and the precision cannot be guaranteed because the film exposure machine needs to be processed by multiple devices; and different testers carry out the test, can lead to the error too big because of different testers' operation difference.

Disclosure of Invention

The invention provides a simple and easy interlayer alignment measuring method which can accurately acquire offset data and has high measuring precision, aiming at the problems that the existing interlayer alignment measuring method of an inner layer plate has poor measuring precision, cannot acquire accurate measuring data, is complicated in measuring method and the like.

In order to achieve the purpose, the invention adopts the following technical scheme.

A method for testing interlayer alignment of a PCB inner layer board comprises the following steps:

s1, correspondingly transferring the patterns on the top film and the bottom film to the top layer and the bottom layer of the inner layer plate respectively through exposure and development, wherein the patterns at least comprise test PAD patterns which are respectively arranged at one of four corners of the top film and the bottom film; coordinates of test PAD pattern on top film as top design coordinates (X)_A，Y_A) The coordinates of the test PAD pattern on the base film are the base design coordinates (X)_B，Y_B)；

S2, etching and film stripping treatment are carried out according to the patterns of the top layer and the bottom layer of the inner layer plate, and an inner layer circuit and a test PAD corresponding to the test PAD pattern are formed on the top layer and the bottom layer of the inner layer plate;

S3, measuring the coordinates of the test PAD by a Pluritec target drilling machine, wherein the coordinates of the test PAD on the top layer of the inner layer plate are the measured coordinates (X) of the top layer_a，Y_a) The coordinate of the test PAD on the bottom layer of the inner layer board is the measured coordinate (X) of the bottom layer_b，Y_b)；

S4, calculating deviation value delta X of the top layer design coordinate and the bottom layer design coordinate in the X direction respectively_sAnd deviation value DeltaY in Y direction_s，ΔX_s＝X_A-X_B，ΔY_s＝Y_A-Y_B；

respectively calculating the deviation value delta X of the top layer measured coordinate and the bottom layer measured coordinate in the X direction_tAnd deviation value DeltaY in Y direction_t，ΔX_t＝X_a-X_b，ΔY_t＝Y_a-Y_b；

S5, wherein the interlayer alignment degree of the inner layer plate in the X direction is delta X_t-ΔX_s(ii) a The interlayer alignment degree of the inner layer plate in the Y direction is delta Y_t-ΔY_s。

Preferably, in step S1, a test PAD pattern is designed at each of four corners of the top film and the bottom film.

Preferably, the test PAD graph is circular, and the diameter is more than or equal to 0.5 mm.

Preferably, on the same corner of the inner layer plate, the projection of the test PAD of the top layer and the test PAD of the bottom layer in the direction vertical to the plate surface is more than or equal to 3 mm.

Compared with the prior art, the invention has the beneficial effects that:

The invention sets a pair of non-coincident test PAD patterns at the same angle of the top layer and the bottom layer of the inner layer plate, and calculates the design deviation values of the pair of test PAD patterns in the X direction and the Y direction; forming a test PAD corresponding to the pair of test PAD patterns on the bottom layer and the top layer of the inner layer plate after etching; calculating actual measurement deviation values of the test PAD in the X direction and the Y direction, and comparing the actual measurement deviation values with design deviation values in the X direction and the Y direction respectively to accurately calculate the deviation between the circuits of the top layer and the bottom layer of the inner layer plate; meanwhile, the method does not relate to subjective judgment of testers, so that errors caused by the subjective judgment of the testers can be avoided, and the test result has good repeatability and is more objective and reliable.

Detailed Description

in order to more fully understand the technical contents of the present invention, the technical solutions of the present invention will be further described and illustrated with reference to the following specific embodiments.