阅读说明：本技术 Vcsel芯片及其制造方法 (VCSEL chip and manufacturing method thereof ) 是由 郭铭浩 陈信男 王立 李念宜 王朝成 田志伟 于 2020-12-21 设计创作，主要内容包括：本申请提供一种VCSEL芯片及其制造方法。所述VCSEL芯片包括多个相互串联的子芯片,每个所述子芯片包括预设数量的VCSEL单元,所述子芯片之间具有预防各所述子芯片产生的热量对其相邻的子芯片的输出光功率产生影响的预设间距,通过这样的配置,所述VCSEL芯片能够在相对较小的电流驱动下,实现较大的光功率输出,并且,所述VCSEL芯片具有良好的高温表现能力。(The application provides a VCSEL chip and a manufacturing method thereof. The VCSEL chip comprises a plurality of sub-chips which are connected in series, each sub-chip comprises a preset number of VCSEL units, a preset distance is reserved between the sub-chips, and the preset distance prevents heat generated by each sub-chip from influencing the output optical power of the adjacent sub-chips.)

1. A VCSEL chip, comprising:

a substrate;

at least two sub-chips formed on the substrate, each sub-chip comprising a plurality of VCSEL units; and

and carrying out a series connection electric conduction pattern on the at least two sub-chips, wherein a preset distance for preventing heat generated by each of the at least two sub-chips from influencing the output optical power of the adjacent sub-chips is arranged between the at least two sub-chips.

2. The VCSEL chip of claim 1, wherein the VCSEL chip further comprises an electrical isolation region formed between each two of the chiplets for electrically isolating the chiplets.

3. The VCSEL chip of claim 2, wherein the electrical isolation region is formed between each two of the chiplets by ion implantation.

4. The VCSEL chip of claim 2, wherein the electrical isolation region is formed between each two of the chiplets through an etching process.

5. The VCSEL chip of claim 1, wherein the preset spacing is greater than or equal to 4 um.

6. A VCSEL chip according to claim 3 or 4, wherein a width of the electrically isolating region ranges from 1nm to 100 um.

7. The VCSEL chip of claim 1, wherein the electrically conductive pattern comprises a positive electrode and a negative electrode, the positive electrode and the negative electrode being formed on a same side surface of the VCSEL chip.

8. The VCSEL chip of claim 1, wherein the electrically conductive pattern comprises positive and negative electrodes formed on opposing side surfaces of the VCSEL chip.

9. The VCSEL chip of claim 1, wherein an output power of the VCSEL chip is 3W to 15W.

10. The VCSEL chip of claim 1, wherein each of the chiplets contains a number of VCSEL units in the range of 100 to 750.

11. A method for fabricating a VCSEL chip, comprising:

forming a substrate;

forming a plurality of VCSEL units on the substrate;

the VCSEL units in the preset region are electrically connected through an electrical connection structure according to the distribution of the preset region to form at least two sub-chips, wherein a preset distance for preventing heat generated by each sub-chip in the at least two sub-chips from influencing the output optical power of the adjacent sub-chips is arranged between the sub-chips;

forming an electrical isolation region between each two of the sub-chips; and

the at least two sub-chips are connected in series by an electrically conductive pattern.

12. The method of claim 11, wherein forming an electrical isolation region between each two of the chiplets comprises:

and forming the electric isolation region between every two sub-chips through an ion implantation process.

13. The method of claim 11, forming an electrical isolation region between each two of the chiplets, comprising:

the electrically isolated regions are formed between each two of the chiplets by an etching process.

14. A method of manufacturing as claimed in claim 12 or 13, wherein the electrically isolated region has a width in the range of 1nm to 100 um.

15. The production method according to claim 11, wherein the preset pitch is greater than or equal to 4 um.

Technical Field

The present invention relates to the field of laser technology, and more particularly, to a VCSEL chip and a method for manufacturing the same, wherein the VCSEL chip can achieve a large optical power output under a relatively small current driving, and the VCSEL chip has a good high temperature performance capability.

Background

Vertical-Cavity Surface-Emitting lasers (VCSELs) are widely used in communication technologies, such as short-wavelength multimode fiber communication, and since the VCSELs can still effectively operate in extreme temperature environments and radiation environments, they are also widely used in the fields of illumination sources and industrial thermal processing. In order to obtain a higher output optical power, the VCSEL lasers are typically arranged in an array on a substrate and packaged to form a VCSEL chip.

In recent years, with the expansion of the application scenarios of VCSEL technology, in some application scenarios, the requirement for the output optical power of the VCSEL chip is higher and higher. Therefore, a corresponding solution is needed to increase the power of the VCSEL chip. There are a number of technical directions for increasing the output optical power of VCSEL chips.

The first common technical scheme for increasing the optical power of the VCSEL chip is to increase the effective light-emitting area of the VCSEL chip, and specifically includes two means: the number of points of the VCSEL units is increased, or the aperture of the light emitting hole of a single VCSEL unit is increased.

Corresponding to the first technical means, the number of points of the VCSEL units cannot be increased infinitely in the implementation, and when the number of points reaches a certain degree, a large input current is required, which means that high heat is generated, and poor heat dissipation performance of the VCSEL chip becomes an important factor for preventing the optical power of the VCSEL chip from increasing.

Corresponding to the second technical means, the aperture of the light emitting hole of each VCSEL unit is increased, in the specific implementation, limited by the current-carrying distribution loss and the restriction of the modal characteristics, and the aperture of the light emitting hole of the VCSEL unit cannot be too large, that is, there is a certain upper limit in increasing the overall output optical power of the VCSEL array by increasing the output optical power of each VCSEL unit.

Although both of the above-mentioned technical means can increase the output optical power of the VCSEL chip to some extent, it is increasingly difficult to meet the increasing optical power requirement of the VCSEL chip.

A second common technical direction for increasing the optical Power of the VCSEL chip is to adjust the structure of each VCSEL unit in the VCSEL chip, and in particular, adjust a single PN junction VCSEL unit into a multiple PN junction VCSEL unit (such as the multiple PN junction VCSEL laser disclosed in US 6936486) to increase the output optical Power of the single VCSEL unit, however, the multiple PN junction VCSEL laser is very sensitive to temperature variation, and the output optical Power of the multiple PN junction VCSEL unit suddenly drops (Power Drop) in a high temperature environment, which is not suitable for being applied in products.

Compared with a single-PN junction VCSEL laser, the layer structure of the multi-PN junction VCSEL unit is more complex, wherein factors such as the position design of the tunnel junction, the position design of the quantum well, the arrangement concentration of the tunnel junction, the material selection and the like have very important influence on the performance of the multi-PN junction VCSEL laser, so that the multi-PN junction VCSEL laser is more difficult to process, and the consistency and the stability of the performance are relatively more difficult to ensure.

Therefore, a new type of VCSEL chip is needed to meet the current demand for higher and higher optical power for VCSEL chips.

Content of application

An advantage of the present application is to provide a VCSEL chip and a method for manufacturing the same, wherein the VCSEL chip can achieve a large optical power output with a relatively small current driving, and the VCSEL chip has a good high temperature performance capability.

Another advantage of the present application is to provide a VCSEL chip and a method of manufacturing the same, in which the VCSEL chip includes a plurality of sub-chips each including a predetermined number of VCSEL units and an electrical conduction pattern for connecting the plurality of sub-chips in series, and by such a configuration, the VCSEL chip can achieve a large optical power output with a relatively small current driving, and the VCSEL chip has a good high temperature performance capability.

Another advantage of the present application is to provide a VCSEL chip and a method for manufacturing the VCSEL chip, wherein a predetermined distance is provided between each of the sub-chips of the VCSEL chip to reduce an influence of heat generated by each of the sub-chips on an adjacent sub-chip.

Another advantage of the present application is to provide a VCSEL chip and a method for manufacturing the VCSEL chip, wherein in one possible implementation manner of the present application, each of the sub-chips is integrally formed on a same substrate and is divided into regions by an ion implantation process or a semiconductor etching process. In this possible implementation, the molding process of the VCSEL chip and the process of dividing the VCSEL chip into a plurality of sub-chips can be completed in one go, which is beneficial to reducing the production cost.

Another advantage of the present application is to provide a VCSEL chip and a method of manufacturing the same, in which the VCSEL chip can realize zoned lighting.

To achieve at least one of the above advantages, the present application provides a VCSEL chip including:

a substrate;

at least two sub-chips formed on the substrate, each sub-chip comprising a plurality of VCSEL units; and

and carrying out a series connection electric conduction pattern on the at least two sub-chips, wherein a preset distance for preventing heat generated by each of the at least two sub-chips from influencing the output optical power of the adjacent sub-chips is arranged between the at least two sub-chips.

In the VCSEL chip according to the present application, the VCSEL chip further includes an electrical isolation region formed between each two of the sub-chips for electrically isolating the sub-chips.

In the VCSEL chip according to the present application, the electrical isolation region is formed between each two sub-chips by ion implantation.

In the VCSEL chip according to the present application, the electrical isolation region is formed between each two of the sub-chips through an etching process.

In the VCSEL chip according to the present application, the preset pitch is greater than or equal to 4 um.

In the VCSEL chip according to the present application, the width of the electrically isolating region ranges from 1nm to 100 um.

In the VCSEL chip according to the present application, the electrical conduction pattern includes a positive electrode and a negative electrode, which are formed on the same side surface of the VCSEL chip.

In the VCSEL chip according to the present application, the electrical conduction pattern includes a positive electrode and a negative electrode formed at opposite side surfaces of the VCSEL chip.

In the VCSEL chip according to the present application, the output power of the VCSEL chip is 3W to 15W.

In the VCSEL chip according to the present application, each of the sub-chips includes the VCSEL units in an amount ranging from 100 to 750.

According to another aspect of the present application, there is also provided a method for manufacturing a VCSEL chip, including:

forming a substrate;

forming a plurality of VCSEL units on the substrate;

the VCSEL units in the preset region are electrically connected through an electrical connection structure according to the distribution of the preset region to form at least two sub-chips, wherein a preset distance for preventing heat generated by each sub-chip in the at least two sub-chips from influencing the output optical power of the adjacent sub-chips is arranged between the sub-chips;

forming an electrical isolation region between each two of the sub-chips; and

the at least two sub-chips are connected in series by an electrically conductive pattern.

In the manufacturing method according to the present application, forming an electrical isolation region between each two of the sub-chips includes: and forming the electric isolation region between every two sub-chips through an ion implantation process.

In the manufacturing method according to the present application, forming an electrical isolation region between each two of the sub-chips includes: the electrically isolated regions are formed between each two of the chiplets by an etching process.

In the fabrication method according to the present application, the width of the electrically isolated region ranges from 1nm to 100 um.

In the manufacturing method according to the present application, the preset pitch is greater than or equal to 4 um.

Further objects and advantages of the present application will become apparent from an understanding of the ensuing description and drawings.

These and other objects, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the claims.

Drawings

These and/or other aspects and advantages of the present application will become more apparent and more readily appreciated from the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings of which:

fig. 1A illustrates a schematic diagram of a VCSEL chip in accordance with an embodiment of the present application.

FIG. 1B illustrates a cross-sectional schematic view of the VCSEL chip illustrated in FIG. 1A.

Fig. 2 illustrates a schematic diagram of a VCSEL unit of the VCSEL chip in accordance with an embodiment of the present application.

Figure 3 illustrates another schematic diagram of the VCSEL unit in accordance with an embodiment of the present application.

Figure 4 illustrates another schematic diagram of the VCSEL chip in accordance with an embodiment of the present application.

Figure 5 illustrates yet another schematic diagram of the VCSEL chip in accordance with an embodiment of the present application.

Figure 6A illustrates yet another schematic diagram of the VCSEL chip in accordance with an embodiment of the present application.

Figure 6B illustrates a cross-sectional view of the VCSEL chip along line AA' as illustrated in figure 6A.

Figure 6C illustrates a cross-sectional view of the VCSEL chip along line BB' as illustrated in figure 6A.

Detailed Description

The terms and words used in the following specification and claims are not limited to the literal meanings, but are used only by the applicant to enable a clear and consistent understanding of the application. Accordingly, it will be apparent to those skilled in the art that the following descriptions of the various embodiments of the present application are provided for illustration only and not for the purpose of limiting the application as defined by the appended claims and their equivalents.

It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.

While ordinal numbers such as "first," "second," etc., will be used to describe various components, those components are not limited herein. The term is used only to distinguish one element from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the teachings of the inventive concepts. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, numbers, steps, operations, components, elements, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, elements, or groups thereof.

Illustrative VCSEL chip

The VCSEL chip 10 according to the embodiment of the present application includes a plurality of sub-chips connected in series, each of the sub-chips includes a predetermined number of VCSEL units 100, and a predetermined distance is provided between the sub-chips to prevent heat generated by each of the sub-chips from affecting output optical power of adjacent sub-chips, so that the VCSEL chip 10 can achieve a large optical power output under relatively small current driving, and the VCSEL chip 10 has good high temperature performance. The high temperature performance capability of the VCSEL chip 10 represents: the VCSEL chip 10 is in a high temperature environment, the optical power thereof can be stably output, and a power drop phenomenon does not occur.

In particular, in the embodiment of the present application, the VCSEL chip 10 can achieve a large optical power output under a relatively small current driving, and the VCSEL chip 10 has a good high temperature performance capability.

The VCSEL chip 10 is described below with the VCSEL chip 10 including two sub-chips as an example.

As shown in fig. 1A and 1B, in the embodiment of the present application, the VCSEL chip 10 includes a substrate 13, a first sub-chip 11 and a second sub-chip 12 molded on the substrate 13, and an electrical conduction pattern 14, wherein the first sub-chip 11 includes a predetermined number of VCSEL units 100 to form a first light emitting area 110, the second sub-chip 12 includes a predetermined number of VCSEL units 100 to form a second light emitting area 120, and the electrical conduction pattern 14 connects the first sub-chip 11 and the second sub-chip 12 in series. In particular, in the embodiment of the present application, the number of the first sub-chip 11 and the second sub-chip including the VCSEL units 100 ranges. In the embodiment of the present application, the substrate 13 may be made of a conductive material or a non-conductive material, that is, the substrate 13 may be the conductive substrate 13 or the non-conductive substrate 13, and the present application is not limited thereto.

As shown in fig. 1A, in the embodiment of the present application, the first sub-chip 11 further includes a P electrode 111 and an N electrode 112 for conducting the first light emitting region 110, wherein when the P electrode 111 and the N electrode 112 are conducted, the VCSEL unit 100 in the first light emitting region 110 is conducted to generate laser light. The second sub-chip 12 further includes a P-electrode 121 and an N-electrode 122 for conducting the second light emitting region 120, wherein when the P-electrode 121 and the N-electrode 122 are conducted, the VCSEL unit 100 in the second light emitting region 120 is conducted to generate laser light. It should be noted that, in the embodiment of the present application, the VCSEL units 100 of the first sub-chip 11 and the second sub-chip 12 may be implemented as VCSEL units 100 emitting light from the front side, and may also be VCSEL units 100 emitting light from the back side, which is not limited by the present application.

Further, in the embodiment of the present application, the electrically conductive pattern 14 electrically connects the P-electrode 111 of the first sub-chip 11 to the N-electrode 122 of the second sub-chip 12, or electrically connects the N-electrode 112 of the first sub-chip 11 to the P-electrode 121 of the second sub-chip 12, in such a way that the first sub-chip 11 and the second sub-chip 12 are conductively connected in series. That is, in the embodiment of the present application, the electrically conductive pattern 14 includes a positive electrode 141 and a negative electrode 142, wherein the positive electrode 141 may be the P-electrode 111 of the first sub-chip 11 or the P-electrode 121 of the second sub-chip 12, the negative electrode 142 may be the N-electrode 112 of the first sub-chip 11 or the N-electrode 122 of the second sub-chip 12, and when an external power is applied to the positive electrode 141 and the negative electrode 142 of the electrically conductive pattern 14, the first sub-chip 11 and the second sub-chip 12 connected in series with each other are simultaneously turned on.

It should be noted that the VCSEL chip 10 according to the embodiment of the present application can also achieve the effect of lighting in a divisional manner, for example, the first sub-chip 11 or the second sub-chip 12 is separately turned on, or the first sub-chip 11 and the second sub-chip 12 are turned on simultaneously.

Since the first sub-chip 11 and the second sub-chip 12 are interconnected in a serial manner, it is very important to divide the areas of the first sub-chip 11 and the second sub-chip 12. Accordingly, as shown in fig. 1A and 1B, in the embodiment of the present application, an electrical isolation region 15 is disposed between the first sub-chip 11 and the second sub-chip 12, wherein the electrical isolation region 15 is formed between every two sub-chips by means of ion arrangement, so as to divide the first sub-chip 11 and the second sub-chip 12 on the substrate 13 by the electrical isolation region 15. More specifically, in the embodiment of the present application, the electrically isolating region 15 extends downward to the substrate 13 between the first sub-chip 11 and the second sub-chip 12 to divide the first sub-chip 11 and the second sub-chip 12, so as to prevent a short circuit from occurring between the first sub-chip 11 and the second sub-chip 12.

Further, as shown in fig. 1A and 1B, in the embodiment of the present application, there is a predetermined interval between the first light-emitting area 110 including a plurality of VCSEL units 100 and the second light-emitting area 120 including a plurality of VCSEL units 100, so that when the first light-emitting area 110 and the second light-emitting area 120 emit light simultaneously, the heat generated by the first light-emitting area 110 does not affect the optical power output characteristics of the VCSEL units 100 in the second light-emitting area 120, and the heat generated by the second light-emitting area 120 does not affect the optical power output characteristics of the VCSEL units 100 in the first light-emitting area 110. In particular, in the embodiment of the present application, the preset distance between the first light-reflecting area 110 and the second light-emitting area 120 is greater than or equal to 4um, and the width range of the electrical isolation area 15 is: 1nm to 100 um.

In the embodiment of the present application, the number of VCSEL units 100 included in the VCSEL chip 10 ranges from 4 to 2000, and the number of VCSEL units 100 included in each of the sub-chips (i.e., the first sub-chip 11 and the second sub-chip 12) ranges from 100 to 750, and preferably, the total number of VCSEL units 100 included in the VCSEL chip ranges from 400 to 1500, so as to obtain a product with an average output power of 3W to 15W. If the shape and size of the VCSEL chip 10 is set to a square configuration of 1.5mm by 1.5mm, the output power range of the VCSEL chip 10 is preferably set to 3W to 15W.

More specifically, in the embodiment of the present application, when the VCSEL chip 10 uses a single epitaxial wafer and includes two sub-chips, the relationship between the input current of the VCSEL chip 10 and the output power thereof is: the input current is 1.55A, and the obtained output peak power is 3W; the input current is 7.25A, and the output peak power is 15W. Accordingly, it should be appreciated that if the power requirement for the VCSEL chip 10 is greater, i.e., the number of VCSEL units 100 it contains is greater, it is more advantageous for the application of the VCSEL chip 10 to be able to output greater power. For example, when the VCSEL chip 10 uses a single epitaxial wafer and includes three of the sub-chips, the relationship between the input current of the VCSEL chip 10 and its output power is: the input current is 1.3A, and the output peak power is 3W; the input current is 5.25A, and the output peak power is 15W. As another example, when the VCSEL chip 10 uses three epitaxial wafers and includes two sub-chips, the relationship between the input current of the VCSEL chip 10 and the output power thereof is: the input current is 0.6A, and the output peak power is 3W; the input current is 2.9A, and the output peak power is 15W.

It should be understood that in the embodiments of the present application, the performance and fabrication process of the VCSEL chip 10 are not as closely related to the structure of the VCSEL unit 100.

Fig. 2 illustrates a schematic diagram of an example of a VCSEL unit 100 of the VCSEL chip 10 according to an embodiment of the present application. As shown in fig. 2, in this example, the VCSEL unit 100 illustrated in fig. 2 is a conventional oxidizing VCSEL unit 100 having a mesa structure, which includes, from bottom to top, a substrate 01, a buffer layer 02, an N-type doped DBR 03, an active region 04, a confinement layer 05, a P-type doped DBR 06, and an ohmic contact layer 07, wherein the active region 04 is sandwiched between the P-type doped DBR 06 and the N-type doped DBR 03 to form a resonant cavity. Further, an N-electrode 09 is formed on the lower surface of the substrate 01, and a P-electrode 08 is formed on the upper surface of the ohmic contact layer 07.

In operation, the VCSEL unit 100 can achieve laser excitation by satisfying the following two conditions: (1) particle number inversion process: in the case where there is population inversion in the active region 04 to make the gain provided by the laser medium sufficiently exceed the loss, when current is injected through the first electrode 09 and the second electrode 08, the light intensity will continuously increase, and when electrons at the bottom of the conduction band of the high energy state transition to a low energy band, the amplification process is repeated as light of a specific wavelength is reflected back and forth between the P-type doped DBR 06 and the N-type doped DBR 03, so as to form laser light; (2) a resonant cavity: the cavity resonator is mainly used for providing a cavity through multiple optical energy feedbacks when light generated in the active region 04 is reflected back and forth between the P-type doped DBR 06 and the N-type doped DBR 03, stimulated radiation is fed back for multiple times to form laser oscillation, and the VCSE unit 100 can project laser after being conducted.

It should be noted that, in the embodiments of the present application, the selection of the materials of the layers of the VCSEL unit 100 is not limited by the present application. For example, in the embodiment of the present application, the substrate 01 may include, but is not limited to, a silicon substrate, a sapphire substrate, a potassium arsenide substrate, and the like; materials of the P-type doped DBR 06 and the N-type doped DBR 03 include, but are not limited to: InGaAsP/InP, AlGaInAs/AlInAs, AlGaAsSb/AlAsSb, GaAs/AlGaAs, Si/MgO, and Si/Al2O3, etc.

It should be understood that in the embodiment of the present application, the substrate 01 of each VCSEL unit 100 forms a base 13 of the VCSEL chip. Alternatively, the VCSEL units 100 share a substrate 01 to form the base 13.

In particular, in this example, the light emitting aperture of the VCSEL unit 100 ranges from 5um to 30um, preferably from 8um to 18 um.

Fig. 3 illustrates another schematic diagram of the VCSEL unit 100 according to an embodiment of the present application, wherein the VCSEL unit 100 illustrated in fig. 3 is an external cavity VCSEL unit 100 comprising an active region 14A, the active region 14A being set between a first semiconductor region forming a first reflector 13A and a second semiconductor region forming a second reflector 16A. The active region 14A includes quantum wells, which may be made of aliningaas (e.g., AlInGaAs, AlGaAs, and InGaAs), InGaAsP (e.g., InGaAsP, GaAs, InGaAs, GaAsP, and GaP), GaAsSb (e.g., GaAsSb, GaAs, and GaSb), InGaAsN (e.g., InGaAsN, GaAs, InGaAs, GaAsN, and GaN), or aliningaasp (e.g., aliningaasp, aliningaas, AlGaAs, InGaAs, InGaAsP, GaAs, InGaAs, GaAsP, and GaP), and the active region 14A may also be made of other compositions for forming quantum well layers.

The first Reflector 13A and the second Reflector 16A each comprise a system of alternating layers of materials of different refractive index, which form a Distributed Bragg Reflector (Distributed Bragg Reflector). The choice of material for the alternating layers depends on the desired operating wavelength of the laser. For example, in one example, the first reflector 13A and the second reflector 16A may be formed of alternating layers of high aluminum content AlGaAs and low aluminum content AlGaAs. In particular, in this example, the first reflector 13A is an N-doped distributed bragg reflector, i.e., an N-DBR, and the second reflector 14A is a P-doped distributed bragg reflector, i.e., a P-DBR.

As shown in fig. 3, the VCSEL unit 100 further includes a first electrode 17A electrically connected to the upper surface of the second reflector 16A, a second electrode 18A electrically connected to the exposed portion of the upper surface of the second reflector 16A, and an insulating layer covering at least a portion of the first mesa, at least a portion of the second mesa, at least a portion of the exposed portion of the upper surface of the first reflector 13A, and at least a portion of the upper surface of the second reflector 16A.

During operation, an operating voltage is applied to the first electrode 17A and the second electrode 18A of the VCSE cell 100 to generate a current in the semiconductor structure, wherein the current is confined by the oxide confinement layer 15A formed over the active region 14A, which is ultimately directed into the middle region of the semiconductor structure to cause lasing in the middle region of the active region 14A.

As shown in fig. 3, the active region 14A is sandwiched between the first reflector 13A and the second reflector 16A to form a resonant cavity, wherein photons are repeatedly amplified by being reflected back and forth in the resonant cavity after being excited to form laser oscillation, so that laser light is formed. In particular, in the present embodiment, the first reflector 13A and the second reflector 16A are configured such that laser light exits from the first reflector 13A after oscillating within the resonant cavity. For ease of understanding and explanation, in the present embodiment, a resonant cavity set between the first reflector 13A and the second reflector 16A is defined as an "inner cavity".

Further, the external cavity VCSEL unit 100 further includes a reflective layer 11A formed on a lower surface of the substrate 12A to form a second oscillation cavity between the reflective layer 11A and the first reflector 13A. For ease of understanding and explanation, the second oscillation cavity is defined herein as an "external cavity". Specifically, the laser light emitted from the first reflector 13A can further oscillate within the external cavity to improve the optical performance of the laser light finally emitted from the bottom surface of the external cavity VCSEL unit 100. More specifically, the external cavity VCSEL unit 100 has a higher output power and a higher brightness.

It should be understood that the external cavity VCSEL unit 100 has a relatively longer optical cavity length (total path of movement of photons within the external cavity VCSEL unit 100 from excitation to light emission) than the VCSEL unit 100 illustrated in fig. 2, in which the external cavity VCSEL unit 100 has an additional oscillation cavity. Therefore, the external cavity VCSEL unit 100 has higher output power and higher brightness compared to the external cavity VCSEL unit 100 illustrated in fig. 2.

In particular, in this example, the light emitting aperture of the VCSEL unit 100 ranges from 5um to 30um, preferably from 8um to 18 um.

It should be noted that in the VCSEL unit 100 as illustrated in fig. 2 and 3, it has only one PN junction, and it should be understood that in other examples of the present application, the VCSEL unit 100 can also be implemented as a VCSEL unit 100 including multiple PN junctions, and the present application is not limited thereto.

The following describes a process for manufacturing the VCSEL chip 10 according to the embodiment of the present application, taking the VCSEL unit 100 as a conventional oxide VCSEL with a mesa structure as an example.

Firstly, forming a substrate 13;

next, an epitaxial structure is formed on the substrate 13 through, for example, a metal deposition process, wherein the epitaxial structure includes, from top to bottom, the substrate 01, the buffer layer 02, the N-type doped DBR 03, the active region 04, and the P-type doped DBR 06, wherein the active region 04 is sandwiched between the P-type doped DBR 06 and the N-type doped DBR 03 to form a resonant cavity.

Then, the epitaxial structure is etched by an etching process (e.g., a photo-etching or chemical etching process) to form a mesa structure;

then, oxidizing the mesa structure to form the confinement layer over the active region;

then, the VCSEL units 100 in a preset region are electrically connected according to a preset region distribution through an electrical connection structure to form the first sub-chip 11 and the second sub-chip 12, wherein a preset distance is provided between the first sub-chip 11 and the second sub-chip 12.

Next, forming an electrical isolation region 15 between the first sub-chip 11 and the second sub-chip 12 through an ion implantation process;

then, the first sub-chip 11 and the second sub-chip 12 are connected in series through the electrically conductive patterns 14.

It should be noted that, in the process of manufacturing the VCSEL chip 10, when the VCSEL unit 100 is implemented as a VCSEL unit 100 with other structure, some adaptive adjustments need to be performed in the process of manufacturing the VCSEL chip 10, and thus, the details are not repeated.

Fig. 4 illustrates another schematic diagram of the VCSEL chip 10 according to an embodiment of the present application, wherein fig. 4 illustrates another way of electrically isolating the first chiplet 11 from the second chiplet 12. As shown in fig. 4, in this variant embodiment, the electrically isolating region 15 is implemented as an isolating slot, which is formed between the first chiplet 11 and the second chiplet 12 by an etching process. In particular, in this variant embodiment, the electrically isolated region 15 is recessed downwards from the middle between the first chiplet 11 and the second chiplet 12 and extends to the base 13.

It is worth mentioning that although the VCSEL chip 10 includes the first sub-chip 11 and the second sub-chip 12 as an example, it should be understood by those skilled in the art that in other examples of the present application, the VCSEL chip 10 can include a larger number of sub-chips to form a larger number of light emitting areas, for example, in the VCSEL chip 10 illustrated in fig. 5, the VCSEL chip 10 further includes a third sub-chip 16 connected in series with the first sub-chip 11 and the second sub-chip 12, wherein the third sub-chip forms a third light emitting area 160.

It is worth mentioning that when the VCSEL chip 10 includes a larger number of sub-chips, it can obtain a larger output power with a relatively smaller current.

It should be noted that, in the VCSEL chip 10 as illustrated in fig. 1A and 1B, the positive electrode 141 and the negative electrode 142 of the electrical conduction pattern 14 are formed on the same side surface of the VCSEL chip 10, i.e., the upper surface or the lower surface of the VCSEL chip 10. Such a structural configuration facilitates implementation of the packaging scheme of the VCSEL chip 10. Of course, in other examples of the present application, the positive electrode 141 and the negative electrode 142 of the electrical conduction pattern 14 may also be respectively disposed on opposite side surfaces of the VCSEL chip 10, for example, in the VCSEL chip 10 as illustrated in fig. 6A to 6C, the positive electrode 141 of the electrical conduction pattern 14 is formed on an upper surface of the VCSEL chip 10, and the negative electrode 142 of the electrical conduction pattern 14 is formed on a lower surface of the VCSEL chip 10, which is not limited by the present application.

In summary, the VCSEL chip 10 according to the embodiment of the present application is illustrated, and includes a plurality of sub-chips connected in series, each of the sub-chips includes a predetermined number of VCSEL units 100, so that the VCSEL chip 10 can achieve a large optical power output under a relatively small current driving, and the VCSEL chip 10 has a good high temperature performance.

Accordingly, the VCSEL chip 10 according to the embodiment of the present application has at least the following advantages:

1. the low current input and the high power output are beneficial to the design of the peripheral driver circuit.

2. The condition that the high-temperature characteristics of the multiple PN junctions are poor can be avoided.

3. The difficulty of the internal epitaxial structure of the multiple PN junctions can be avoided.

4. The division of the regions can be achieved by using an ion implantation process and an etching process.

5. The division of different light-emitting areas is complementary to the process of the existing foundry, and can be finished in one run in the foundry.

6. The VCSEL chip 10 is suitable for use as a structured light source, an IToF light source, a DTOF light source, a speckle light source, and the like.

7. The VCSEL chip 10 is not limited to the epitaxial structure of the VCSEL unit 100, and includes a single PN junction, a multiple PN junction, and the like.

8. The VCSEL chip 10 can be manufactured to have a cathode coplanar with an anode, which is beneficial to future Flip chip packaging modes and the like.

9. The VCSEL chip 10 can be fabricated with the cathode and anode non-coplanar, consistent with many consumer products currently in use.

10. Is very beneficial to future AR application, distance measurement application and optical radar scanner.

The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.

The block diagrams of devices, apparatuses, systems referred to in this application are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".

It should also be noted that in the devices, apparatuses, and methods of the present application, the components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered as equivalents of the present application.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for the purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.