阅读说明：本技术 一种在硅上制作垂直腔面发射激光器阵列的方法 (Method for manufacturing vertical cavity surface emitting laser array on silicon ) 是由 王冰 施裕庚 陈哲茜 余思远 于 2021-08-16 设计创作，主要内容包括：本发明公开了一种在硅上制作垂直腔面发射激光器阵列的方法,所述方法包括：在硅衬底上外延生长缓冲层之后,利用氮化硅或二氧化硅介质薄膜作为掩膜,用来定义后续外延生长的VCSEL的尺寸和形状,以及缓解大面积薄膜外延时由热膨胀系数失配导致的薄膜开裂和晶圆翘曲,从而制造出器件尺寸较小的VCSEL阵列,减小单个VCSEL中位错缺陷的数量或避开位错缺陷的影响,并通过进一步优化VCSEL的尺寸和阵列排布方式,以提高阵列器件的完好率,最终提高硅衬底上外延生长的VCSEL的性能和可靠性。(The invention discloses a method for manufacturing a vertical cavity surface emitting laser array on silicon, which comprises the following steps: after the buffer layer is epitaxially grown on the silicon substrate, the silicon nitride or silicon dioxide dielectric film is used as a mask to define the size and the shape of the VCSEL which is subsequently epitaxially grown, and the film cracking and the wafer warping caused by the mismatch of the thermal expansion coefficient of the large-area film external delay are relieved, so that the VCSEL array with a smaller device size is manufactured, the number of dislocation defects in a single VCSEL is reduced or the influence of the dislocation defects is avoided, the perfectness of the array device is improved by further optimizing the size and the array arrangement mode of the VCSEL, and finally the performance and the reliability of the VCSEL which is epitaxially grown on the silicon substrate are improved.)

1. A method of fabricating a vertical cavity surface emitting laser array on silicon, comprising the steps of:

s1: epitaxially growing a germanium buffer layer on a silicon (001) wafer by chemical vapor deposition;

s2: epitaxially growing a doped gallium arsenide buffer layer on the germanium buffer layer by utilizing metal organic chemical vapor deposition or molecular beam epitaxy equipment or other III-V semiconductor epitaxial growth equipment, wherein the doped gallium arsenide buffer layer is used as a lower electrode of the VCSEL;

s3: depositing a layer of silicon dioxide or silicon nitride film on the gallium arsenide buffer layer by using a chemical vapor deposition method;

s4: making a VCSEL epitaxial growth mask pattern in the silicon dioxide or silicon nitride film by using an exposure and etching method;

s5: epitaxially growing the whole epitaxial structure of the VCSEL on the mask pattern by utilizing metal organic chemical vapor deposition or molecular beam epitaxy equipment or other III-V semiconductor epitaxial growth equipment;

s6: and (4) completing the fabrication of the VCSEL by utilizing a common VCSEL fabrication process on the whole epitaxial structure of the grown VCSEL.

2. A method of fabricating a vcsel array on silicon according to claim 1, wherein said germanium buffer layer is no more than 1 micron.

3. The method of claim 1, wherein the mask pattern has an opening with a size equal to that of the VCSEL, and the GaAs buffer layer is exposed in the opening of the mask.

4. A method of fabricating a vcsel array on silicon according to claim 1, wherein the silicon (001) wafer has a bevel angle such that the surface has diatomic steps; or a diatomic step can be formed after surface heat treatment, and the diatomic step characteristics are continuously transferred to the surface of the germanium buffer layer, so that the formation of an anti-phase domain can be inhibited when the gallium arsenide buffer layer is epitaxially grown.

5. A method for fabricating an array of vertical cavity surface emitting lasers on silicon as claimed in claim 1 wherein said germanium buffer layer mitigates lattice mismatch and a majority of dislocation defects are localized at the interface of the germanium buffer layer and the silicon substrate with a threading dislocation density at the surface of no more than 1 x 10⁷cm^-2。

6. A method according to claim 1, wherein said gaas buffer layer and said ge buffer layer have a lattice mismatch of less than 0.1%, and wherein said threading dislocation density is no higher than said ge buffer layer and there are no anti-domain, stacking fault lattice defects.

7. A method for fabricating VCSEL arrays on silicon as claimed in claim 6 wherein the GaAs buffer layer is doped N-type or P-type so that it can serve as an electrode contact layer for VCSELs.

8. A method of fabricating a VCSEL array on silicon as claimed in claim 1 wherein the mask pattern of silicon dioxide or silicon nitride fabricated by steps S3 and S4 has a size corresponding to a size of a VCSEL device to be fabricated, and the size ranges from 1 micron to 100 microns.

9. A method of fabricating a VCSEL array on silicon as in claim 1, wherein the mask pattern is also arranged in accordance with the VCSEL array.

10. A method for fabricating a VCSEL array on silicon as claimed in claim 1, wherein the epitaxial growth VCSEL has a whole epitaxial structure comprising upper and lower bragg reflectors, quantum well active regions of the VCSEL, and electrode contact layers in step S5, which is the same as the common VCSEL epitaxial structure;

the VCSEL to be fabricated will be epitaxially grown in the opening portion of the silicon dioxide or silicon nitride mask pattern, i.e. the exposed gallium arsenide surface, and the three-dimensional shape of the VCSEL will be defined and realized by the mask pattern, wherein the bottom electrode of the VCSEL can be served by the originally epitaxially grown gallium arsenide buffer layer.

Technical Field

The present invention relates to the field of integrated optoelectronic devices and semiconductor material technology, and more particularly, to a method of fabricating vertical cavity surface emitting laser arrays on silicon.

Background

Vertical Cavity Surface Emitting Lasers (VCSELs) have the characteristics of compact structure, large direct modulation bandwidth, easiness in array manufacture, easiness in coupling with optical fibers and the like, and have important application in short-distance optical communication. In the current big data age, massive data needs to be transmitted inside a data center, and a light emitting module or a cable with a VCSEL as a core is widely applied in the data center. In recent years, the application of the VCSEL is further expanded to the fields of face recognition, 3D sensing, automatic driving, and the like, and the application market thereof is rapidly expanded. Another important potential application of VCSELs is integration with silicon chips, on the one hand with silicon-based control modules to realize integrated sensing or communication chips; and the other aspect is that the light source is integrated with a silicon optical chip, and the VCSEL is used as the light source of the silicon optical chip. However, since most of VCSELs with short wavelength (emission wavelength below 1000 nm) are epitaxially grown on a gallium arsenide substrate, there are several not yet completely solved scientific and technical problems in directly integrating them with a silicon-based control circuit or a silicon optical chip:

it is very difficult to epitaxially grow a gallium arsenide-based VCSEL directly on silicon. The material properties of silicon and gallium arsenide are different, and lattice, polarity and thermal expansion coefficient mismatch exist, which can cause a large number of material defects such as mismatch/threading dislocation, inversion domains, stacking faults and the like to appear in the gallium arsenide single crystal film directly epitaxially grown on silicon, and wafer warpage and film cracking caused by the thermal expansion coefficient mismatch. These material defects drastically deteriorate the performance, reliability and lifetime of the VCSEL, rendering it useless for practical use. The Threading dislocation is an important defect affecting the performance and reliability of the laser, and the density (TDD) of the Threading dislocation is a main index for measuring the defect level of the semiconductor in three five groups such as gallium arsenide heteroepitaxially grown on silicon. The lowest TDD currently available for epitaxially growing gallium arsenide on silicon is about 10⁶cm^-2This is still too high for making high performance, long-lived lasers.

Good quality devices can be obtained by transferring VCSELs fabricated on gaas substrates to silicon by wafer bonding or flip chip bonding, but these methods are limited by their own limitations, such as wafer level integration and fabrication, for example, VCSELs are currently fabricated mainly on gaas wafers with a diameter of 6 inches, but the production line of 6 inch diameter silicon wafers is rare, direct wafer level integration is inconvenient, and the reliability of these methods is yet to be tested. These techniques are therefore not yet mature.

The publication number is CN109449760A Chinese invention patent. Disclosed at 20 is a vertical cavity surface emitting laser array module and a display device, the vertical cavity surface emitting laser array module including an active matrix display control circuit substrate; the first distributed Bragg reflection grating forms a reflector array; an array of semiconductor light emitting sublayers; an aperture array that limits current distribution; the second distributed Bragg reflection grating forms a reflector array; the active matrix display control circuit in the active matrix display control circuit substrate drives the semiconductor light emitting sub-layer array to emit light through the metal electrode array. Although the proposal also relates to a vertical cavity surface emitting laser, the proposal does not solve the problem that gallium arsenide-based VCSEL epitaxially grown on a silicon substrate has high defect density and is difficult to obtain the VCSEL with good performance.

Disclosure of Invention

The invention provides a method for manufacturing a vertical cavity surface emitting laser array on silicon, aiming at overcoming the defects that gallium arsenide-based VCSELs epitaxially grown on a silicon substrate in the prior art have higher defect density and are difficult to obtain VCSELs with good performance.

The primary objective of the present invention is to solve the above technical problems, and the technical solution of the present invention is as follows:

a method of fabricating a vertical cavity surface emitting laser array on silicon, comprising the steps of:

s1: epitaxially growing a germanium buffer layer on a silicon (001) wafer by chemical vapor deposition;

s2: epitaxially growing a doped gallium arsenide buffer layer on the germanium buffer layer by utilizing metal organic chemical vapor deposition or molecular beam epitaxy equipment or other III-V semiconductor epitaxial growth equipment, wherein the doped gallium arsenide buffer layer is used as a lower electrode of the VCSEL;

s3: depositing a layer of silicon dioxide or silicon nitride film on the gallium arsenide buffer layer by using a chemical vapor deposition method;

s4: making a VCSEL epitaxial growth mask pattern in the silicon dioxide or silicon nitride film by using an exposure and etching method;

s5: epitaxially growing the whole epitaxial structure of the VCSEL on the mask pattern by utilizing metal organic chemical vapor deposition or molecular beam epitaxy equipment or other III-V semiconductor epitaxial growth equipment;

s6: the fabrication of the VCSEL is completed on the overall epitaxial structure of the grown VCSEL using a common VCSEL fabrication process, wherein the bottom electrode of the VCSEL can be served by an initially epitaxially grown gallium arsenide buffer layer.

Further, the germanium buffer layer is no more than 1 micron.

Furthermore, the size of the opening of the mask pattern is the same as that of the VCSEL, and the surface of the GaAs buffer layer is exposed in the opening of the mask.

Further, the silicon (001) wafer should have a certain crystal orientation bevel angle, so that the surface thereof has diatomic steps; or a diatomic step can be formed after surface heat treatment, and the diatomic step characteristics are continuously transferred to the surface of the germanium buffer layer, so that the formation of an anti-phase domain can be inhibited when the gallium arsenide buffer layer is epitaxially grown.

Furthermore, the germanium buffer layer can relieve lattice mismatch, most dislocation defects are positioned at the interface of the germanium buffer layer and the silicon substrate, and the threading dislocation density of the surface of the germanium buffer layer is not higher than 1 multiplied by 10⁷cm^-2。

Furthermore, the lattice mismatch between the gallium arsenide buffer layer and the germanium buffer layer is less than 0.1%, the threading dislocation density is not higher than that of the germanium buffer layer, and the gallium arsenide buffer layer and the germanium buffer layer have no anti-phase domain and no stacking fault lattice defects.

Further, the gallium arsenide buffer layer should be doped N-type or P-type so that it can act as an electrode contact layer for the VCSEL.

Further, the size of the silicon dioxide or silicon nitride mask pattern fabricated in steps S3 and S4 is consistent with the size of the VCSEL device to be fabricated, and the size ranges from 1 micron to 100 microns.

Further, the arrangement of the mask pattern is also consistent with the VCSEL array.

Further, in step S5, the overall epitaxial structure of the epitaxially grown VCSEL includes upper and lower bragg reflectors, a quantum well active region of the VCSEL, and an electrode contact layer, which is the same as the general VCSEL epitaxial structure;

the VCSEL to be fabricated will be epitaxially grown in the opening portion of the silicon dioxide or silicon nitride mask pattern, i.e. the exposed gallium arsenide surface, and the three-dimensional shape of the VCSEL will be defined and realized by the mask pattern, wherein the bottom electrode of the VCSEL can be served by the originally epitaxially grown gallium arsenide buffer layer.

Compared with the prior art, the technical scheme of the invention has the beneficial effects that:

according to the invention, after the buffer layer is epitaxially grown on the silicon substrate, the silicon nitride or silicon dioxide dielectric film is used as a mask to define the size and the shape of the VCSEL which is subsequently epitaxially grown, and the film cracking and the wafer warping caused by the thermal expansion coefficient mismatch of the large-area film external delay are relieved, so that the VCSEL array with smaller device size is manufactured, the number of dislocation defects in a single VCSEL is reduced or the influence of the dislocation defects is avoided, the perfectness rate of the array device is improved by further optimizing the size and the array arrangement mode of the VCSEL, and finally the performance and the reliability of the VCSEL which is epitaxially grown on the silicon substrate are improved.

Drawings

FIG. 1 is a flow chart of the method of the present invention.

Fig. 2 is a schematic diagram of a VCSEL structure fabricated in accordance with an embodiment of the present invention.

Fig. 3 is a schematic diagram of a VCSEL array fabricated according to an embodiment of the present invention.

Detailed Description

In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.

Example 1

As shown in fig. 1, a method of fabricating a vertical cavity surface emitting laser array on silicon includes the steps of:

s1: epitaxially growing a germanium buffer layer on a silicon wafer with a (001) crystal orientation by using a chemical vapor deposition method;

in the invention, the thickness of the germanium buffer layer is not more than 1 micron, the germanium buffer layer can relieve lattice mismatch, most dislocation defects are positioned at the interface of the germanium buffer layer and the silicon substrate, and the threading dislocation density of the surface of the germanium buffer layer is not higher than 1 multiplied by 10⁷cm^-2。

It should be noted that the silicon (001) wafer should have a certain crystal orientation bevel angle, so that the surface thereof has diatomic steps; or even though no specific crystal orientation is obliquely cut, diatomic steps can be formed after surface heat treatment, and diatomic step characteristics are continuously transferred to the surface of the germanium buffer layer, so that the formation of an anti-phase domain can be inhibited when the gallium arsenide buffer layer is epitaxially grown.

S2: epitaxially growing a doped gallium arsenide buffer layer on the germanium buffer layer by using Metal Organic Chemical Vapor Deposition (MOCVD) or molecular beam epitaxy equipment (MBE) or other III-V semiconductor epitaxial growth equipment, wherein the doped gallium arsenide buffer layer is used as a lower electrode of the VCSEL;

it should be noted that the lattice mismatch between the gallium arsenide buffer layer and the germanium buffer layer is less than 0.1%, the threading dislocation density is not higher than that of the germanium buffer layer, and there is no anti-phase domain and no lattice defect. And the gaas buffer layer should be doped N-type or P-type so that it can serve as an electrode contact layer for the VCSEL.

S3: depositing a layer of silicon dioxide or silicon nitride film on the gallium arsenide buffer layer by using a chemical vapor deposition method;

s4: making a VCSEL epitaxial growth mask pattern in the silicon dioxide or silicon nitride film by using an exposure and etching method; the size of the opening of the mask pattern is the same as that of the VCSEL, and the surface of the GaAs buffer layer is exposed in the opening of the mask.

It should be noted that the size of the silicon dioxide or silicon nitride mask pattern fabricated in steps S3 and S4 is consistent with the size of the VCSEL device to be fabricated, and the size ranges from 1 micron to 100 microns.

S5: epitaxially growing the whole epitaxial structure of the VCSEL on the mask pattern by using Metal Organic Chemical Vapor Deposition (MOCVD) or molecular beam epitaxy equipment (MBE) or other III-V semiconductor epitaxial growth equipment, wherein the whole epitaxial structure comprises an upper Bragg reflector (DBR), a lower Bragg reflector (DBR), a quantum well active region of the VCSEL and an electrode contact layer; the structure is the same as a common VCSEL epitaxial structure;

it should be noted that the VCSEL to be fabricated will be epitaxially grown on the opening portion of the silicon dioxide or silicon nitride mask pattern, i.e. the exposed surface of the gallium arsenide, and the three-dimensional shape of the VCSEL will be defined and realized by the mask pattern.

A schematic diagram of a VCSEL structure fabricated is shown in fig. 2.

S6: the fabrication of the VCSEL is completed on the overall epitaxial structure of the grown VCSEL using a common VCSEL fabrication process, wherein the bottom electrode of the VCSEL can be served by an initially epitaxially grown gallium arsenide buffer layer. Fig. 3 is a schematic diagram of a VCSEL array fabricated according to an embodiment of the present invention.

The invention fully utilizes the smaller device area of the VCSEL, and the threading dislocation density is about 10⁶cm^-2～10⁷cm^-2During the process, the size, the array arrangement and the manufacturing mode of the device are reasonably designed, so that the adverse effect of dislocation defects is avoided as much as possible, and the silicon-based VCSEL laser with higher performance is realized.

The invention is similar to the selective epitaxial growth mode in form, but the physical principle is completely different. In the selective epitaxial growth, the lattice defects such as dislocation, stacking fault and the like generated in the III-V group semiconductor during the heterogeneous epitaxial growth are blocked by the side wall of the dielectric mask pattern by utilizing the depth-to-width ratio of the mask pattern, so that the III-V group semiconductor with higher quality is obtained. The aspect ratio of the dielectric mask pattern in the method must meet certain requirements, such as not less than 2:1, otherwise the dielectric mask cannot effectively block the growth and propagation of lattice defects. The specific size and shape of the silicon dioxide or silicon nitride mask pattern related by the invention do not meet the requirement of selective epitaxial growth, and the silicon dioxide or silicon nitride mask pattern does not play a role in blocking the propagation of lattice defects, and the main role is as follows: 1. to define the shape of the VCSEL; 2. and the film cracking and wafer warping caused by the mismatch of the thermal expansion coefficients of the large-area film external delay are relieved.

The terms describing positional relationships in the drawings are for illustrative purposes only and are not to be construed as limiting the patent;

it should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.