阅读说明：本技术 降低相干测量设备零秒延时波动的方法 (Method for reducing zero second delay fluctuation of coherent measurement equipment ) 是由 蒋文丰 于 2019-09-28 设计创作，主要内容包括：本发明提出的一种降低相干测量设备零秒延时波动的方法,旨在提供一种降低相干测量设备零秒延时波动的电路设计方法。本发明通过下述技术方案予以实现：在相干测量设备的电路设计中,将信号处理电路的低频参考时钟,通过锁相环电路提升到高频时钟,然后将高频时钟信号送给DAC,DAC将高频参考时钟送给现场可编程门阵列FPGA,高频时钟信号通过FPGA内置数字时钟管理模块DCM,在DCM中产生ADC和DAC的工作时钟,并对齐ADC与DAC的工作时钟相位；FPGA内部逻辑处理电路将ADC工作时钟作为系统钟,把ADC采样时刻模糊产生的零秒延时波动控制在一个高频时钟波长内,处理后产生的转发数据,通过数模转换器DAC输出。(The invention provides a method for reducing zero-second delay fluctuation of coherent measurement equipment, and aims to provide a circuit design method for reducing the zero-second delay fluctuation of the coherent measurement equipment. The invention is realized by the following technical scheme: in the circuit design of the coherent measurement equipment, a low-frequency reference clock of a signal processing circuit is promoted to a high-frequency clock through a phase-locked loop circuit, then the high-frequency clock signal is sent to a DAC (digital-to-analog converter), the DAC sends the high-frequency reference clock to a Field Programmable Gate Array (FPGA), the high-frequency clock signal is internally provided with a digital clock management module (DCM) through the FPGA, working clocks of the ADC and the DAC are generated in the DCM, and the working clock phases of the ADC and the DAC are aligned; the FPGA internal logic processing circuit takes an ADC working clock as a system clock, controls zero-second delay fluctuation generated by ADC sampling time blurring within a high-frequency clock wavelength, and outputs forwarding data generated after processing through a digital-to-analog converter (DAC).)

1. A method for reducing zero second delay fluctuation of coherent measurement equipment is characterized by comprising the following steps: in the circuit design of the coherent measurement equipment, a low-frequency reference clock of a signal processing circuit is promoted to a high-frequency clock through a phase-locked loop circuit, then a high-frequency clock signal is sent to a digital-to-analog converter (DAC), the DAC sends the high-frequency reference clock to a Field Programmable Gate Array (FPGA), the high-frequency clock signal passes through a digital clock management module (DCM) built in the FPGA, working clocks of the ADC and the DAC are generated in the DCM, and the working clock phases of the ADC and the DAC are aligned; the FPGA internal logic processing circuit takes an ADC working clock as a system clock, controls zero-second delay fluctuation generated by ADC sampling time blurring within a high-frequency clock wavelength, and outputs forwarding data generated after processing through a digital-to-analog converter (DAC).

2. The method of reducing zero second delay ripple in a coherent measurement device of claim 1, wherein: the FPGA digital processing circuit system clock and the ADC sampling reference clock are high-frequency clocks.

3. The method of reducing zero second delay ripple in a coherent measurement device of claim 1, wherein: the ADC sampling instant ambiguity is set to 1 high frequency clock wavelength.

Technical Field

The invention relates to a technology used in aerospace measurement and control, in particular to a method for reducing zero-second delay fluctuation of coherent measurement equipment through hardware circuit design.

Background

In space measurement and control, a coherent measurement method is usually adopted to complete distance measurement of a flying target, and a coherent forwarding device is installed on an aircraft platform and cooperates with a ground measurement and control station to complete a distance measurement task. Taking the case of satellite-ground radio measurement and control, the ground station modulates the ranging signal to an uplink carrier and transmits the uplink carrier, and the satellite-based coherent measurement device (generally called a measurement and control transponder) processes the received signal, wherein the processing of the ranging signal can adopt a relatively simple transparent transmission mode or a regeneration mode. And the processed ranging signals are modulated to downlink carriers again, the ranging signals received by the ground station and the local ranging signals are subjected to correlation operation to obtain signal transmission delay, and the distance is obtained through conversion. The signal transmission delay measured by the method comprises the real transmission time of the ranging signal in the space and the processing delay of the ranging signal in the coherent measurement equipment. The processing delay of the ranging signal in the coherent measurement equipment is called zero second delay, and the zero second delay needs to be deducted from the finally measured distance parameter. Due to the difference of parameter variation and design mode of circuit components, the zero-second delay parameter of each startup of the coherent measurement equipment has difference, and the difference is called zero-second delay fluctuation.

For the transparent transmission mode, the operations of frequency conversion, filtering, amplification and the like are only needed to be carried out on signals in an analog domain, the operations of signal regeneration and the like are not needed, and zero-second delay fluctuation is only related to the characteristics of components. For the regeneration mode, digital signal processing needs to be performed on the ranging signals to realize the processing and regeneration of the ranging signals, ADC and DAC conversion and digital signal processing need to be performed on the ranging signals to complete the processing and regeneration of the ranging signals, and the digital signal processing is completed through a field programmable gate array FPGA. The traditional distance measurement signal digital processing circuit sends a reference clock to an FPGA (field programmable gate array), and the FPGA respectively sends the reference clock to an ADC (analog to digital converter) and a DAC (digital to analog converter) to be used as sampling clocks. The reference clock of the traditional digital signal processing method is generally about 100MHz under the limitation of the frequency of an internal working clock of an FPGA device, and because the rising edge position of the reference clock has uncertainty when the computer is started every time, the sampling time of the ADC is fuzzy. Due to the initial phase difference of the reference clock after each startup, the sampling clock edge of the ADC sampling time has sampling time ambiguity of one wavelength, and when 100MHz sampling is used, the zero-second delay fluctuation of the measurement and control transponder caused by the sampling time ambiguity of the ranging signal ADC during each startup is 3 meters. In order to improve the measurement accuracy of the space measurement and control system, zero-second delay fluctuation of coherent measurement equipment needs to be reduced so as to accurately measure the distance of the aircraft.

Disclosure of Invention

In order to overcome the problem of overlarge zero-second delay fluctuation caused by fuzzy sampling time of an ADC (analog to digital converter) of the conventional digital signal processing circuit, the invention aims to provide a method for reducing the zero-second delay fluctuation of coherent measurement equipment.

The technical scheme adopted by the invention for solving the technical problems is as follows: a method for reducing zero second delay fluctuation of coherent measurement equipment is characterized by comprising the following steps: in the circuit design of the coherent measurement equipment, a low-frequency reference clock of a signal processing circuit is promoted to a high-frequency clock through a phase-locked loop circuit, then a high-frequency clock signal is sent to a digital-to-analog converter (DAC), the DAC sends the high-frequency reference clock to a Field Programmable Gate Array (FPGA), the high-frequency clock signal passes through a digital clock management module (DCM) built in the FPGA, working clocks of the ADC and the DAC are generated in the DCM, and the working clock phases of the ADC and the DAC are aligned; the FPGA internal logic processing circuit takes an ADC working clock as a system clock, controls zero-second delay fluctuation generated by ADC sampling time blurring within a high-frequency clock wavelength, and outputs forwarding data generated after processing through a digital-to-analog converter (DAC).

Compared with the prior art, the invention has the following beneficial effects:

the zero-second delay fluctuation of the coherent measurement equipment can be obviously reduced. According to the invention, the low-frequency reference clock is converted into the high-frequency clock through the phase-locked loop, the high-frequency clock is used as the DAC working clock and is sent to the FPGA, and the digital clock management module DCM in the FPGA generates the ADC sampling clock with the same phase as the DAC, so that the phase alignment of the ADC sampling clock and the DAC working clock is ensured. The phase alignment of the ADC sampling clock and the clock of the DAC modulator can ensure that the processing time of the measurement signal in the FPGA is fixed, and zero-second delay fluctuation caused by uncertainty of the clock phase is eliminated. The FPGA controls zero-second delay fluctuation generated by ADC sampling time blurring within a high-frequency clock wavelength by taking an ADC sampling clock as a digital processing circuit system clock, so that the zero-second delay fluctuation of coherent measurement equipment can be greatly reduced.

According to the invention, a low-frequency reference clock is converted into a high-frequency clock to be used as an ADC reference clock, and the FPGA can control zero-second delay fluctuation of coherent measurement equipment caused by ADC sampling time blurring within a high-frequency clock wavelength.

The invention combines the FPGA and ADC sampling clock phases of the signal processing circuit with the DAC, simultaneously considers the flexibility of the signal processing circuit and the reliability of the analog circuit, and reduces the cost.

Drawings

The patent is further described below with reference to the drawings and examples.

FIG. 1 is a schematic diagram of a circuit for reducing zero-second delay ripple of a coherent measurement device according to the present invention.

Detailed Description

See fig. 1. According to the invention, in the circuit design of the coherent measurement equipment, a low-frequency reference clock of a signal processing circuit is promoted to a high-frequency clock through a phase-locked loop circuit, then the high-frequency clock signal is sent to a digital-to-analog converter (DAC), the DAC sends the high-frequency reference clock to a Field Programmable Gate Array (FPGA), the high-frequency clock signal passes through a digital clock management module (DCM) built in the FPGA, working clocks of an analog-to-digital converter (ADC) and the digital-to-analog converter (DAC) are generated in the DCM, and the working clock phases of the ADC; the FPGA internal logic processing circuit takes an ADC working clock as a system clock, controls zero-second delay fluctuation generated by ADC sampling time blurring within a high-frequency clock wavelength, and outputs forwarding data generated after processing through a digital-to-analog converter (DAC).

The FPGA digital processing circuit system clock and the ADC sampling reference clock are high-frequency clocks. The ADC sampling instant ambiguity is set to 1 high frequency clock wavelength.

The digital clock management module DCM can be composed of four parts, namely a bottom layer DLL module, a digital frequency synthesizer DFS, a digital phase shifter DPS and a digital spectrum expander DSS, wherein the DLL module is composed of a delay line and control logic, the delay line generates a delay to a clock input end CLKIN, and a clock distribution network line distributes the clock to each register and a clock feedback end CLKB in the device; the control logic samples the input clock when the feedback clock arrives to adjust the deviation between the input clock and the feedback clock so as to realize zero delay of input and output, the control logic adjusts the delay line parameters after comparing the deviation of the input clock and the feedback clock, the delay is inserted continuously after the input clock until the rising edges of the input clock and the feedback clock are synchronous, the locking loop enters a locking state, and the input clock and the feedback clock keep synchronous as long as the input clock does not change. The DLL provides zero propagation delay, low clock skew, and advanced clock domain control, among other things.

While the foregoing has described preferred embodiments of the present invention, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.