阅读说明：本技术 一种s模式询问信号检测方法、存储介质及检测设备 (S-mode interrogation signal detection method, storage medium and detection device ) 是由 赵峙岳 李洪鑫 洪成 刘斌 于 2019-09-23 设计创作，主要内容包括：本发明公开了一种S模式询问信号检测方法、存储介质及检测设备,所述检测方法包括：S1、接收中频信号并进行下变频,生成I、Q两路信号；S2、分别对I、Q信号进行滤波处理；S3、将滤波后的I、Q信号分别送入移位寄存器缓存；S4、将移位寄存器中缓存的I、Q信号相邻的前后码元进行相关累积求和处理；S5、将I、Q信号的相关累积求和处理的结果合成相位反转信号；S6、根据相位反转信号,搜索P1、P2脉冲；S7、通过检测P6脉冲进行位同步；S8、通过相关累积求和结果处理的值进行判决,并根据判决结果输出码元信息。本发明通过前后码元相关累积求和生成相位反转信号,既实现S模式ASK信号的检测,又实现DPSK同步导向点的搜索和码元的解码。(The invention discloses a detection method, a storage medium and a detection device for an S-mode inquiry signal, wherein the detection method comprises the following steps: s1, receiving the intermediate frequency signals and carrying out down-conversion to generate I, Q two paths of signals; s2, respectively filtering the I, Q signals; s3, respectively sending the filtered I, Q signals to a shift register for buffering; s4, carrying out correlation accumulation summation processing on adjacent front and back code elements of I, Q signals buffered in the shift register; s5, synthesizing the result of the correlation accumulation summation processing of the I, Q signals into a phase reversal signal; s6, searching for P1 and P2 pulses according to the phase reversal signal; s7, carrying out bit synchronization by detecting the P6 pulse; s8, making a decision by correlating the values processed by accumulating the summation results, and outputting symbol information according to the decision result. The invention generates the phase reversal signal through the correlation accumulation summation of the front code element and the rear code element, thereby realizing the detection of the ASK signal in the S mode and the search of the DPSK synchronous guide point and the decoding of the code element.)

1. A method of S-mode interrogation signal detection comprising the steps of:

s1, receiving the intermediate frequency signals and carrying out down-conversion to generate I, Q two paths of signals;

s2, respectively filtering the I, Q signals;

s3, respectively sending the filtered I, Q signals to a shift register for buffering;

s4, carrying out correlation accumulation summation processing on adjacent front and back code elements of I, Q signals buffered in the shift register;

s5, synthesizing the result of the correlation accumulation summation processing of the I, Q signals into a phase reversal signal;

s6, according to the phase reversal signal, the preliminary judgment of the S mode inquiry signal is realized by searching pulses P1 and P2; the P1 and P2 pulses are constant-amplitude leading pulses;

s7, after searching the P1 and P2 pulses, carrying out bit synchronization by detecting the P6 pulse to realize reconfirmation of the S-mode inquiry signal;

and S8, judging through the value of the result of the correlation accumulation summation processing, and outputting code element information according to the judgment result, thereby realizing the decoding of the S-mode inquiry signal information.

2. The method of claim 1, wherein the step S1 is a method comprising: if the intermediate frequency signal is

wherein m (t) is a DPSK baseband signal; am is the amplitude of the intermediate frequency signal;

3. The method of claim 2, wherein the step S2 is a method comprising: i, Q signals are respectively subjected to low-pass filtering processing; the filtered I, Q signals are:

4. the S-mode interrogation signal detection method of claim 3, characterized in that the size of the shift register is 2 DPSK symbol width.

5. The S-mode interrogation signal detection method according to claim 4, characterized in that the result of the correlation accumulation and sum processing in said step S4 is expressed by the following expression:

correlation accumulation of I signals_sumComprises the following steps:

correlation accumulation of Q signals_sumComprises the following steps:

wherein m is₁(i) Representing a pre-symbol value; m is₂(i) Representing a post-symbol value; n is the number of sampling points of one code element, and N is 0.25f_s，f_sIs the AD sampling frequency.

6. The S-mode interrogation signal detection method of claim 5, characterized in that the result of the correlation accumulation summation process of the I, Q signal in said step S5 is synthesized into an expression of a phase reversal signal as follows:

7. the method of claim 6, wherein the step S8 is a method comprising: when the decision point is less than zero, it indicates that phase reversal exists, and the demodulated value is 1; when the decision point is greater than zero, it indicates that there is no phase inversion, and the demodulated value is 0, thereby outputting symbol information and realizing decoding of S-mode interrogation signal information.

8. A computer-readable storage medium, having stored thereon a computer program; the computer program is executed by a processor to implement the method of any one of claims 1-7.

9. An S-mode interrogation signal detection apparatus, comprising:

a memory;

a processor; and

a computer program;

wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of any one of claims 1-7.

Technical Field

The invention relates to the technical field of secondary radar and signal processing, in particular to a method, a storage medium and a device for detecting an S-mode inquiry signal.

Background

The number of airplanes supported by the secondary radar A/C mode is limited, the problems of mutual interference, serious multipath influence and the like are easily exposed when the number of airplanes is increased to a certain degree, the secondary radar A/C mode is gradually replaced by an advanced secondary radar S mode protocol, and the secondary radar A/C mode protocol is accepted by the international civil aviation organization and serves as an industrial standard of a secondary monitoring radar. The S mode adopts ASK and DPSK mixed modulation mode, wherein DPSK completes binary coding through 180 degrees of phase reversal, and the currently common DPSK demodulation mode comprises the following steps: orthogonal demodulation, differential demodulation, demodulation based on DFT, DPSK demodulation based on cross-spectral analysis and the like, wherein differential decoding is simpler but has poorer performance, and other algorithms involve complex work such as carrier recovery, timing extraction and the like, and have advantages in performance.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: in view of the above-mentioned existing problems, an S-mode interrogation signal detection method, a storage medium, and a detection apparatus are provided, which generate a phase reversal signal by accumulation and summation of correlation between preceding and following symbols, and implement both detection of an S-mode ASK signal and search of a DPSK synchronization guide point and decoding of a symbol.

The technical scheme adopted by the invention is as follows:

the invention provides a method for detecting an S-mode interrogation signal, which comprises the following steps:

s1, receiving the intermediate frequency signals and carrying out down-conversion to generate I, Q two paths of signals;

s2, respectively filtering the I, Q signals;

s3, respectively sending the filtered I, Q signals to a shift register for buffering;

s4, carrying out correlation accumulation summation processing on adjacent front and back code elements of I, Q signals buffered in the shift register;

s5, synthesizing the result of the correlation accumulation summation processing of the I, Q signals into a phase reversal signal;

s6, searching pulses P1 and P2 according to the phase reversal signal, and realizing the preliminary judgment of the S mode inquiry signal; the P1 and P2 pulses are constant-amplitude leading pulses;

s7, after searching the P1 and P2 pulses, carrying out bit synchronization by detecting the P6 pulse to realize reconfirmation of the S-mode inquiry signal;

and S8, judging through the value of the result of the correlation accumulation summation processing, and outputting code element information according to the judgment result, thereby realizing the decoding of the S-mode inquiry signal information.

Further, the method of step S1 is:

if the intermediate frequency signal is

The I, Q signals after down-converting the if signal are:

wherein m (t) is a DPSK baseband signal; am is the amplitude of the intermediate frequency signal;

is a carrier phase out-of-sync phase difference; Δ f is the carrier frequency offset.

Further, the method of step S2 is: i, Q signals are respectively subjected to low-pass filtering processing; the filtered I, Q signals are:

further, the size of the shift register is 2 times the DPSK symbol width.

Further, the result of the correlation accumulation and summation process in the step S4 is expressed by the following expression:

correlation accumulation of I signals_sumComprises the following steps:

correlation accumulation of Q signals_sumComprises the following steps:

wherein m is₁(i) Representing a pre-symbol value; m is₂(i) Representing a post-symbol value; n is the number of sampling points of one code element, and N is 0.25f_s，f_sIs the AD sampling frequency.

Further, the expression of synthesizing the result of the correlation accumulation sum processing of the I, Q signal into a phase reversal signal in the step S5 is as follows:

further, the method of step S8 is: when the decision point is less than zero, it indicates that phase reversal exists, and the demodulated value is 1; when the decision point is greater than zero, it indicates that there is no phase inversion, and the demodulated value is 0, thereby outputting symbol information and realizing decoding of S-mode interrogation signal information.

The present invention also provides a computer-readable storage medium having stored thereon a computer program; which is executed by a processor to implement the above-described method.

The present invention also provides an S-mode interrogation signal detection apparatus, comprising:

a memory;

a processor; and

a computer program;

wherein the computer program is stored in the memory and configured to be executed by the processor to implement the above-described method.

In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:

1. the invention generates the phase reversal signal through the correlation accumulation summation of the front code element and the rear code element, thereby realizing the detection of the ASK signal in the S mode and the search of the DPSK synchronous guide point and the decoding of the code element.

2. The invention is insensitive to carrier phase asynchronism and time domain I, Q signal unbalance, does not need digital correction to I, Q amplitude, can resist certain carrier frequency offset, and has sensitivity superior to-90 dBm and obviously higher than the design requirement of receiver sensitivity of-85 dBm.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a waveform of an S-mode interrogation signal.

FIG. 2 is a block flow diagram of the S-mode interrogation signal detection method of the present invention.

FIG. 3 is a diagram of a shift register according to the present invention.

Fig. 4 is a waveform diagram of the implementation process of the correlated inversion signal of the present invention.

Fig. 5 is an S-mode interrogation phase-reversed signal to which the present invention is applied.

Fig. 6 is a diagram illustrating a pre-symbol and post-symbol correlation cumulative summation waveform according to the present invention.

Fig. 7 shows the S-mode interrogation signal detection probability using the present invention.

Detailed Description

The features and properties of the present invention are described in further detail below with reference to examples.

FIG. 1 is an S-mode interrogation signal waveform; FIG. 2 is a block flow diagram of the S-mode interrogation signal detection method of the present invention. The S-mode interrogation signal detection method comprises the following steps:

s1, receiving the intermediate frequency signals and carrying out down-conversion to generate I, Q two paths of signals:

if the intermediate frequency signal isThe I, Q signals after down-converting the if signal are:

wherein m (t) is a DPSK baseband signal; am is the amplitude of the intermediate frequency signal;

is a carrier phase out-of-sync phase difference; Δ f is the carrier frequency offset.

S2, respectively filtering the I, Q signals:

phase difference due to carrier phase asynchronismAnd the existence of carrier frequency deviation delta f, which can make the I-path signal amplitude

And Q-path signal amplitude

The amplitudes of the signals are inconsistent, so that the amplitudes of the I, Q signals are unbalanced, and the embodiment respectively performs low-pass filtering processing on the I, Q two paths of signals; the filtered I, Q signals are:

s3, mixingThe filtered I, Q signals are respectively sent to a shift register for buffering; preferably, as shown in FIG. 3, the size of the shift register is 2 DPSK symbol widths, i.e., 0.5f_sThat is, let the AD sampling frequency be f_s80MHz, the size of the shift register is 40.

S4, carrying out correlation accumulation summation processing on adjacent front and back code elements of I, Q signals buffered in the shift register:

the correlation accumulation and summation processing is to multiply and add the front and rear symbols, and specifically, the result of the correlation accumulation and summation processing is expressed by the following expression:

correlation accumulation of I signals_sumComprises the following steps:

correlation accumulation of Q signals_sumComprises the following steps:

wherein m is₁(i) Representing a pre-symbol value; m is₂(i) Representing a post-symbol value; n is the number of sampling points of one code element, and N is 0.25f_s＝20，f_sIs the AD sampling frequency.

S5, synthesizing the result of the correlation accumulation summation process of I, Q signals into a phase reversal signal:

the phase inversion signal implementation shown in fig. 4 is expressed as follows:

as can be seen from the above formula, the phase inversion signal is out of phase with the carrier phase

Independent of carrier frequency deviation delta f, only with the junction of the correlation accumulation summation processing of preceding and following symbolsThe correlation results show that the problems of carrier non-synchronization and frequency offset can be well solved through the process.

S6, searching pulses P1 and P2 according to the phase reversal signal, and realizing the preliminary judgment of the S mode inquiry signal; wherein the pulses P1 and P2 are constant-amplitude leading pulses.

The P1 and P2 pulses have fixed pulse width and pulse interval, in the embodiment, as shown in fig. 1, the pulse width of the P1 and P2 pulses is 0.8us, the pulse interval is 2us, and the P1 and P2 pulses can be searched by searching the pulse width and the pulse interval, so as to realize the preliminary judgment of the S-mode interrogation signal;

and S7, after the P1 and P2 pulses are searched, the bit synchronization is carried out by detecting the P6 pulse, and the S mode inquiry signal is confirmed again.

In the present embodiment, as shown in fig. 1, 1.25us before the P6 pulse is an ASK modulated constant amplitude pulse signal, which has a constant amplitude 180 ° phase inversion (synchronous phase inversion) at 1.25us, and is used to synchronize the clock signal for transponder data demodulation, thereby realizing a bit synchronization function. Therefore, the S-mode interrogation signal can be reconfirmed by detecting the pulse width of 1.25us of the P6 pulse with the same amplitude, and then searching for the inversion point 1.25us later (synchronous phase inversion point) for bit synchronization. As shown in fig. 5, in the correlation inversion signal, the signal near the inversion point assumes a "V" shape, and the inversion point can be searched by the area minimum. That is, in a region of the signal near the inversion point, the position of the searched minimum value is the inversion point.

And S8, judging through the value of the correlation accumulation summation result, and outputting code element information according to the judgment result, thereby realizing the decoding of the S-mode inquiry signal information.

As shown in fig. 6, according to the expression of the correlation inversion signal, when the phase inversion occurs in the preceding and following symbols, the minimum value is output; and when the phase inversion does not occur in the front and rear code elements, outputting the maximum value. Therefore, a method of making a decision by correlating values of the cumulative sum result and outputting symbol information according to the decision result is: when the decision point is less than zero, it indicates that phase reversal exists, and the demodulated value is 1; when the decision point is greater than zero, it indicates that there is no phase inversion, and the demodulated value is 0, thereby outputting symbol information and realizing decoding of S-mode interrogation signal information.

Through system simulation, the S-mode detection probability realized by applying the S-mode interrogation signal detection method of the present invention is shown in fig. 7, and it can be seen from the figure that the method of the present invention has high system sensitivity.

In summary, the invention generates the phase reversal signal by the correlation accumulation summation of the front and rear code elements, realizes the detection of the ASK signal in the S mode, realizes the search of the DPSK synchronization inversion point and the decoding of the code elements, and can normally work under the conditions of asynchronous carrier phases and different frequency offsets, thereby avoiding the operation process of carrier recovery, having better carrier frequency offset resistance, and the sensitivity is better than-90 dBm and is obviously higher than the design requirement of the receiver sensitivity of-85 dBm.

Furthermore, an embodiment of the present invention also provides a computer-readable storage medium having a computer program stored thereon; the computer program is executed by a processor to implement the method of any one of claims 1-7.

Further, an embodiment of the present invention also provides an S-mode interrogation signal detection apparatus including:

a memory;

a processor; and

a computer program;

wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of any one of claims 1-7.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.