阅读说明：本技术 一种脉冲相参应答装置 (Pulse coherent answering device ) 是由 吴红梅 李晓龙 杨振 朱博弢 刘庆 陈勇前 周荣 于 2019-09-25 设计创作，主要内容包括：本申请提供了一种脉冲相参应答装置,主要由微波变频组合、中频滤波放大组合、数字处理组合和整机电源模块构成,微波变频组合主要包括环形器、限幅器、预选滤波器、低噪放、下变频器、锁相源、参考晶振、上变频器、射频滤波器和固态功放模块,中频滤波放大组合主要包括中频滤波器、前中放、功分器、检波器、选频滤波器和后中放,数字处理组合主要包括双路高速A/D电路、时钟驱动器、高速D/A电路、FPGA信号处理电路、RS422接口电路、EEPROM和遥测参数产生电路。本申请可以通过RS422接口电路和EEPROM,在产品软硬件平台固化后,快速、方便地满足不同场合转发脉冲延迟时间、整机封闭时间等参数的调整需求。(The application provides a pulse coherent response device, which mainly comprises a microwave frequency conversion combination, an intermediate frequency filtering amplification combination, a digital processing combination and a complete machine power module, wherein the microwave frequency conversion combination mainly comprises a circulator, an amplitude limiter, a preselection filter, a low-noise amplifier, a down converter, a phase-locked source, a reference crystal oscillator, an up converter, a radio frequency filter and a solid-state power amplifier module, the intermediate frequency filtering amplification combination mainly comprises an intermediate frequency filter, a front middle amplifier, a power divider, a detector, a frequency selection filter and a rear middle amplifier, and the digital processing combination mainly comprises a double-circuit high-speed A/D circuit, a clock driver, a high-speed D/A circuit, an FPGA signal processing circuit, an RS422 interface circuit, an EEPROM and a telemetering parameter generating circuit. The application can quickly and conveniently meet the adjustment requirements of parameters such as the forwarding pulse delay time of different occasions, the closed time of the whole machine and the like after the software and hardware platform of the product is solidified through the RS422 interface circuit and the EEPROM.)

1. A pulsed coherent response device, comprising:

the microwave frequency conversion combination comprises a circulator, an amplitude limiter, a preselection filter, a low-noise amplifier, a down converter, a phase-locked source, a reference crystal oscillator, an up converter, a radio frequency filter and a solid-state power amplifier module, wherein the microwave frequency conversion combination is used for passing a received target radio frequency pulse signal through the circulator, sequentially limiting the amplitude limiter by the amplitude limiter, filtering by the preselection filter, amplifying by the low-noise amplifier and transmitting to the intermediate frequency filtering amplifier combination after frequency conversion of the down converter, the microwave frequency conversion combination is also used for receiving the target intermediate frequency pulse signal after the intermediate frequency filtering amplifier combination is processed, the processed intermediate frequency pulse signal is sequentially processed by the frequency conversion of the up converter, the radio frequency filter is processed and the solid-state power amplifier module is processed, and the circulator is used for sending the processed target radio frequency pulse signal to a radio frequency transceiving port, the phase-locked source provides local oscillator signals for the up-converter and the down-converter, and the reference crystal oscillator is used for providing a clock reference source for the phase-locked source;

the intermediate frequency filtering and amplifying combination comprises an intermediate frequency filter, a front intermediate amplifier, a power divider, a detector, a frequency selection filter and a rear intermediate amplifier, wherein a target pulse signal sent by the microwave frequency conversion combination is filtered by the intermediate frequency filter, is linearly amplified by the front intermediate amplifier and is divided into two paths of signals by the power divider, the power divider is used for transmitting a first path of signals in the two paths of signals to a high-speed double-path A/D circuit in a digital processing combination, the detector is used for detecting a second path of signals in the two paths of signals and sending a detected detection signal to the high-speed double-path A/D circuit, the intermediate frequency filtering and amplifying combination is also used for receiving the target intermediate frequency pulse signal processed by the digital processing combination, and the frequency selection filter is used for performing frequency selection filtering on the received target intermediate frequency pulse signal, the rear intermediate amplifier is used for performing power amplification on the target intermediate frequency pulse signal subjected to frequency selection and filtering and sending the amplified target intermediate frequency pulse signal to the microwave frequency conversion combination;

the digital processing combination comprises the two-way high-speed A/D circuit, a clock distributor, a high-speed D/A circuit, an FPGA signal processing circuit, an RS422 interface circuit, an EEPROM (electrically erasable programmable read-only memory) and a telemetering parameter generating circuit, wherein the FPGA signal processing circuit is used for judging whether the width of a received detection signal is qualified or not, reading configuration parameters stored in the EEPROM, generating a time sequence control signal according to a judgment result and the configuration parameters, controlling the target pulse signal to generate time delay according to the time sequence control signal, and sending the delayed target pulse signal to the high-speed D/A circuit.

2. The apparatus of claim 1, wherein the configuration parameters stored in the EEPROM comprise: the FPGA signal processing circuit is also used for adjusting the pulse forwarding delay time and the complete machine sealing time stored by the EEPROM by receiving an instruction of the RS422 interface.

3. The apparatus of claim 2, wherein the pre-mid amplifier is a linear amplifier.

4. The apparatus according to any one of claims 1 to 3, wherein the FPGA signal processing circuit is further configured to perform amplitude-consistency adjustment on the pulses of the target intermediate frequency pulse signal according to the amplitude of the detection signal of the detector.

5. The apparatus of claim 2, wherein the FPGA signal processing circuit is configured to stop receiving new rf pulse signals during the whole machine close time period from the start of receiving the target rf pulse signal.

6. The apparatus of claim 5, wherein the amplitude limiter of the microwave frequency conversion combination is configured to perform pulse signal amplitude limitation on the received RF pulse signal.

7. The apparatus of claim 1, wherein the phase-locked source in the microwave frequency conversion combination is configured to provide local oscillator signals for the up-converter and the down-converter, the reference crystal is configured to provide a reference source for the phase-locked source, the reference crystal is also configured to provide a reference clock for the clock distributor, and the clock distributor is configured to provide a synchronous reference clock for the two-way high-speed a/D circuit, the FPGA signal processing circuit, and the high-speed D/a circuit, respectively.

8. The device of any one of claims 1 to 3, wherein the low frequency power supply interface of the pulse coherent response device, the interface of the telemetry parameter generation circuit, and the RS422 circuit interface share the same low frequency connector.

Technical Field

The application relates to the technical field of aerospace measurement and control communication equipment, in particular to a pulse coherent response device with adjustable time delay.

Background

The pulse coherent response device is mainly used for an external measurement safety subsystem or a measurement subsystem of a carrier rocket, is used for cooperating with a ground pulse radar, increasing the system action distance and improving the system measurement precision, completing rocket tracking measurement, and providing missile path data for post analysis and processing for a flight test.

According to the characteristics of the existing ground station pulse radar and the technical requirements of long-range series rockets and the like, the pulse delay time of the pulse coherent response device is generally 6.4 mu s or 12.8 mu s, the closing time of the whole machine is generally 20 mu s-29 mu s, and other technical indexes are basically consistent. With the development of digital signal processing technology and considering the modularization and generalization design of products, the software and hardware platforms of the pulse coherent response device need to be unified so as to improve the productivity, consistency and reliability of the products.

A missile-borne coherent multi-station trigger working pulse responder (patent number: CN201210496900.0, inventor: Wu national English, yellow Bingarmy, Yan forest repair, Zhang Xin, Wubi spring) provides a missile-borne coherent multi-station trigger working pulse responder, which comprises a microwave unit module and a terminal control module; a co-channel interference processing system of an impulse coherent transponder is proposed in the patent No. CN201611057684.4 (inventor: Chenxia Huang Wei normal level). The software and hardware implementation modes of the two patents are similar, the same frequency and common local oscillator for receiving and transmitting is adopted, the time-sharing isolation for receiving and transmitting is realized through a front-end microwave switch of a receiving channel, the dynamic range of a received signal is realized by a receiving intermediate frequency amplifier, and a Field Programmable Gate Array (FPGA) generates a control time sequence signal and stores and delays the intermediate frequency signal for forwarding. The isolation of the receiving channel to the transmitting signal needs to be controlled by a microwave switch, the isolation degree of the switch has certain requirements, and a signal processing part is needed to generate a switch control signal. Although the FPGA signal processing part can realize software adjustment of parameters such as the delay time of the forwarded pulse, the closing time and the like, the software version needs to be updated, re-solidified, tested and the like according to actual requirements, and particularly when the FPGA signal processing part is applied to the field of bullets (arrows), the workload is large, the technical state is multiple and the parameter change is not flexible enough under the software engineering management requirements.

In view of the above situation, there is a need for a pulse coherent responder capable of flexibly delaying a pulse.

Disclosure of Invention

The application provides a pulse coherent response device, which can flexibly change parameters such as pulse delay time, complete machine closing time and the like.

In one aspect, there is provided a pulse coherent response apparatus, the apparatus comprising:

the microwave frequency conversion combination comprises a circulator, an amplitude limiter, a preselection filter, a low-noise amplifier, a down converter, a phase-locked source, a reference crystal oscillator, an up converter, a radio frequency filter and a solid-state power amplifier module, wherein the microwave frequency conversion combination is used for passing a received target radio frequency pulse signal through the circulator, sequentially limiting the amplitude limiter by the amplitude limiter, filtering by the preselection filter, amplifying by the low-noise amplifier and transmitting to the intermediate frequency filtering amplifier combination after frequency conversion of the down converter, the microwave frequency conversion combination is also used for receiving the target intermediate frequency pulse signal after the intermediate frequency filtering amplifier combination is processed, the processed intermediate frequency pulse signal is sequentially processed by the frequency conversion of the up converter, the radio frequency filter is processed and the solid-state power amplifier module is processed in an amplifying way, and the circulator is used for sending the processed target radio frequency pulse signal to a radio frequency transceiving port, the phase-locked source provides local oscillator signals for the up converter and the down converter, and the reference crystal oscillator is used for providing a clock reference source for the phase-locked source;

the intermediate frequency filtering and amplifying combination comprises an intermediate frequency filter, a front intermediate amplifier, a power divider, a detector, a frequency selection filter and a rear intermediate amplifier, wherein a target pulse signal sent by the microwave frequency conversion combination is filtered by the intermediate frequency filter, is linearly amplified by the front intermediate amplifier and is divided into two paths of signals by the power divider, the power divider is used for transmitting a first path of signals in the two paths of signals to a high-speed double-path A/D circuit in a digital processing combination, the detector is used for detecting a second path of signals in the two paths of signals and sending a detected detection signal to the high-speed double-path A/D circuit, the intermediate frequency filtering and amplifying combination is also used for receiving the target intermediate frequency pulse signal processed by the digital processing combination, and the frequency selection filter is used for performing frequency selection filtering on the received target intermediate frequency pulse signal, the rear intermediate amplifier is used for performing power amplification on the target intermediate frequency pulse signal subjected to frequency selection and filtering and sending the amplified target intermediate frequency pulse signal to the microwave frequency conversion combination;

the digital processing combination comprises the two-way high-speed A/D circuit, a clock distributor, a high-speed D/A circuit, an FPGA signal processing circuit, an RS422 interface circuit, a charged Erasable Programmable read only memory (EEPROM) and a telemetering parameter generating circuit, wherein the FPGA signal processing circuit is used for judging whether the received detection signal width is qualified or not and reading the configuration parameters stored in the EEPROM, generating a time sequence control signal according to the judgment result and the configuration parameters, controlling the target pulse signal to generate time delay according to the time sequence control signal, and sending the delayed target pulse signal to the high-speed D/A circuit.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the configuration parameters stored in the EEPROM include: the FPGA signal processing circuit is also used for adjusting the pulse forwarding delay time and the complete machine closing time stored by the EEPROM by receiving an instruction of the RS422 interface.

With reference to the first aspect and the foregoing implementation manner, in a second possible implementation manner of the first aspect, the front-middle amplifier is a linear amplifier.

With reference to the first aspect and the foregoing implementation manner, in a third possible implementation manner of the first aspect, the FPGA signal processing circuit is further configured to perform amplitude consistency adjustment on pulses of the target intermediate frequency pulse signal according to the amplitude of the detection signal of the detector.

With reference to the first aspect and the foregoing implementation manner, in a fourth possible implementation manner of the first aspect, the FPGA signal processing circuit is configured to not receive a new radio frequency pulse signal any more in the complete machine closed time period from the receiving of the target radio frequency pulse signal.

With reference to the first aspect and the foregoing implementation manner, in a fifth possible implementation manner of the first aspect, the limiter in the microwave frequency conversion combination is used to limit the pulse signal.

With reference to the first aspect and the foregoing implementation manner, in a sixth possible implementation manner of the first aspect, the phase-locked source in the microwave frequency conversion combination is configured to provide local oscillator signals for the upconverter and the downconverter, the reference crystal oscillator is configured to provide a reference source for the phase-locked source, the reference crystal oscillator is also configured to provide a reference source for the clock distributor, and the clock distributor is configured to respectively reference clocks for the two-way high-speed a/D circuit, the FPGA signal processing circuit, and the high-speed D/a circuit.

With reference to the first aspect and the foregoing implementation manner, in a seventh possible implementation manner of the first aspect, the low-frequency power supply interface of the pulse coherent response device, the interface of the telemetry parameter generating circuit, and the RS422 circuit interface share the same low-frequency connector.

Therefore, according to the requirement of a universal design, the invention discloses a pulse coherent response device with adjustable time delay, which can store parameters needing to be adjusted, such as pulse forwarding delay time, complete machine sealing time and the like, as configuration parameter quantities in an EEPROM (electrically erasable programmable read-only memory) on the basis of the solidification and unification of a software and hardware platform, and communicate with an FPGA (field programmable gate array) signal processing circuit through an RS422 interface to change and manage the configuration parameters, thereby realizing the rapid and convenient adjustment of the parameters, such as the delay time, the sealing time and the like.

Compared with the traditional pulse coherent responder device, the pulse coherent responder device with adjustable time delay provided by the invention realizes the rapid and convenient adjustment of parameters such as pulse forwarding time delay, complete machine closing time and the like through the RS422 interface circuit and the EEPROM. The invention has the following outstanding advantages:

1. parameters to be adjusted, such as pulse forwarding delay time, complete machine sealing time and the like, are stored in an EEPROM as configuration parameter quantities, and the parameters are communicated with an FPGA signal processing circuit through an RS422 interface to change the configuration parameters stored in the EEPROM, so that the parameters, such as the pulse forwarding delay time, the complete machine sealing time and the like, can be quickly and conveniently adjusted; the delay time of the forwarded pulse, the closing time of the whole machine and the like are used as configuration parameters to carry out engineering quality management without changing and re-solidifying software. In addition, the RS422 communication interface can realize real-time adjustment of parameters such as the delay time of the forwarding pulse, the closed time of the whole machine and the like, and the method has great flexibility when being used for other fields such as a radar flight correction system and the like.

2. The front-middle amplifier is a linear amplifier, a large dynamic range is received through a double-path high-speed A/D circuit, amplitude consistency adjustment of the forwarding pulse signals is performed through an FPGA signal processing circuit, and compared with amplitude limiting amplification of a traditional large gain middle-frequency amplifier, the signal-to-noise ratio degradation degree of the forwarding pulse signals when large signals are input is reduced.

3. The limitation on transmitting high-power signals is realized by using an amplitude limiter in the microwave frequency conversion combination, the damage of the high-power transmitting signals to a receiving channel is avoided, and compared with a traditional microwave switch, a control signal of an FPGA signal processing circuit is not needed; for the signal of the transmitted pulse leaking to the receiving channel, the FPGA signal processing circuit ignores the A/D sampling signal within a fixed time t after the qualified pulse, the receiving and transmitting are thoroughly isolated through software, the same frequency interference is avoided, and the isolation degree does not depend on the performance of a microwave switch.

4. In the microwave frequency conversion combination, a phase-locked source is used as a local oscillation signal of an up-down converter, and a reference clock of the phase-locked source is also used as a reference clock of the digital processing combination, so that all local clocks are in the same source; a clock distributor is used in the digital processing combination to realize clock synchronization of a double-path high-speed A/D circuit, an FPGA signal processing circuit and a high-speed D/A circuit; the homology and synchronization of the clocks have certain optimization effect on the signal processing quality.

Drawings

Fig. 1 is a schematic block diagram of a pulse coherent response device according to the present application.

Detailed Description

The technical solution in the present application will be described below with reference to the accompanying drawings.

With reference to fig. 1, a delay adjustable pulse coherent response device is shown, which mainly comprises a microwave frequency conversion combination, an intermediate frequency filtering amplification combination, a digital processing combination and a complete machine power module, wherein the microwave frequency conversion combination mainly comprises a circulator, an amplitude limiter, a preselection filter, a low-noise amplifier, a down converter, a phase-locked source, a reference crystal oscillator, an up converter, a radio frequency filter and a solid-state power amplifier module, the intermediate frequency filtering amplification combination mainly comprises an intermediate frequency filter, a front intermediate amplifier, a power divider, a detector, a frequency selection filter and a rear intermediate amplifier, and the digital processing combination mainly comprises a two-way high-speed a/D circuit, a clock driver, a high-speed D/a circuit, an FPGA signal processing circuit, an RS422 interface circuit, an EEPROM and a telemetry parameter generating circuit.

The signal flow is as follows: the radio frequency transceiving port receives a radio frequency pulse signal transmitted by a ground radar, the radio frequency pulse signal passes through a circulator in a microwave frequency conversion combination and then is sequentially subjected to amplitude limiting by an amplitude limiter, filtering by a preselection filter, low-noise amplification and frequency conversion by a down converter and then is transmitted to an intermediate frequency filtering amplification combination, the intermediate frequency filter in the intermediate frequency filtering amplification combination is used for filtering and then is subjected to linear amplification by a front intermediate amplifier, the intermediate frequency filter is divided into two paths after amplification, one path of the signal is transmitted to a high-speed double-path A/D circuit, the other path of the signal is detected by a detector to give a high-speed double-path A/D circuit, and then the received signal is processed. The FPGA signal processing circuit generates a corresponding time sequence control signal and generates an intermediate frequency signal after corresponding time delay and amplitude normalization processing to be sent to a high-speed D/A circuit for digital-to-analog conversion, the converted forwarding analog intermediate frequency signal is subjected to frequency selection filtering and then intermediate amplification by a frequency selection filter in an intermediate frequency filtering and amplifying combination, then is sent to a microwave frequency conversion combination, is subjected to up-conversion by an up-converter, filtering by a radio frequency filter and power amplification by a solid-state power amplification module, and finally is transmitted by a radio frequency receiving and transmitting port through a circulator. The low-frequency power supply and remote measurement power supply interface supplies power to the whole machine, and the power is converted into power supply voltage required by each circuit module through the power module of the whole machine.

Optionally, as an embodiment of the present application, parameters to be adjusted, such as pulse forwarding delay time, complete machine sealing time, and the like, are stored in an EEPROM as configuration parameter quantities, and are communicated with an FPGA signal processing circuit through an RS422 interface to change the configuration parameters stored in the EEPROM, so as to implement fast and convenient adjustment of parameters, such as pulse forwarding delay time, complete machine sealing time, and the like; the delay time of the forwarded pulse, the closing time of the whole machine and the like are used as configuration parameters to carry out engineering quality management without changing and re-solidifying software.

Optionally, as an embodiment of the present application, the front-middle amplifier is a linear amplifier, and the requirement of receiving a large dynamic range is met by a two-way high-speed a/D circuit; the FPGA signal processing circuit not only stores and delays the intermediate frequency signal processing, but also needs to carry out amplitude consistency adjustment, thereby realizing the power consistency of the pulse forwarding signal in the dynamic range of the received signal, and the amplitude modulation basis is the detection signal amplitude of the detector.

Optionally, as an embodiment of the present application, the FPGA signal processing circuit needs to perform demodulation width discrimination processing on the received signal, determine the storage time of the intermediate frequency signal according to the delay requirement of the whole device based on the discrimination result, and generate a power-on control signal of the solid-state power amplifier module and a pulse width modulation signal required by the telemetry parameter generating circuit;

optionally, as an embodiment of the present application, after the FPGA signal processing circuit completes the processing and discrimination of the received signal, if the received signal is a qualified pulse, the signal sampled by the high-speed two-way a/D circuit is not identified again within the immediately fixed time t, and the identification processing is restarted after the time t to avoid the co-frequency transceiving interference, where the time t is determined by the overall enclosure time and is generally shorter than the overall enclosure time by one pulse width time.

Optionally, as an embodiment of the present application, the limiter in the microwave frequency conversion combination is used to limit the transmitted pulse signal, so that the low-noise amplifier and the down converter are not damaged when the high-power pulse signal is transmitted.

Optionally, as an embodiment of the present application, a phase-locked source in the microwave frequency conversion combination is used as local oscillator signals of the up-converter and the down-converter, and a reference clock thereof is also used as a reference clock of the digital processing combination, so that all local clocks are homologous; and a clock distributor is used in the digital processing combination to realize clock synchronization of the two-way high-speed A/D circuit, the FPGA signal processing circuit and the high-speed D/A circuit.

Optionally, as an embodiment of the present application, the low-frequency power supply interface, the stand-alone telemetry parameter interface, and the RS422 interface share one low-frequency connector, which facilitates the airtight design of the whole machine and reduces the number of low-frequency interfaces.

The above description is only a preferred embodiment of the present invention, and any modifications, replacements, improvements, etc. made within the spirit and principle of the present invention, for example, the RS422 interface circuit may be adjusted to other serial communication circuits such as RS232, and the configuration parameters such as the forwarding pulse delay, the closing time of the whole machine, etc. may be changed into the pulse width fine-tuning parameter, the delay automatic switching period parameter, etc. according to the needs, all of which are included in the scope of the claimed invention.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a second device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.