阅读说明：本技术 优化过孔反焊盘走线的方法、电路板、设备和存储介质 (Method, circuit board, equipment and storage medium for optimizing via hole anti-pad routing ) 是由 荣世立 于 2021-06-11 设计创作，主要内容包括：本发明提出了优化过孔反焊盘走线的方法、电路板、设备和存储介质。该方法包括针对不同尺寸的过孔反焊盘,以第一距离的第一数值为初始值,第二数值为步长进行遍历,确定过孔阻抗最小时对应的第一距离；第一距离为过孔反焊盘内差分线耦合位置距离差分信号孔中间的直线距离。在对反焊盘区域内的走线方式进行优化的同时,对反焊盘区域内的信号孔进行背钻。基于该方法还提出了印刷电路板、印刷电路板的过孔反焊盘走线优化设备和存储介质。本发明在高速链路设计时需要关注过孔处的阻抗特性,在优化过孔阻抗时,除了通过改变反焊盘尺寸以外,还可以对反焊盘区域内的走线方式进行优化,进一步优化过孔阻抗,提高链路阻抗连续性,提高信号传输质量。(The invention provides a method, a circuit board, equipment and a storage medium for optimizing via hole anti-pad routing. The method comprises the steps of traversing by taking a first numerical value of a first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of a via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole. And back drilling the signal holes in the region of the reverse welding disc while optimizing the wiring mode in the region of the reverse welding disc. The method also provides the printed circuit board, the via hole anti-pad routing optimization equipment of the printed circuit board and the storage medium. The impedance characteristic of the through hole needs to be paid attention to when the high-speed link is designed, when the impedance of the through hole is optimized, the wiring mode in the area of the reverse pad can be optimized except that the size of the reverse pad is changed, the impedance of the through hole is further optimized, the continuity of the impedance of the link is improved, and the signal transmission quality is improved.)

1. The method for optimizing the routing of the via anti-pad is characterized by comprising the following steps of: traversing by taking a first numerical value of the first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of the via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole.

2. The method for optimizing via antipad routing of claim 1, wherein the first value is 0mil or a radius of the via antipad.

3. The method for optimizing via antipad routing according to claim 2, wherein when the first value is 0mil, the second value is any value greater than 0 and less than the via antipad radius; and when the first value is the radius of the via hole anti-pad, the second value is smaller than 0, and the absolute value is smaller than any value of the radius of the via hole anti-pad.

4. The method for optimizing via antipad routing of claim 1, wherein when the radius of the via antipad is less than the first threshold, the relationship between the first distance and the radius of the via antipad is: the first distance is 2 via anti-pad radius-10 mil.

5. The method for optimizing via antipad routing of claim 1, wherein when the radius of the via antipad is greater than the second threshold and less than the designed maximum radius of the via antipad, the relationship between the first distance and the radius of the via antipad is: the first distance is 75-2 the radius of the via antipad.

6. The method for optimizing via antipad routing according to any of claims 1 to 5, further comprising backdrilling a signal hole within a via antipad.

7. The method for optimizing via anti-pad routing according to claim 6, wherein the signal hole back-drilling depth is determined by:

calculating the thickness of the via stub according to the thickness of the signal routing and the printed circuit board;

and determining the back drilling depth of the signal hole according to the thickness of the via hole stub.

8. The printed circuit board is characterized in that the printed circuit board is processed by the method for optimizing via hole anti-pad routing according to any one of claims 1 to 7; the method for manufacturing the printed circuit board comprises the following steps: traversing by taking a first numerical value of the first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of the via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole.

9. The anti-pad of via hole of printed circuit board walks optimization device, its characterized in that includes:

a memory for storing a computer program;

a processor for implementing the method steps for optimizing via anti-pad routing according to any of claims 1 to 7 when executing said computer program.

10. Computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the method steps of optimizing via anti-pad routing according to any of claims 1 to 7.

Technical Field

The invention belongs to the technical field of printed circuit board design, and particularly relates to a method for optimizing via hole anti-pad routing, a circuit board, equipment and a storage medium.

Background

With the rapid development of microelectronic technology, the rising edge of signals is faster and faster, and the transmission line effect generated by high-speed circuits is more and more serious. For the mainstream high-speed circuit at present, a PCB engineer must adopt a high-speed PCB design technology based on a transmission line theory to ensure the normal operation of the circuit. The characteristic impedance design and control is the core and the foundation for solving the transmission line effect of the high-speed circuit, and is valued by more and more PCB engineers and manufacturers. To obtain a final high-precision characteristic impedance circuit board product, control needs to be performed from multiple aspects such as PCB design, processing, impedance testing, and the like. The necessity of high-precision characteristic impedance design is to make the same signal have the same impedance value on its transmission path, i.e., impedance matching. In high speed PCBs, when there is an impedance mismatch over the signal link, problems such as signal distortion, aggravation of electromagnetic radiation emissions, and reflections can arise. In conventional digital system designs, high speed interconnect phenomena are often negligible because they have a weak impact on the performance of the system. However, with the continuous development of computer technology, the phenomenon of high-speed interconnection is dominant among many factors determining the performance of the system, often resulting in some unpredictable problems, and greatly increasing the complexity of system design. Therefore, in the high-speed link design, each module is optimized as much as possible, the design feasibility and risk points are evaluated in advance by means of a simulation tool, the design is optimized according to the simulation result, the success rate of the system design is improved, and the research and development period is shortened. In the process of designing a high-speed signal link of a server system, the optimization design of the link impedance is particularly important, and if the continuity of the link impedance is poor, signal reflection and link loss are caused, so that the signal transmission quality is influenced, and even the design is failed. In the link design, the via is an important factor affecting the continuity of the link impedance, and the via additionally exhibits parasitic capacitance and parasitic inductance at a high frequency, which makes the via an impedance discontinuity point, so that it is important to perform impedance optimization at the via.

In the high-speed link design, aiming at the problem of impedance discontinuity at a via hole, the signal hole is often only optimally designed, the impedance characteristic at the via hole is changed by changing the size of an anti-bonding pad, and the capacitance between the via hole and a reference plane is different due to the different sizes of the anti-bonding pads, so that the impedance characteristic is optimized, and the impedance discontinuity is reduced. For higher rate signals such as PCIe Gen4, backdrilling of signal holes is often required, removing excess via hole walls, reducing via stubs and thereby improving link impedance consistency. Although the design method can change the impedance at the via hole and reduce the impedance discontinuity, the sizes of the required anti-bonding pads are different due to the fact that the lengths of the via holes and the lengths of the stubs are different, so that the board card manufacturing process is complex, and the cost is increased. On the other hand, for ultra-high speed vias with backdrilling, the design requirements may still be missed by solely anti-pad optimization, which makes the above approach limited.

Disclosure of Invention

In order to solve the technical problems, the invention provides a method, a circuit board, equipment and a storage medium for optimizing the routing of a via hole reverse pad.

In order to achieve the purpose, the invention adopts the following technical scheme:

the method for optimizing the routing of the via anti-pad comprises the following steps: traversing by taking a first numerical value of the first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of the via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole.

Further, the first value is 0mil or a radius of the via anti-pad.

Further, when the first value is 0mil, the second value is any value which is larger than 0 and smaller than the radius of the via hole anti-pad; and when the first value is the radius of the via hole anti-pad, the second value is smaller than 0, and the absolute value is smaller than any value of the radius of the via hole anti-pad.

Further, when the radius of the via anti-pad is smaller than the first threshold, the relationship between the first distance and the radius of the via anti-pad is: the first distance is 2 via anti-pad radius-10 mil.

Further, when the radius of the via anti-pad is greater than the second threshold and smaller than the designed maximum radius of the via anti-pad, the relationship between the first distance and the radius of the via anti-pad is as follows: the first distance is 75-2 the radius of the via antipad.

Further, the method also includes back-drilling the signal hole in the via anti-pad.

Further, the method for determining the back drilling depth of the signal hole comprises the following steps:

calculating the thickness of the via stub according to the thickness of the signal routing and the printed circuit board;

and determining the back drilling depth of the signal hole according to the thickness of the via hole stub.

The invention also provides a printed circuit board which is processed by adopting a method for optimizing the via hole reverse pad routing; the method for manufacturing the printed circuit board comprises the following steps: traversing by taking a first numerical value of the first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of the via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole.

The invention also provides a via hole anti-pad routing optimization device of the printed circuit board, which comprises:

a memory for storing a computer program;

and the processor is used for realizing the method steps of optimizing the routing of the via hole anti-pad when the computer program is executed.

The invention also provides a computer readable storage medium having a computer program stored thereon, which when executed by a processor implements method steps for optimizing via antipad routing.

The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:

the invention provides a method, a circuit board, equipment and a storage medium for optimizing via hole anti-pad routing. The method comprises the steps of traversing by taking a first numerical value of a first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of a via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole. According to the invention, aiming at different anti-bonding pad sizes, wiring design in different modes needs to be carried out in the anti-bonding pad area, and the two are combined to find out the optimal design. Generally, when the radius of the anti-pad is smaller than 23mil, the capacitance at the via is larger, the impedance is reduced more seriously, and the value D can be increased properly, which is suggested to be 2 × impedance-10 mil, that is, the differential line is delayed from coupling, and the impedance is raised properly. When the radius of the anti-bonding pad is larger than 25mil and smaller than 35mil (the radius of the anti-bonding pad is not larger than 35mil by conventional design), the capacitance at the through hole is reduced, the impedance rises, the differential line can be coupled as early as possible, and the proposal is 75-2 × anti, so that the overall impedance consistency of the link is improved. The invention needs to pay attention to the impedance characteristic of the through hole when designing the high-speed link, and can optimize the wiring mode in the area of the reverse pad except changing the size of the reverse pad when optimizing the impedance of the through hole, thereby further optimizing the impedance of the through hole, improving the impedance continuity of the link, reducing the signal reflection and effectively improving the signal transmission quality.

The invention can optimize the wiring mode in the region of the reverse welding disc, and back-drill the signal holes in the region of the reverse welding disc, thereby better optimizing the impedance of the via holes, improving the continuity of the impedance of the link and better improving the signal transmission quality.

Based on the method for optimizing the via hole reverse pad routing disclosed by the invention, the invention also provides the printed circuit board, the via hole reverse pad routing optimization equipment of the printed circuit board and the storage medium, and the method also has the function of the method for optimizing the via hole reverse pad routing, and is not described herein again.

Drawings

FIG. 1 is a schematic diagram of a via layout of a PCIe Gen4 link according to embodiment 1 of the present invention;

FIG. 2 is a three-dimensional diagram of a via design for a PCIe Gen4 link according to embodiment 1 of the present invention;

FIG. 3 is a schematic diagram of a PCIe Gen4 link back-drilled for signal holes according to embodiment 1 of the present invention;

FIG. 4 is a schematic diagram of a PCIe Gen4 via antipad design according to embodiment 1 of the present invention;

fig. 5 is a first layout diagram of routing in a via insulation area according to embodiment 1 of the present invention;

fig. 6 is a second layout diagram of routing in a via anti area according to embodiment 1 of the present invention;

FIG. 7 is a simulation diagram of a TDR waveform with a reverse pad radius of 15mil according to example 1 of the present invention;

FIG. 8 is a simulation diagram of a TDR waveform with a 20mil anti-pad radius according to example 1 of the present invention;

FIG. 9 is a simulation diagram of a TDR waveform with a reverse pad radius of 25mil according to example 1 of the present invention;

FIG. 10 is a simulation diagram of a TDR waveform with a reverse pad radius of 30mil according to example 1 of the present invention.

Detailed Description

In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.

Example 1

To further illustrate the design method of the present invention, a specific via is taken as an example for a detailed description, and fig. 1 shows a via design for a PCIe Gen4 link, wherein the signal vias complete a via radius of 4 mils and via pad radius of 10 mils. The signal routing on the via hole is from L1 layer to L5 layer. FIG. 2 shows a three-dimensional diagram of a via design for a PCIe Gen4 link. The target controlled impedance of the via is 85ohm 2 ohm.

Due to the fact that the signal speed is high, the via hole has 51mil via stub, and therefore the signal hole is back-drilled with a depth of 41mil, as shown in fig. 3, the back-drilling of the via hole is only performed for the signal hole. Fig. 4 shows the anti design of the via hole, and the radius of the anti is set as a variable anti, and the traversal is performed with 15 mils as an initial value and 5 mils as a step size, and the maximum is 30 mils.

The embodiment 1 of the invention optimizes the wiring method of the anti area. The method for optimizing the routing of the via anti-pad comprises the following steps: traversing by taking a first numerical value of the first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of the via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole.

The first value is 0mil or the radius of the via anti-pad. When the first value is 0mil, the second value is any value which is larger than 0 and smaller than the radius of the via hole anti-pad; when the first value is the radius of the via anti-pad, the second value is less than 0, and the absolute value is less than any value of the radius of the via anti-pad.

When the radius of the via anti-pad is smaller than the first threshold, the relationship between the first distance and the radius of the via anti-pad is as follows: the first distance is 2 via anti-pad radius-10 mil. When the radius of the via hole anti-pad is larger than the second threshold value and smaller than the designed maximum radius of the via hole anti-pad, the relation between the first distance and the radius of the via hole anti-pad is as follows: the first distance is 75-2 the radius of the via antipad.

For different anti sizes, wiring design in different modes needs to be carried out in an anti area, and the two are combined to find the optimal design. Generally, when the radius of the differential is smaller than 23mil, the capacitance at the via is larger, the impedance is reduced more seriously, and the value D can be increased appropriately, which is suggested to be 2 × differential-10 mil, that is, the differential line is delayed from coupling, and the impedance is increased appropriately. When the radius of the anti is larger than 25mil and smaller than 35mil (the radius of the anti is not larger than 35mil by conventional design), the capacitance at the through hole is reduced, the impedance rises, the differential lines can be coupled as early as possible, and the suggested impedance is 75-2 × anti, so that the overall impedance consistency of the link is improved.

Fig. 5 is a first layout diagram of routing in a via insulation area according to embodiment 1 of the present invention; as shown in fig. 6, which is a second design diagram for routing through the via insulation area in embodiment 1 of the present invention, for an insulation of a certain specific size, the routing of the insulation area may have various forms, and a linear distance D between a differential line coupling position and the middle of a differential signal hole is studied as a variable, and the maximum distance is 30 mils by traversing with 0mil as an initial value and 5 mils as a step length. Where the maximum is the radius of the anti-pad. The initial value in this application may start at 0mil or at a maximum value. And designing the step size of traversal according to different initial values, wherein the traversed area is from D equal to 0 to D equal to the radius of the anti-bonding pad.

Impedance simulation is performed on the via hole, and fig. 7 is a simulation diagram of a TDR waveform corresponding to a radius of an anti-pad of 15mil in embodiment 1 of the present invention. Firstly, an optimal anti-pad wiring mode is found, namely a parameter D corresponding to the minimum impedance change at a via hole is found, the parameter D is 20mil at the moment, the maximum deviation impedance corresponding to the situation is 78.56ohm, and the secondary design does not meet the design requirement. Wherein the waveform information:

m7 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 15 mil; d is 0 mil;

m6 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 15 mil; d is-5 mil;

m5 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 15 mil; d is-10 mil;

m4 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 15 mil; d is-15 mil;

m3 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 15 mil; d is-20 mil;

m2 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 15 mil; d ═ 25 mil;

m1 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 15 mil; d is-30 mil;

FIG. 8 is a simulation diagram of a TDR waveform with a 20mil anti-pad radius according to example 1 of the present invention. Firstly, an optimal anti wiring mode is found, namely a parameter D corresponding to the minimum impedance change at the position of a through hole is found, the parameter D is 30mil at the moment, the maximum deviation impedance corresponding to the condition is 82.43ohm, and the secondary design does not meet the design requirement. Wherein the curve information is as follows:

m7 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 20 mil; d is 0 mil;

m6 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 20 mil; d is-5 mil;

m5 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 20 mil; d is-10 mil;

m4 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 20 mil; d is-15 mil;

m3 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 20 mil; d is-20 mil;

m2 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 20 mil; d ═ 25 mil;

m1 TDR differential signal impedance; setting information: the radius of the reverse welding disc is 20 mil; d is-30 mil;

FIG. 9 is a simulation diagram of a TDR waveform with a reverse pad radius of 25mil according to example 1 of the present invention. Firstly, an optimal anti-pad wiring mode is found, namely a parameter D corresponding to the minimum impedance change at the position of a via hole is 25mil at the moment, the maximum deviation impedance corresponding to the condition is 87.02ohm, and the secondary design does not meet the design requirement. Wherein the curve information is as follows:

m7 TDR differential signal impedance; setting information: anti-pad radius 25 mil; d is 0 mil;

m6 TDR differential signal impedance; setting information: anti-pad radius 25 mil; d is-5 mil;

m5 TDR differential signal impedance; setting information: anti-pad radius 25 mil; d is-10 mil;

m4 TDR differential signal impedance; setting information: anti-pad radius 25 mil; d is-15 mil;

m3 TDR differential signal impedance; setting information: anti-pad radius 25 mil; d is-20 mil;

m2 TDR differential signal impedance; setting information: anti-pad radius 25 mil; d ═ 25 mil;

m1 TDR differential signal impedance; setting information: anti-pad radius 25 mil; d is-30 mil;

FIG. 10 is a simulation diagram of a TDR waveform with a reverse pad radius of 30mil according to example 1 of the present invention. The optimal anti routing mode is found first, that is, the parameter D corresponding to the minimum impedance change at the via hole is 20 mils at this time, and the maximum deviation impedance corresponding to this case is 86.74 ohms. The secondary design meets the design requirements. Wherein the curve information is as follows:

m7 TDR differential signal impedance; setting information: the anti-pad radius is 30 mil; d is 0 mil;

m6 TDR differential signal impedance; setting information: the anti-pad radius is 30 mil; d is-5 mil;

m5 TDR differential signal impedance; setting information: the anti-pad radius is 30 mil; d is-10 mil;

m4 TDR differential signal impedance; setting information: the anti-pad radius is 30 mil; d is-15 mil;

m3 TDR differential signal impedance; setting information: the anti-pad radius is 30 mil; d is-20 mil;

m2 TDR differential signal impedance; setting information: the anti-pad radius is 30 mil; d ═ 25 mil;

m1 TDR differential signal impedance; setting information: the anti-pad radius is 30 mil; d is-30 mil;

it can be seen from the above simulation that, for different anti sizes, different wiring designs need to be performed in the anti area, and the two are combined to find the optimal design. Generally, when the radius of the differential is smaller than 23mil, the capacitance at the via is larger, the impedance is reduced more seriously, and the value D can be increased appropriately, which is suggested to be 2 × differential-10 mil, that is, the differential line is delayed from coupling, and the impedance is increased appropriately. When the radius of the anti is larger than 25mil and smaller than 35mil (the radius of the anti is not larger than 35mil by conventional design), the capacitance at the through hole is reduced, the impedance rises, the differential lines can be coupled as early as possible, and the suggested impedance is 75-2 × anti, so that the overall impedance consistency of the link is improved.

The method for optimizing the routing of the via hole reverse bonding pad further comprises back drilling a signal hole in the via hole reverse bonding pad when the impedance is optimized.

The method for determining the back drilling depth of the signal hole comprises the following steps: calculating the thickness of the via stub according to the thickness of the signal routing and the printed circuit board; and determining the back drilling depth of the signal hole according to the thickness of the via hole stub.

The thickness of the via stub is equal to the thickness of the printed circuit board (L)₁To L_NThickness of (d);

wherein L is₁A first layer which is a signal line; said L_NIs the nth layer of the signal layer.

The method for determining the back drilling depth of the signal hole by the thickness of the via hole stub comprises the following steps: the depth of the signal hole back drilling is equal to the thickness of the via stub, namely-10 mil. And the back drilling of the signal hole is added, so that the impedance characteristic can be better optimized.

The impedance characteristic of the via hole needs to be paid attention to when the high-speed link is designed, when the impedance of the via hole is optimized, besides the fact that the size of the anti is changed, the routing mode in the anti area can be optimized, therefore, the impedance of the via hole can be further optimized, the continuity of the link impedance is improved, the signal reflection is reduced, and the signal transmission quality is effectively improved.

The invention can optimize the wiring mode in the region of the reverse welding disc, and back-drill the signal holes in the region of the reverse welding disc, thereby better optimizing the impedance of the via holes, improving the continuity of the impedance of the link and better improving the signal transmission quality.

Example 2

Based on the method for optimizing the routing of the via hole anti-pad provided by the embodiment 1 of the invention, the embodiment 2 of the invention provides a printed circuit board. The printed circuit board is processed by adopting a method for optimizing via hole reverse pad routing; the method for manufacturing the printed circuit board comprises the following steps: traversing by taking a first numerical value of the first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of the via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole.

The first value is 0mil or the radius of the via anti-pad. When the first value is 0mil, the second value is any value which is larger than 0 and smaller than the radius of the via hole anti-pad; and when the first value is the radius of the via hole anti-pad, the second value is smaller than 0, and the absolute value is smaller than any value of the radius of the via hole anti-pad.

When the radius of the via anti-pad is smaller than the first threshold, the relationship between the first distance and the radius of the via anti-pad is as follows: the first distance is 2 via anti-pad radius-10 mil. When the radius of the via hole anti-pad is larger than the second threshold value and smaller than the designed maximum radius of the via hole anti-pad, the relation between the first distance and the radius of the via hole anti-pad is as follows: the first distance is 75-2 the radius of the via antipad.

The first value is 0mil or the radius of the via anti-pad.

When the first value is 0mil, the second value is any value which is larger than 0 and smaller than the radius of the via hole anti-pad; and when the first value is the radius of the via hole anti-pad, the second value is smaller than 0, and the absolute value is smaller than any value of the radius of the via hole anti-pad.

For different anti sizes, wiring design in different modes needs to be carried out in an anti area, and the two are combined to find the optimal design. Generally, when the radius of the differential is smaller than 23mil, the capacitance at the via is larger, the impedance is reduced more seriously, and the value D can be increased appropriately, which is suggested to be 2 × differential-10 mil, that is, the differential line is delayed from coupling, and the impedance is increased appropriately. When the radius of the anti is larger than 25mil and smaller than 35mil (the radius of the anti is not larger than 35mil by conventional design), the capacitance at the through hole is reduced, the impedance rises, the differential lines can be coupled as early as possible, and the suggested impedance is 75-2 × anti, so that the overall impedance consistency of the link is improved.

The method for optimizing the routing of the via hole reverse bonding pad further comprises back drilling a signal hole in the via hole reverse bonding pad when the impedance is optimized.

The method for determining the back drilling depth of the signal hole comprises the following steps: calculating the thickness of the via stub according to the thickness of the signal routing and the printed circuit board; and determining the back drilling depth of the signal hole according to the thickness of the via hole stub.

The thickness of the via stub is equal to the thickness of the printed circuit board (L)₁To L_NThickness of (d);

wherein L is₁A first layer which is a signal line; said L_NIs the nth layer of the signal layer.

The method for determining the back drilling depth of the signal hole by the thickness of the via hole stub comprises the following steps: the depth of the signal hole back drilling is equal to the thickness of the via stub, namely-10 mil. And the back drilling of the signal hole is added, so that the impedance characteristic can be better optimized.

The impedance characteristic of the via hole needs to be paid attention to when the high-speed link is designed, when the impedance of the via hole is optimized, besides the fact that the size of the anti is changed, the routing mode in the anti area can be optimized, therefore, the impedance of the via hole can be further optimized, the continuity of the link impedance is improved, the signal reflection is reduced, and the signal transmission quality is effectively improved.

The invention can optimize the wiring mode in the region of the reverse welding disc, and back-drill the signal holes in the region of the reverse welding disc, thereby better optimizing the impedance of the via holes, improving the continuity of the impedance of the link and better improving the signal transmission quality.

Example 3

Based on the method for optimizing the via hole anti-pad routing provided in embodiment 1 of the present invention, embodiment 3 of the present invention provides a via hole anti-pad routing optimization device for a printed circuit board, including:

a memory for storing a computer program; and the processor is used for realizing the method steps of optimizing the routing of the via hole anti-bonding pad when executing a computer program. The method comprises the following steps:

traversing by taking a first numerical value of the first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of the via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole.

The first value is 0mil or the radius of the via anti-pad. When the first value is 0mil, the second value is any value which is larger than 0 and smaller than the radius of the via hole anti-pad; and when the first value is the radius of the via hole anti-pad, the second value is smaller than 0, and the absolute value is smaller than any value of the radius of the via hole anti-pad.

When the radius of the via anti-pad is smaller than the first threshold, the relationship between the first distance and the radius of the via anti-pad is as follows: the first distance is 2 via anti-pad radius-10 mil. When the radius of the via hole anti-pad is larger than the second threshold value and smaller than the designed maximum radius of the via hole anti-pad, the relation between the first distance and the radius of the via hole anti-pad is as follows: the first distance is 75-2 the radius of the via antipad.

The first value is 0mil or the radius of the via anti-pad.

When the first value is 0mil, the second value is any value which is larger than 0 and smaller than the radius of the via hole anti-pad; and when the first value is the radius of the via hole anti-pad, the second value is smaller than 0, and the absolute value is smaller than any value of the radius of the via hole anti-pad.

For different anti sizes, wiring design in different modes needs to be carried out in an anti area, and the two are combined to find the optimal design. Generally, when the radius of the differential is smaller than 23mil, the capacitance at the via is larger, the impedance is reduced more seriously, and the value D can be increased appropriately, which is suggested to be 2 × differential-10 mil, that is, the differential line is delayed from coupling, and the impedance is increased appropriately. When the radius of the anti is larger than 25mil and smaller than 35mil (the radius of the anti is not larger than 35mil by conventional design), the capacitance at the through hole is reduced, the impedance rises, the differential lines can be coupled as early as possible, and the suggested impedance is 75-2 × anti, so that the overall impedance consistency of the link is improved.

The method for optimizing the routing of the via hole reverse bonding pad further comprises back drilling a signal hole in the via hole reverse bonding pad when the impedance is optimized.

The method for determining the back drilling depth of the signal hole comprises the following steps: calculating the thickness of the via stub according to the thickness of the signal routing and the printed circuit board; and determining the back drilling depth of the signal hole according to the thickness of the via hole stub.

The thickness of the via stub is equal to the thickness of the printed circuit board (L)₁To L_NThickness of (d);

wherein L is₁A first layer which is a signal line; said L_NIs the nth layer of the signal layer.

The method for determining the back drilling depth of the signal hole by the thickness of the via hole stub comprises the following steps: the depth of the signal hole back drilling is equal to the thickness of the via stub, namely-10 mil. And the back drilling of the signal hole is added, so that the impedance characteristic can be better optimized.

The impedance characteristic of the via hole needs to be paid attention to when the high-speed link is designed, when the impedance of the via hole is optimized, besides the fact that the size of the anti is changed, the routing mode in the anti area can be optimized, therefore, the impedance of the via hole can be further optimized, the continuity of the link impedance is improved, the signal reflection is reduced, and the signal transmission quality is effectively improved.

The invention can optimize the wiring mode in the region of the reverse welding disc, and back-drill the signal holes in the region of the reverse welding disc, thereby better optimizing the impedance of the via holes, improving the continuity of the impedance of the link and better improving the signal transmission quality.

Need to explain: the technical solution of the present invention also provides an electronic device, including: the communication interface can carry out information interaction with other equipment such as network equipment and the like; and the processor is connected with the communication interface to realize information interaction with other equipment, and is used for executing the method for optimizing the via hole anti-pad routing provided by one or more technical schemes when running a computer program, and the computer program is stored on the memory. Of course, in practice, the various components in an electronic device are coupled together by a bus system. It will be appreciated that a bus system is used to enable communications among the components. The bus system includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for the sake of clarity the various buses are labeled as a bus system in figure 4. The memory in the embodiments of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device. It will be appreciated that the memory can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The memories described in the embodiments of the present application are intended to comprise, without being limited to, these and any other suitable types of memory. The method disclosed in the embodiments of the present application may be applied to a processor, or may be implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a DSP (Digital Signal Processing, i.e., a chip capable of implementing Digital Signal Processing technology), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc. The processor may implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium located in a memory where a processor reads the programs in the memory and in combination with its hardware performs the steps of the method as previously described. When the processor executes the program, corresponding processes in the methods of the embodiments of the present application are implemented, and for brevity, are not described herein again.

Example 4

Based on the method for optimizing the routing of the via hole anti-pad provided in embodiment 1 of the present invention, embodiment 4 of the present invention further provides a computer readable storage medium, where a computer program is stored, and the computer program, when executed by a processor, implements the method steps for optimizing the routing of the via hole anti-pad.

The method comprises the following steps:

traversing by taking a first numerical value of the first distance as an initial value and a second numerical value as a step length aiming at via hole anti-pads with different sizes, and determining the corresponding first distance when the impedance of the via hole is minimum; the first distance is a straight line distance between a coupling position of the differential line in the via hole reverse pad and the middle of the differential signal hole.

The first value is 0mil or the radius of the via anti-pad. When the first value is 0mil, the second value is any value which is larger than 0 and smaller than the radius of the via hole anti-pad; and when the first value is the radius of the via hole anti-pad, the second value is smaller than 0, and the absolute value is smaller than any value of the radius of the via hole anti-pad.

When the radius of the via anti-pad is smaller than the first threshold, the relationship between the first distance and the radius of the via anti-pad is as follows: the first distance is 2 via anti-pad radius-10 mil. When the radius of the via hole anti-pad is larger than the second threshold value and smaller than the designed maximum radius of the via hole anti-pad, the relation between the first distance and the radius of the via hole anti-pad is as follows: the first distance is 75-2 the radius of the via antipad.

The first value is 0mil or the radius of the via anti-pad.

When the first value is 0mil, the second value is any value which is larger than 0 and smaller than the radius of the via hole anti-pad; and when the first value is the radius of the via hole anti-pad, the second value is smaller than 0, and the absolute value is smaller than any value of the radius of the via hole anti-pad.

For different anti sizes, wiring design in different modes needs to be carried out in an anti area, and the two are combined to find the optimal design. Generally, when the radius of the differential is smaller than 23mil, the capacitance at the via is larger, the impedance is reduced more seriously, and the value D can be increased appropriately, which is suggested to be 2 × differential-10 mil, that is, the differential line is delayed from coupling, and the impedance is increased appropriately. When the radius of the anti is larger than 25mil and smaller than 35mil (the radius of the anti is not larger than 35mil by conventional design), the capacitance at the through hole is reduced, the impedance rises, the differential lines can be coupled as early as possible, and the suggested impedance is 75-2 × anti, so that the overall impedance consistency of the link is improved.

The method for optimizing the routing of the via hole reverse bonding pad further comprises back drilling a signal hole in the via hole reverse bonding pad when the impedance is optimized.

The method for determining the back drilling depth of the signal hole comprises the following steps: calculating the thickness of the via stub according to the thickness of the signal routing and the printed circuit board; and determining the back drilling depth of the signal hole according to the thickness of the via hole stub.

The thickness of the via stub is equal to the thickness of the printed circuit board (L)₁To L_NThickness of (d);

wherein L is₁A first layer which is a signal line; said L_NIs the nth layer of the signal layer.

The method for determining the back drilling depth of the signal hole by the thickness of the via hole stub comprises the following steps: the depth of the signal hole back drilling is equal to the thickness of the via stub, namely-10 mil. And the back drilling of the signal hole is added, so that the impedance characteristic can be better optimized.

The impedance characteristic of the via hole needs to be paid attention to when the high-speed link is designed, when the impedance of the via hole is optimized, besides the fact that the size of the anti is changed, the routing mode in the anti area can be optimized, therefore, the impedance of the via hole can be further optimized, the continuity of the link impedance is improved, the signal reflection is reduced, and the signal transmission quality is effectively improved.

The invention can optimize the wiring mode in the region of the reverse welding disc, and back-drill the signal holes in the region of the reverse welding disc, thereby better optimizing the impedance of the via holes, improving the continuity of the impedance of the link and better improving the signal transmission quality.

Embodiments of the present application further provide a storage medium, that is, a computer storage medium, specifically, a computer-readable storage medium, for example, a memory storing a computer program, where the computer program is executable by a processor to perform the steps of the foregoing method. The computer readable storage medium may be Memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface Memory, optical disk, or CD-ROM.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code. Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof that contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.

For the description of the related parts in the device and the storage medium for optimizing the routing of the via anti-pad provided in the embodiment of the present application, reference may be made to the detailed description of the corresponding parts in the method for optimizing the routing of the via anti-pad provided in embodiment 1 of the present application, and details are not described here again.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include elements inherent in the list. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. In addition, parts of the above technical solutions provided in the embodiments of the present application, which are consistent with the implementation principles of corresponding technical solutions in the prior art, are not described in detail so as to avoid redundant description.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the scope of the present invention is not limited thereto. Various modifications and alterations will occur to those skilled in the art based on the foregoing description. And are neither required nor exhaustive of all embodiments. On the basis of the technical scheme of the invention, various modifications or changes which can be made by a person skilled in the art without creative efforts are still within the protection scope of the invention.