阅读说明：本技术 一种通用宽带雷达信号监测设备 (Universal broadband radar signal monitoring equipment ) 是由 夏益锋 朱波 纪要 尚仁超 史经丛 陶升炜 潘建华 于 2021-09-30 设计创作，主要内容包括：一种通用宽带雷达信号监测设备。提供了一种便于携带,方便架设,能够在复杂的电磁频谱空间内对雷达信号进行监测和特征分析的通用宽带雷达信号监测设备。包括微波机箱、接收机箱和显示控制单元,所述微波机箱、接收机箱和显示控制单元之间具有通讯连接；所述微波机箱包括干涉仪接收天线阵、全向天线、接收前端和下变频模块,所述接收前端前接所述的干涉仪接收天线阵和全向天线,所述接收前端后接所述下变频模块；所述显示控制单元设在所述接收机箱外,所述显示控制单元连接所述信号分选及主控模块。本发明既具有瞬时全频段、全方位快速频谱监视功能,也具有一定带宽和方位内的雷达信号分选、脉间分析和脉内调制特征分析功能。(A universal broadband radar signal monitoring device. The utility model provides a portable conveniently erects, can monitor and characteristic analysis's general broadband radar signal monitoring facilities to radar signal in the electromagnetic spectrum space of complicacy. The microwave receiver comprises a microwave case, a receiver case and a display control unit, wherein the microwave case, the receiver case and the display control unit are in communication connection; the microwave case comprises an interferometer receiving antenna array, an omnidirectional antenna, a receiving front end and a down-conversion module, wherein the receiving front end is connected with the interferometer receiving antenna array and the omnidirectional antenna in front, and the receiving front end is connected with the down-conversion module in back; the display control unit is arranged outside the receiver case and is connected with the signal sorting and main control module. The invention has the functions of instantaneous full-band and omnibearing rapid spectrum monitoring, and also has the functions of radar signal sorting, inter-pulse analysis and intra-pulse modulation characteristic analysis in a certain bandwidth and direction.)

1. The universal broadband radar signal monitoring equipment is characterized by comprising a microwave case, a receiver case and a display control unit, wherein the microwave case, the receiver case and the display control unit are in communication connection;

the microwave case comprises an interferometer receiving antenna array, an omnidirectional antenna, a receiving front end and a down-conversion module, wherein the receiving front end is connected with the interferometer receiving antenna array and the omnidirectional antenna in front, and the receiving front end is connected with the down-conversion module in back;

the interferometer receives signals of an antenna array and an omnidirectional antenna and is connected to the receiving front end, the receiving front end sends a first signal and a second signal, and the first signal of the receiving front end is connected to the down-conversion module;

the receiver case comprises a digital interferometer receiver, a single-bit receiver, a storage module and a signal sorting and main control module, wherein the digital interferometer receiver is connected with the down-conversion module in front, and a signal II at the receiving front end is connected with the single-bit receiver;

the signal sorting and main control module is respectively connected with the digital interferometer receiver, the single-bit receiver and the storage module,

the display control unit is arranged outside the receiver case and is connected with the signal sorting and main control module.

2. The universal broadband radar signal monitoring device according to claim 1, wherein the interferometer receiving antenna array comprises a first antenna array consisting of four 2-6 GHz directional antennas and a second antenna array consisting of four 6-18 GHz directional antennas; four 2-6 GHz directional antennas of the first antenna array are annularly and uniformly distributed, and four 6-18 GHz directional antennas of the second antenna array are annularly and uniformly distributed.

3. The universal broadband radar signal monitoring device according to claim 1, wherein the receiving front end comprises a 2-6 GHz radio frequency front end module and a 6-18 GHz radio frequency front end module,

the 2-6 GHz radio frequency front-end module comprises four channels I, wherein each channel I comprises a coupler I, a filter I, an amplitude limiter I, a low noise amplifier I and a program-controlled attenuator I which are sequentially connected; the coupler I in each channel I is connected with each 2-6 GHz antenna of the antenna array I in advance in a one-to-one correspondence mode, and the coupler I in each channel I is also connected with a calibration signal I in advance;

the 6-18 GHz radio frequency front-end module comprises four channels II, and each channel II comprises a coupler II, a filter II, an amplitude limiter II, a low noise amplifier II and a programmable attenuator II which are sequentially connected; the second coupler in each second channel is connected with the 6-18 GHz antenna of the second antenna array in front in a one-to-one corresponding mode, and the second coupler in each second channel is further connected with a second calibration signal in front.

4. The universal broadband radar signal monitoring device according to claim 1, wherein the down-conversion module comprises a 2-8 GHz down-conversion module and an 8-18 GHz down-conversion module, and is configured to down-convert an input 2-8 GHz and 8-18 GHz radio frequency signal to an intermediate frequency of 1.3-2.3 GHz, and transmit the processed signal to the receiver case.

5. The universal wideband radar signal monitoring device according to claim 1, wherein said single bit receiver comprises a radio frequency front end, an analog-to-digital conversion unit, a fast fourier transform unit, and a frequency selective logic unit.

6. The universal wideband radar signal monitoring device according to claim 5, wherein the overall noise figure NF of the RF front-end is:

NF₁is the noise figure of the first stage circuit, NF₂Is the noise figure of the second stage circuit, NF₃Is the noise figure of the third stage circuit, NF_nIs the noise coefficient of the nth stage circuit, n is the cascade circuit of the RF front endNumber of stages, G₁Is the gain of the first stage circuit, G₂Is the gain of the second stage circuit, G_n-1Is the gain of the (n-1) th stage circuit;

the radio frequency front end also comprises a detection logarithmic video amplifier.

Technical Field

The invention relates to the technical field of electronic warfare, in particular to radar signal monitoring equipment.

Background

With the rapid development of modern radar technology, especially the wide application of various multifunctional radars, great challenges are brought to radar radiation source identification, and modern war has brought electronic reconnaissance and electronic countermeasure into important fields, the electromagnetic spectrum space has no countermeasure without smoke at all times, the difference between wartime and normal time is not available, and daily electronic reconnaissance is the most basic and normalized mode for 'identifying' the electromagnetic spectrum space. The conventional electromagnetic spectrum space electronic reconnaissance needs to adopt reconnaissance equipment with large volume and complex structure.

Therefore, how to quickly and conveniently comprehensively master radar information of a war zone in a complex electromagnetic spectrum space, realize monitoring of radar signals in the complex electromagnetic environment, and perform radar signal characteristic analysis becomes a problem to be solved in the field.

Disclosure of Invention

Aiming at the problems, the invention provides the universal broadband radar signal monitoring equipment which is convenient to carry and erect and can monitor and analyze the radar signals in a complex electromagnetic spectrum space.

The technical scheme of the invention is as follows: a universal broadband radar signal monitoring device comprises a microwave case, a receiver case and a display control unit, wherein the microwave case, the receiver case and the display control unit are in communication connection;

the microwave case comprises an interferometer receiving antenna array, an omnidirectional antenna, a receiving front end and a down-conversion module, wherein the receiving front end is connected with the interferometer receiving antenna array and the omnidirectional antenna in front, and the receiving front end is connected with the down-conversion module in back;

the interferometer receives signals of an antenna array and an omnidirectional antenna and is connected to the receiving front end, the receiving front end sends a first signal and a second signal, and the first signal of the receiving front end is connected to the down-conversion module;

the receiver case comprises a digital interferometer receiver, a single-bit receiver, a storage module and a signal sorting and main control module, wherein the digital interferometer receiver is connected with the down-conversion module in front, and a signal II at the receiving front end is connected with the single-bit receiver;

the signal sorting and main control module is respectively connected with the digital interferometer receiver, the single-bit receiver and the storage module,

the display control unit is arranged outside the receiver case and is connected with the signal sorting and main control module.

The interferometer receiving antenna array comprises a first antenna array consisting of four 2-6 GHz directional antennas and a second antenna array consisting of four 6-18 GHz directional antennas; four 2-6 GHz directional antennas of the first antenna array are annularly and uniformly distributed, and four 6-18 GHz directional antennas of the second antenna array are annularly and uniformly distributed.

The receiving front end comprises a 2-6 GHz radio frequency front end module and a 6-18 GHz radio frequency front end module,

the 2-6 GHz radio frequency front-end module comprises four channels I, wherein each channel I comprises a coupler I, a filter I, an amplitude limiter I, a low noise amplifier I and a program-controlled attenuator I which are sequentially connected; the coupler I in each channel I is connected with each 2-6 GHz antenna of the antenna array I in advance in a one-to-one correspondence mode, and the coupler I in each channel I is also connected with a calibration signal I in advance;

the 6-18 GHz radio frequency front-end module comprises four channels II, and each channel II comprises a coupler II, a filter II, an amplitude limiter II, a low noise amplifier II and a programmable attenuator II which are sequentially connected; the second coupler in each second channel is connected with the 6-18 GHz antenna of the second antenna array in front in a one-to-one corresponding mode, and the second coupler in each second channel is further connected with a second calibration signal in front.

The down-conversion module comprises a 2-8 GHz down-conversion module and an 8-18 GHz down-conversion module, and is used for carrying out down-conversion on input 2-8 GHz and 8-18 GHz radio frequency signals to an intermediate frequency of 1.3-2.3 GHz, and transmitting the processed signals to the receiver case.

The single-bit receiver comprises a radio frequency front end, an analog/digital conversion unit, a fast Fourier transform unit and a frequency selection logic unit.

The total noise figure NF of the radio frequency front end is:

NF₁is the noise figure of the first stage circuit, NF₂Is the noise figure of the second stage circuit, NF₃Is the noise figure of the third stage circuit, NF_nIs the noise coefficient of the nth stage circuit, n is the stage number of the cascade circuit of the radio frequency front end, G₁Is the gain of the first stage circuit, G₂Is the gain of the second stage circuit, G_n-1Is the gain of the (n-1) th stage circuit;

the radio frequency front end also comprises a detection logarithmic video amplifier.

The invention adopts the combination of the broadband single-bit receiver technology and the multi-channel interferometer technology to monitor and intercept the space radar signal, completes the measurement of the frequency, the pulse width, the repetition frequency and the azimuth information of the radar signal, obtains the radar signal existing in the space after the complex signal sorting, and can also analyze the concerned frequency band and the target in detail and measure the inter-pulse and intra-pulse modulation characteristics. In the invention, in order to save energy and improve measurement precision, an interferometer receiving antenna array is not opened in real time, however, in order to avoid losing radar signals of each antenna in the interferometer receiving antenna array within the open window time of starting at intervals, the invention senses wide-area radar signals by utilizing an omnidirectional antenna, judges the direction of the radar signals, then transmits the direction signals of the sensed radar signals to the interferometer receiving antenna array, and then opens each antenna in the corresponding direction to collect the radar signals; the interferometer receiving antenna array is wide in corresponding coverage range when opened, the working frequency range is 2-18 GHz, and the frequency ranges of a search/tracking radar, a fire control radar, an imaging radar and a part of missile-borne radar are covered; the system has the functions of instantaneous full-band and omnibearing rapid spectrum monitoring, and also has the functions of radar signal sorting, inter-pulse analysis and intra-pulse modulation characteristic analysis in a certain bandwidth and direction; the fingerprint feature analysis function for a certain radar signal is provided.

Drawings

Figure 1 is a schematic view of the principle of the invention,

FIG. 2 is a schematic diagram of the 2-6 GHz antenna array of the present invention,

FIG. 3 is a schematic diagram of a 6-18 GHz antenna array according to the invention,

FIG. 4 is a schematic diagram of the 2-18 GHz receiver front-end of the present invention,

FIG. 5 is a schematic diagram of the 2-8 GHz down-conversion module according to the present invention,

FIG. 6 is a schematic diagram of the 8-18 GHz down-conversion module according to the present invention,

figure 7 is a schematic diagram of a receiver chassis of the present invention,

figure 8 is a 4-point twiddle factor quantization graph in accordance with the present invention,

figure 9 is an 8-point twiddle factor quantization diagram of the present invention,

figure 10 is a 12-point twiddle factor quantization graph in accordance with the present invention,

FIG. 11 is a diagram of the relationship between the dynamic range and the quantization bits of the input signal when 4-point twiddle factor is quantized according to the present invention,

FIG. 12 is a diagram of the relationship between the dynamic range and the quantization bits of the input signal when 8-point twiddle factor is quantized according to the present invention,

FIG. 13 is a diagram of the relationship between the dynamic range and the quantization bits of the input signal when quantizing 12-point twiddle factors according to the present invention,

figure 14 is a time-frequency contour plot for 1bit quantization of the input signal and 4-point quantization of the twiddle factor of the present invention,

figure 15 is a time-frequency contour plot for 2bit quantization of the input signal and 8-point quantization of the twiddle factor of the present invention,

figure 16 is a time-frequency contour plot obtained from a conventional STFT calculation,

fig. 17 is a plot of time-frequency contours calculated from the STFT after quantization in accordance with the present invention.

Detailed Description

The present invention is further described below with reference to fig. 1-17, and includes a microwave chassis, a receiver chassis, and a display control unit, which are communicatively connected to each other;

the microwave case comprises an interferometer receiving antenna array, an omnidirectional antenna, a receiving front end and a down-conversion module, wherein the receiving front end is connected with the interferometer receiving antenna array and the omnidirectional antenna in front, and the receiving front end is connected with the down-conversion module in back;

the interferometer receives signals of an antenna array and an omnidirectional antenna and is connected to the receiving front end, the receiving front end sends a first signal and a second signal, and the first signal of the receiving front end is connected to the down-conversion module;

the receiver case comprises a digital interferometer receiver, a single-bit receiver, a storage module and a signal sorting and main control module, wherein the digital interferometer receiver is connected with the down-conversion module in front, and a signal II at the receiving front end is connected with the single-bit receiver;

the signal sorting and main control module is respectively connected with the digital interferometer receiver, the single-bit receiver and the storage module,

the display control unit is arranged outside the receiver case and is connected with the signal sorting and main control module.

The invention adopts the combination of the broadband single-bit receiver technology and the multi-channel interferometer technology to monitor and intercept the space radar signal, completes the measurement of the frequency, the pulse width, the repetition frequency and the azimuth information of the radar signal, obtains the radar signal existing in the space after the complex signal sorting, and can also analyze the concerned frequency band and the target in detail and measure the inter-pulse and intra-pulse modulation characteristics. In the invention, in order to save energy and improve measurement precision, an interferometer receiving antenna array is not opened in real time, however, in order to avoid losing radar signals of each antenna in the interferometer receiving antenna array within the open window time of starting at intervals, the invention senses wide-area radar signals by utilizing an omnidirectional antenna, judges the direction of the radar signals, then transmits the direction signals of the sensed radar signals to the interferometer receiving antenna array, and then opens each antenna in the corresponding direction to collect the radar signals; the interferometer receiving antenna array is wide in corresponding coverage range when opened, the working frequency range is 2-18 GHz, and the frequency ranges of a search/tracking radar, a fire control radar, an imaging radar and a part of missile-borne radar are covered; the system has the functions of instantaneous full-band and omnibearing rapid spectrum monitoring, and also has the functions of radar signal sorting, inter-pulse analysis and intra-pulse modulation characteristic analysis in a certain bandwidth and direction; the fingerprint feature analysis function for a certain radar signal is provided.

The interferometer receiving antenna array comprises a first antenna array consisting of four 2-6 GHz directional antennas and a second antenna array consisting of four 6-18 GHz directional antennas; four 2-6 GHz directional antennas of the first antenna array are annularly and uniformly distributed, and four 6-18 GHz directional antennas of the second antenna array are annularly and uniformly distributed.

The receiving front end comprises a 2-6 GHz radio frequency front end module and a 6-18 GHz radio frequency front end module,

the 2-6 GHz radio frequency front-end module comprises four channels I, wherein each channel I comprises a coupler I, a filter I, an amplitude limiter I, a low noise amplifier I and a program-controlled attenuator I which are sequentially connected; the coupler I in each channel I is connected with each 2-6 GHz antenna of the antenna array I in advance in a one-to-one correspondence mode, and the coupler I in each channel I is also connected with a calibration signal I in advance;

the 6-18 GHz radio frequency front-end module comprises four channels II, and each channel II comprises a coupler II, a filter II, an amplitude limiter II, a low noise amplifier II and a programmable attenuator II which are sequentially connected; the second coupler in each second channel is connected with the 6-18 GHz antenna of the second antenna array in front in a one-to-one corresponding mode, and the second coupler in each second channel is further connected with a second calibration signal in front.

The coupler simultaneously accesses the external signal and the calibration signal and synthesizes the signals,

the filter filters out-of-band signals in the environment,

the limiter protects the back-end circuit from being burned by high-power input signals,

the low noise amplifier compensates for the link loss,

the programmable attenuator realizes the manual adjustment dynamic of input signals.

As shown in fig. 2, the 2-6 GHz antenna array includes 4 directional antennas, 4 paths of 2-6 GHz radio frequency signals enter the 2-6 GHz receiving front end, the 2-6 GHz receiving front end performs filtering, amplitude limiting, amplification and sensitivity control on the entering radar signals, and inputs the 4 paths of signals into 2-18 GHz down-conversion.

As shown in fig. 3, the 6-18 GHz antenna array includes 4 directional antennas, wherein 4 paths of 6-18 GHz radio frequency signals enter a 6-18 GHz receiving front end, the 6-18 GHz receiving front end performs filtering, amplitude limiting, amplification and sensitivity control on the entering radar signals, and inputs the 4 paths of signals into 2-18 GHz down-conversion.

The input end of each receiving front end is a coupler, synthesis of external receiving signals and calibration input signals is completed, then the signals are filtered, limited and amplified and then output to a 2-18 down conversion unit, the filter filters out-of-band signals in the environment, the limiter protects a rear end circuit from being burnt by high-power input signals, the low-noise amplifier compensates link loss, and the program-controlled attenuator realizes manual adjustment dynamics of the input signals.

When the equipment is in a monitoring mode, the calibration input is cut off, and the input signal of the calibration branch circuit is ensured to have no influence on direction finding. When the equipment works in a self-checking mode, the input power of the calibration signal is high, and the external receiving signal has no influence on the calibration branch.

The signal is filtered, amplitude limited and amplified, and then power is divided into two paths. One path of the signal is output to a 2-18 down conversion unit, and the other path of the signal is output to a single-bit receiver.

The down-conversion module comprises a 2-8 GHz down-conversion module and an 8-18 GHz down-conversion module, and is used for carrying out down-conversion on input 2-8 GHz and 8-18 GHz radio frequency signals to an intermediate frequency of 1.3-2.3 GHz, and transmitting the processed signals to the receiver case. The receiver case (intermediate frequency) is the core of the whole digital signal processing, and is used for converting an intermediate frequency analog signal into a digital signal and completing signal monitoring and parameter measurement in an intermediate frequency bandwidth. The method mainly comprises the steps of performing 12-bit @2.4Gsps high-speed acquisition on 1.8GHz +/-500 MHz output by a 2-18 GHz down conversion unit, obtaining high-speed ADC (analog to digital converter) data, entering an FPGA (field programmable gate array) for signal detection and parameter measurement, completing processing such as digital channelization and parameter measurement, performing full airspace frequency measurement by a single-bit receiver, performing signal sorting after PDW (pulse description word) parameters are obtained, obtaining EDW (radiation source description word) data, transmitting the EDW data to a display control device, and performing data storage and calculation processing.

As shown in fig. 7, the digital receiving board receives 4 channels of direction-finding signals and 1 channel of pressure side lobe signals output from the down-conversion unit, completes the functions of acquisition of intermediate frequency signals, pulse detection, parameter measurement and direction finding, sends PDW to the signal sorting board, and sends AD data and PDW data to the signal recording board.

The signal sorting and main control board sorts the PDW to obtain EDW data and reports the EDW data to the upper computer, and the control command of the upper computer is received to realize the control of the digital receiving board, the signal sorting board and the data recording board.

And the signal recording board receives and records the AD data.

The single-bit receiver comprises a radio frequency front end, an analog/digital conversion unit, a fast Fourier transform unit and a frequency selection logic unit.

Since the output of the limiting amplifier is constant, theoretically, a 1-bit ADC can be used to meet the requirement. In fact, the performance of a 2-bit adc is superior to that of a 1-bit adc, but the improvement of the performance of the receiver can hardly be brought about by the increase of the number of bits when the number of bits exceeds 3 bits, mainly because of the characteristics of the limiting amplifier and the special FFT algorithm design of the single-bit receiver, the requirements of the FFT algorithm design and the system real-time property are integrated, and the 2-bit adc is adopted in the invention. The frequency range of the signal environment suitable for the invention is 2-18 GHz, and in order to cover the bandwidth of 16GHz, the ADC sampling rate at least needs to reach 32Gsps according to the Nyquist sampling theorem. Meanwhile, considering that the amplitude-frequency characteristic of the input filter cannot be an ideal rectangle, the amplitude-frequency characteristic of the input filter is generally more similar to a smoothed trapezoid, so that the bandwidth of the actual filter has a certain spread, and therefore the sampling rate of the ADC generally needs to be designed according to 2.5 times of the input bandwidth. Therefore, the sampling rate of the ADC of the single bit receiver of the present invention is designed to be 40 Gsps.

The FFT unit is the core part of a single bit receiver. The purpose of designing a single-bit receiver is to avoid multiplication operations during the computation of the discrete fourier transform (DFT, FFT is the fast algorithm of DFT), and only keep addition operations, thus greatly reducing the processing time of FFT (fast algorithm of DFT).

The discrete fourier transform DFT can be expressed as:

in the above formula, x (N) is the nth number in the integrated input data, N is the number of the integrated data points, N and k are integers,is a Kernel function, also known as a twiddle factor.

As can be seen from the above equation, the Discrete Fourier Transform (DFT) is obtained by adding the products of the input data x (n) and the twiddle factor. If x (n) is equal to ± 1, no multiplication is needed between the input data and the twiddle factor, only addition and subtraction are needed, and the required operation complexity is greatly reduced.

The quantization format of x (n) is relatively simple due to the small number of sampling bits. However, the rotation factorIs a floating point value and has N choices, obviously, when the butterfly FFT operation is applied, a floating point algorithm which involves complex numbers is still needed except for the first stage, and the operation speed of the FFT is not effectively reduced. If the twiddle factor can be further reduced to a finite number of values (the value should be much smaller than N) and replaced by a similar integer complex value (both the real part and the imaginary part are integers), the operation complexity is obviously reduced, and the hardware implementation which is good at fixed-point parallel operation like the FPGA is more favorable. It is clear that a small number of twiddle factors are applied instead of a large number of twiddlesThe factor necessarily introduces a certain phase error, but this is traded for the great advantage of greatly increasing the signal processing speed. Rotation factorIs a complex function and therefore it cannot be represented by a real number of 1bit, the simplest way to represent the twiddle factor is to represent the real part by 1bit and the imaginary part by lbit. Fig. 8 is a 4-point twiddle factor quantization diagram with both real and imaginary parts quantized to 1bit, where values of twiddle factors are distributed on a unit circle of a complex plane, and there may be four values of ± 1 and ± j, where the twiddle factors may be represented as:

as can be seen from fig. 8: when theta is more than or equal to 0 and less than or equal to pi/4 and more than or equal to 7 pi/4 and less than 2 pi, the rotation factor is quantized to 1; when theta is more than or equal to 3 pi/4 and less than 5 pi/4, the rotating factor is quantized to-1; when the phi/4 is more than or equal to the theta and less than 3 phi/4, the twiddle factor is quantized into j; when theta is more than or equal to 5 pi/4 and less than 7 pi/4, the twiddle factor is quantized to-j.

In fact, the twiddle factors can be selected more finely, such as 8 points, 12 points, 24 points, etc., but the more complicated twiddle factors are more troublesome to calculate, and in the case of fixed quantization precision, the finer the twiddle factors is, the better the twiddle factors are, the selection is usually carried out in a compromise mode according to the system requirements and hardware speed, and the maximum twiddle factor is generally 12 points. The 8-point twiddle factor quantized values are shown in fig. 9.

In FIG. 9, the 4 vertices of the square are 1+ j, -1-j, and 1-j, respectively, and their intersections with the unit circle are 1+ j, -1-j, and 1-j, respectively

In fig. 9, the twiddle factor may be 8-point quantized in the following manner (mode 1): when theta is more than or equal to 0 and less than or equal to pi/8 and more than or equal to 15 pi/8 and less than 2 pi, the rotation factor is quantized to 1; when the theta is more than or equal to pi/8 and less than 3 pi/8, the twiddle factor is quantized to 1+ j; when theta is more than or equal to 3 pi/8 and less than 5 pi/8, the twiddle factor is quantized into j; when theta is more than or equal to 5 pi/8 and less than 7 pi/8, the twiddle factor is quantized to-1 + j; when theta is more than or equal to 7 pi/8 and less than or equal to 9 pi/8, the rotation factor is quantized to-1; when theta is more than or equal to 9 pi/8 and less than 11 pi/8, the twiddle factor is quantized to-1-j; when the theta is more than or equal to 11 pi/8 and less than 13 pi/8, the twiddle factor is quantized to-j; when theta is more than or equal to 13 pi/8 and less than 15 pi/8, the rotation factor is quantized to 1-j.

In fig. 9, the twiddle factor can also be approximated by 8 points in the following manner (manner 2): when theta is more than or equal to 0 and less than or equal to pi/8 and more than or equal to 15 pi/8 and less than 2 pi, the rotation factor is approximately 1; when the phi/8 is more than or equal to theta and less than 3 phi/8, the rotation factor is approximate toWhen theta is more than or equal to 3 pi/8 and less than 5 pi/8, the twiddle factor is approximately j; when theta is more than or equal to 5 pi/8 and less than 7 pi/8, the twiddle factor is approximatelyWhen theta is more than or equal to 7 pi/8 and less than or equal to 9 pi/8, the twiddle factor is approximately-1; when theta is more than or equal to 9 pi/8 and less than 11 pi/8, the twiddle factor is approximatelyWhen the theta is more than or equal to 11 pi/8 and less than 13 pi/8, the twiddle factor is approximate to-j; when theta is more than or equal to 13 pi/8 and less than 15 pi/8, the twiddle factor is approximately

As can be seen from fig. 9, the difference between quantization in mode 1 and approximation in mode 2 is only the coefficients in mode 2As can also be seen from fig. 9, the error resulting from quantization in the manner 1 is larger than the error resulting from approximation in the manner 2. However, since the method 2 requires multiplication by a coefficientThe decimal multiplication operation greatly increases the operation amount of the FPGA. Therefore, if the real-time performance of the system needs to be considered, the quantization mode of the mode 1 is selected; and if the interception probability of the system needs to be considered in an important mode, selecting an approximate mode of the mode 2.

According to the analysis process of 8-point twiddle factor quantization and 8-point twiddle factor approximation, 12-point twiddle factor quantization and 12-point twiddle factor approximation can be obtained. On the one hand, however, 12-point twiddle factor quantization produces much smaller errors than 8-point twiddle factor quantization and 8-point twiddle factor approximation; on the other hand, the multiplication required for the 12-point twiddle factor approximation is larger in amount and slower in operation speed. Therefore, the FFT operation is generally performed only by the 12-point twiddle factor quantization method. The quantized values of the 12-point twiddle factor are shown in fig. 10. As can be seen from FIG. 10, the radius of the unit circle is enlarged to 2 in the 12-point twiddle factor quantization mode, so that 12 quantized values are changed from 1, 1+0.5j, 0.5+ j, -0.5+ j, -1+0.5j, -1-0.5j, -0.5-j, 0.5-j, and 1-0.5j to 2, 2+ j, 1+2j, -1+2j, -2-j, -1-2j, 1-2j, and 2-j, respectively, so as to avoid decimal operation, and multiplication by 2 can be implemented by shifting one bit to the left, which is as simple as addition of 1 and subtraction of 1 in hardware, and improves the operation speed.

Single bit receivers perform similarly to DFT receivers except that the dynamic range of the dual signal is small, and thus improving the dynamic range of the dual signal is key to improving the performance of the single bit receiver. From the foregoing analysis, it can be seen that the main factor limiting the dynamic range is that the number of quantization bits of the input signal is too low, and therefore increasing the number of quantization bits of the input signal is the key to improve the dynamic range of the dual signal. The dynamic range of a single-bit receiver was simulated using a simple pulse signal with an input signal frequency of f 1-3 GHz and a simple pulse signal with a frequency of f 2-3.75 GHz as two simultaneously arriving signals, with an SNR of 2. The input signal is quantized by 1bit, 2bit and 4bit respectively, the twiddle factor is quantized by 4 points, 8 points and 12 points, and then the relation between the quantization digit and the dynamic range of the dual signal is obtained by simulation and is respectively shown in fig. 8-10.

From the analysis of fig. 8 to 10, it can be seen that: (1) after the twiddle factors are quantized by 4 points, 8 points and 12 points, the dynamic range is increased along with the increase of the quantization bit number, the dynamic range of 8-point quantization is 9dB greater than that of 4-point quantization, and the dynamic range of 12-point quantization is only 1dB greater than that of 8-point quantization. Therefore, the improvement of the dynamic range of the single-bit receiving system by further increasing the quantization point number of the twiddle factor is small. (2) When the quantization points of the same rotating factor are counted, when the input signal is quantized by 1bit, 2bit and 4bit respectively, the dynamic range when the quantization bit number is 2bit is greatly increased compared with the dynamic range when the quantization bit number is 1bit, and the dynamic range when the quantization bit number is 4bit and the dynamic range when the quantization bit number is 2bit are almost unchanged. Therefore, further increasing the number of quantization bits of the input signal provides little improvement in the dynamic range of a single-bit receiver system.

Meanwhile, as can be known from the AD sampling quantization theory, the quantization generates harmonics, and the lower the quantization bit number, the more harmonics are generated, so that the harmonics generated by the single-bit receiving system when the input signal is quantized by 2 bits and the twiddle factor is quantized by 8 points are smaller than those generated when the input signal is quantized by 1bit and the twiddle factor is quantized by 4 points.

According to the analysis and the comprehensive system interception probability and real-time requirement, the single-bit receiving system adopts a design method of input signal 2-bit quantization and twiddle factor 8-point quantization. The invention adopts a simple pulse signal with the frequency of an input signal f1 being 2GHz and a linear frequency modulation signal with the frequency of f2 being 2.375GHz and the bandwidth being 50MHz as two simultaneously arriving signals to carry out actual acquisition and analysis, and adopts short-time Fourier transform (STFT) to respectively obtain a time-frequency contour map when the input signal is quantized by 1bit and the twiddle factor by 4 points and a time-frequency contour map when the input signal is quantized by 2bit and the twiddle factor by 8 points under the same spectrum amplitude detection threshold, and the results are shown in fig. 14 and fig. 15. As can be seen from fig. 14, when the input signal is quantized by 1bit and the twiddle factor is quantized by 4 points, the two input signals cannot be well distinguished, the spectrum side lobe is too large due to too few quantization bits, and many false frequencies appear on the time-frequency contour diagram. In fig. 15, the spectrum sidelobe amplitude is reduced due to the increase of the quantization bits, and the false frequency can be removed by setting a threshold, so that the two signals can be better detected and identified. In fig. 14 and 15, the abscissa is normalized time and the ordinate is normalized frequency.

The intermediate frequency digital receiver/intelligence analysis unit is also one of the cores of the invention, and is used for converting an intermediate frequency analog signal into a digital signal and completing signal monitoring and parameter measurement in an intermediate frequency bandwidth. The method mainly comprises the steps of carrying out 12bit @3.2Gsps high-speed acquisition on intermediate-frequency signals output by a 2-18 GHz down conversion unit, obtaining high-speed ADC data, entering an FPGA for signal detection and parameter measurement, completing processing such as digital channelization and parameter measurement, carrying out full airspace frequency measurement by a single-bit receiver, carrying out signal sorting after PDW parameters are obtained, obtaining EDW data, transmitting the EDW data to display control equipment, and carrying out data storage and calculation processing.

The hardware of the intermediate frequency receiver mainly comprises 1 digital receiver/information analysis unit, 1 signal sorting and main control module and 1 data recording board, as shown in fig. 7.

The intermediate frequency digital receiver receives intermediate frequency 4-path direction-finding signals output by the down-conversion unit and 1-path pressure side lobe signals generated according to the single-bit receiver, completes the functions of acquisition, pulse detection, parameter measurement and direction finding of the intermediate frequency signals, sends generated PDW to the signal sorting and main control module, and sends AD data and PDW data to the storage module. The digital receiver simultaneously generates bandwidth signals with selectable 50MHz and 400MHz according to the information analysis command sent by the display control module through down conversion, and the information analysis unit performs corresponding analysis according to the display control command. The 400MHz bandwidth signal is used for inter-pulse characteristics (conventional pulse, multiple frequency spread, multiple frequency jitter, frequency agility radar, frequency diversity, etc.) and intra-pulse characteristic analysis (linear frequency modulation, non-linear frequency modulation, two-phase code, four-phase code, frequency coding, etc.) of the multi-part signal in the bandwidth; the 50MHz bandwidth signal is used for fingerprint feature analysis of a certain signal in the bandwidth, such as precision intra-pulse modulation type analysis, spectrum point number, spectrum amplitude variance, envelope rising edge point number, envelope falling edge point number, etc.).

The signal sorting and main control module sorts PDW (pulse description word) generated by the digital receiver to obtain radiation source description word (EDW) data and reports the data to the display and control module; the database is used for completing the identification of the signals and giving an identification result; and the signals detected by each frequency band are subjected to fusion processing, so that multiple batches of displays of the same batch of targets are reduced, and the like.

The storage module receives the AD sampling data generated by the digital receiver, records and plays back the AD sampling data, and offline analysis is facilitated. The hardware system of the storage module mainly comprises a CPU, a coprocessor, a high-speed serial exchange chip, a storage array, a gigabit network, an optical module interface and the like. The module is divided into two parts: a carrier card and additional daughter cards, the daughter cards providing 4TB capacity. Meanwhile, the method can be expanded to 10TB by using FLASH particles with larger capacity according to actual requirements.

The time-frequency analysis is one of the important judgment bases for identifying the radar signal modulation type. The invention is inspired by the analysis of the single-bit receiver FFT unit, improves and designs the 400MHz bandwidth signal processing algorithm of the information analysis unit, improves the signal processing speed on the premise of not influencing the analysis effect, and leads the information analysis unit to better meet the requirement of on-site real-time monitoring.

The digital receiver of the invention adopts a high-speed analog-digital converter ADC12DJ3200 of TI company to carry out high-speed sampling on the intermediate frequency signal output by the down-conversion unit, and the ADC12DJ3200 is 12bit and 3.2 Gsps. In the intelligence analysis unit, for a 400MHz bandwidth signal obtained by down-converting a sampling signal, at least 8 data (3.2/0.4-8) are collected in each cycle, that is, at least 4 data are sampled in a half cycle. Thus, the present invention quantizes the signal to be analyzed to-3, -1, and 3, thus avoiding fractional multiplication operations while performing an 8-point approximation of the twiddle factor. The 8-point approximation is used instead of 8-point quantization, mainly because the real-time requirement of 400MHz intelligence analysis is low compared to that of a single-bit receiver, and thus certain real-time is sacrificed to ensure the analysis accuracy.

The actual analysis is still performed using as the two simultaneously arriving signals a simple pulse signal with an input signal frequency of f 1-2 GHz and a chirp signal with a frequency of f 2-2.375 GHz and a bandwidth of 50 MHz. Fig. 16 is a time-frequency contour plot obtained using a conventional STFT algorithm, and fig. 17 is a time-frequency contour plot obtained using a post-quantization STFT algorithm. As can be seen from fig. 16 and 17, under the same spectrum amplitude detection threshold, two signals can be identified, but the bandwidth of the chirp signal in the quantized STFT calculation result is slightly increased. This is acceptable considering that the 400MHz bandwidth intelligence analysis is for real-time monitoring rather than accurate fingerprinting.

The total noise figure NF of the radio frequency front end is:

NF₁is the noise figure of the first stage circuit, NF₂Is the noise figure of the second stage circuit, NF₃Is the noise figure of the third stage circuit, NF_nIs the noise coefficient of the nth stage circuit, n is the stage number of the cascade circuit of the radio frequency front end, G₁Is the gain of the first stage circuit, G₂Is the gain of the second stage circuit, G_n-1Is the gain of the (n-1) th stage circuit;

the radio frequency front end also comprises a detection logarithmic video amplifier. Dynamic range is one of the other important indicators of the rf receive front-end of a single-bit receiver. The radio frequency receiving front end of the invention adopts a large dynamic Detection Logarithmic Video Amplifier (DLVA), thereby ensuring the large dynamic range of the radio frequency receiving front end. In a sensitivity state, a signal formed after an input pulse signal passes through the large dynamic DLVA is a minimum detectable signal of the large dynamic DLVA by setting a gain level of the amplifier, and a radio frequency signal input into the large dynamic DLVA is a maximum detectable signal of the large dynamic DLVA by setting the output of the amplifier. Therefore, the radio frequency signals entering the large dynamic DLVA in the full input dynamic range are theoretically ensured to be in the dynamic range of the large dynamic DLVA, and the whole dynamic range of the single-bit receiving system is improved.

The present invention is not limited to the above-mentioned embodiments, and based on the technical solutions disclosed in the present invention, those skilled in the art can make some substitutions and modifications to some technical features without creative efforts according to the disclosed technical contents, and these substitutions and modifications are all within the protection scope of the present invention.