阅读说明：本技术 一种倒装电极及其制作方法 (Inverted electrode and manufacturing method thereof ) 是由 邓高杰 林武 李文浩 陈荣炎 于 2020-12-18 设计创作，主要内容包括：一种倒装电极及其制作方法,其中方法包括如下步骤,制作第1层Cr层；制作第2层AlCu合金层；交替蒸镀Ti层和Pt层各3层,形成第3-8层的TiPt复合层；制作第9层Au层；蒸镀第10Ti层及第11层Pt层；制作第12层Au层；制作第13层Ti层。上述技术方案,可以改善倒装电极芯片在顶针测试实验中的性能表现,并能够降低使用成本。(A flip-chip electrode and its preparation method, wherein the method includes the following step, make the layer Cr of layer 1; manufacturing a 2 nd AlCu alloy layer; alternately evaporating 3 Ti layers and 3 Pt layers to form a TiPt composite layer of the 3 rd to 8 th layers; manufacturing a 9 th Au layer; evaporating a 10 th Ti layer and an 11 th Pt layer; manufacturing a 12 th Au layer; the 13 th Ti layer was produced. By the technical scheme, the performance of the flip electrode chip in the thimble test experiment can be improved, and the use cost can be reduced.)

1. A manufacturing method of a flip electrode is characterized by comprising the following steps,

manufacturing a 1 st Cr layer;

manufacturing a 2 nd AlCu alloy layer;

alternately evaporating 3 Ti layers and 3 Pt layers to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer;

evaporating a 10 th Ti layer and an 11 th Pt layer;

manufacturing a 12 th Au layer;

the 13 th Ti layer was produced.

2. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S;

manufacturing a 2 nd AlCu alloy layer, and coating at a plating rate of 5A/S;

alternately evaporating 3 Ti layers and 3 Pt layers, plating Ti layers at the plating rate of 1A/S, and plating Pt layers at the plating rate of 1A/S to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;

evaporating a 10 th Ti layer and an 11 th Pt layer, plating a Ti layer at a plating rate of 1A/S, and plating a Pt layer at a plating rate of 1A/S;

manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;

a13 th Ti layer was formed, and the Ti layer was plated at a plating rate of 1A/S.

3. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S;

manufacturing a 2 nd AlCu alloy layer, and coating at a plating rate of 5A/S;

alternately evaporating 3 Ti layers and 3 Pt layers, plating Ti layers at the plating rate of 2A/S, and plating Pt layers at the plating rate of 1A/S to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;

evaporating a 10 th Ti layer and an 11 th Pt layer, plating a Ti layer at a plating rate of 2A/S, and plating a Pt layer at a plating rate of 1A/S;

manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;

a13 th Ti layer was formed, and the Ti layer was plated at a plating rate of 2A/S.

4. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,

manufacturing a 1 st Cr layer, wherein the thickness of a plated film is 30A;

manufacturing a 2 nd AlCu alloy layer, wherein the coating thickness is 1500A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein the thickness of each Ti layer is 600A, and the thickness of each Pt layer is 500A, so as to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer, wherein the thickness of a plated film is 11000A;

evaporating a 10 th Ti layer with the coating thickness of 1500A and evaporating an 11 th Pt layer with the coating thickness of 700A;

manufacturing a 12 th Au layer, wherein the thickness of a plated film is 1000A;

and (5) manufacturing a 13 th Ti layer, wherein the thickness of the plated film is 500A.

5. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S, wherein the coating thickness is 30A;

manufacturing a 2 nd AlCu alloy layer, and plating at a plating rate of 5A/S, wherein the plating thickness is 1500A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein each Ti layer is 600A in thickness, each Ti layer is firstly plated at 300A at a plating rate of 1A/S and then plated at 300A at a plating rate of 2A/S, and each Pt layer is 500A in thickness to form a 3-8 th TiPt composite layer; each layer of Ti is 600A in thickness, each layer of Pt is 500A in thickness, and a TiPt composite layer of 3-8 layers is formed;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 11000A;

evaporating a 10 th Ti layer, performing Ti layer coating at a coating rate of 1A/S, wherein the coating thickness is 1500A, evaporating an 11 th Pt layer, and performing Pt layer coating at a coating rate of 1A/S, wherein the coating thickness is 700A;

manufacturing a 12 th Au layer, and plating a film with the plating rate of 10A/S, wherein the thickness of the plated film is 1000A;

and (3) preparing a 13 th Ti layer, and plating the Ti layer at a plating rate of 2A/S to obtain a plating film with the thickness of 500A.

6. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S, wherein the coating thickness is 27A;

manufacturing a 2 nd AlCu alloy layer, and coating at a coating rate of 5A/S, wherein the coating thickness is 1350A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein each Ti layer is 540A thick, each Ti layer is firstly coated with 270A at a coating rate of 1A/S, then coated with 270A at a coating rate of 2A/S, and each Pt layer is 450A thick to form a 3-8 TiPt composite layer; each layer of Ti is 540A in thickness, and each layer of Pt is 450A in thickness, so that a TiPt composite layer of 3-8 layers is formed;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 9900A;

evaporating a 10 th Ti layer, performing Ti layer coating at a coating rate of 1A/S, wherein the coating thickness is 1350A, evaporating an 11 th Pt layer, and performing Pt layer coating at a coating rate of 1A/S, wherein the coating thickness is 630A;

manufacturing a 12 th Au layer, and plating at a plating rate of 10A/S, wherein the plating thickness is 900A;

and (3) preparing a 13 th Ti layer, and plating the Ti layer at a plating rate of 2A/S to obtain a plated film with the thickness of 450A.

7. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S, wherein the coating thickness is 33A;

manufacturing a 2 nd AlCu alloy layer, and plating a film at a plating rate of 5A/S, wherein the thickness of the plated film is 1650A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein each Ti layer is 660A in thickness, each Ti layer is subjected to 330A film plating at the plating rate of 1A/S, then the 330A film plating is performed at the plating rate of 2A/S, and each Pt layer is 500A in thickness to form a 3-8 TiPt composite layer; each layer of Ti is 660A in thickness, and each layer of Pt is 550A in thickness, so that a TiPt composite layer of the 3 rd to 8 th layers is formed;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 12100A;

evaporating a 10 th Ti layer, plating a Ti layer at a plating rate of 1A/S to obtain a plated film with a thickness of 1650A, evaporating an 11 th Pt layer, plating a Pt layer at a plating rate of 1A/S to obtain a plated film with a thickness of 770A;

manufacturing a 12 th Au layer, and plating a film with the plating rate of 10A/S, wherein the thickness of the plated film is 1100A;

and (3) preparing a 13 th Ti layer, and plating the Ti layer at a plating rate of 2A/S to obtain a plated film with the thickness of 550A.

8. A flip chip electrode made according to the method of any one of claims 1-7.

Technical Field

The invention relates to a flip electrode design, in particular to a manufacturing method for improving the performance of a flip electrode.

Background

Gallium nitride based Light Emitting Diodes (LEDs) have the advantages of low functional loss, long lifetime, good reliability, etc. and are widely used in the fields of signal lamps, backlight displays, automotive lighting, indoor lighting, etc. With the popularization and application of high-power and high-luminous-efficiency LEDs, flip-Chip products (Filp chips) have wider application market and higher application value. In the current chip-scale packaging processing technology, a method of puncturing a blue film by a thimble is commonly used in the separation of a processing chip and the blue film by traditional chip-mounting packaging equipment such as an LED die bonder and a chip mounter; the flip chip product designed by the product needs to be subjected to the thimble performance verification, and flip chips introduced in the prior art such as CN 201320549532.1 and CN 201320550892.3 have the problem of high electrode consumption.

Disclosure of Invention

Therefore, it is necessary to provide a method capable of improving the performance of the chip anti-thimble test of the flip-chip electrode.

A method for manufacturing a flip-chip electrode comprises the following steps,

manufacturing a 1 st Cr layer;

manufacturing a 2 nd AlCu alloy layer;

alternately evaporating 3 Ti layers and 3 Pt layers to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer;

evaporating a 10 th Ti layer and an 11 th Pt layer;

manufacturing a 12 th Au layer;

the 13 th Ti layer was produced.

In particular, it includes the steps of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S;

manufacturing a 2 nd AlCu alloy layer, and coating at a plating rate of 5A/S;

alternately evaporating 3 Ti layers and 3 Pt layers, plating Ti layers at the plating rate of 1A/S, and plating Pt layers at the plating rate of 1A/S to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;

evaporating a 10 th Ti layer and an 11 th Pt layer, plating a Ti layer at a plating rate of 1A/S, and plating a Pt layer at a plating rate of 1A/S;

manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;

a13 th Ti layer was formed, and the Ti layer was plated at a plating rate of 1A/S.

In particular, it includes the steps of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S;

manufacturing a 2 nd AlCu alloy layer, and coating at a plating rate of 5A/S;

alternately evaporating 3 Ti layers and 3 Pt layers, plating Ti layers at the plating rate of 2A/S, and plating Pt layers at the plating rate of 1A/S to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;

evaporating a 10 th Ti layer and an 11 th Pt layer, plating a Ti layer at a plating rate of 2A/S, and plating a Pt layer at a plating rate of 1A/S;

manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;

a13 th Ti layer was formed, and the Ti layer was plated at a plating rate of 2A/S.

In particular, it includes the steps of,

manufacturing a 1 st Cr layer, wherein the thickness of a plated film is 30A;

manufacturing a 2 nd AlCu alloy layer, wherein the coating thickness is 1500A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein the thickness of each Ti layer is 600A, and the thickness of each Pt layer is 500A, so as to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer, wherein the thickness of a plated film is 11000A;

evaporating a 10 th Ti layer with the coating thickness of 1500A and evaporating an 11 th Pt layer with the coating thickness of 700A;

manufacturing a 12 th Au layer, wherein the thickness of a plated film is 1000A;

and (5) manufacturing a 13 th Ti layer, wherein the thickness of the plated film is 500A.

Specifically, the method comprises the steps of manufacturing a 1 st Cr layer, and plating a film on the surface of a chip at a plating rate of 0.2A/S, wherein the thickness of the plated film is 30A;

manufacturing a 2 nd AlCu alloy layer, and plating at a plating rate of 5A/S, wherein the plating thickness is 1500A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein each Ti layer is 600A in thickness, each Ti layer is firstly plated at 300A at a plating rate of 1A/S and then plated at 300A at a plating rate of 2A/S, and each Pt layer is 500A in thickness to form a 3-8 th TiPt composite layer; each layer of Ti is 600A in thickness, each layer of Pt is 500A in thickness, and a TiPt composite layer of 3-8 layers is formed;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 11000A;

evaporating a 10 th Ti layer, performing Ti layer coating at a coating rate of 1A/S, wherein the coating thickness is 1500A, evaporating an 11 th Pt layer, and performing Pt layer coating at a coating rate of 1A/S, wherein the coating thickness is 700A;

manufacturing a 12 th Au layer, and plating a film with the plating rate of 10A/S, wherein the thickness of the plated film is 1000A;

and (3) preparing a 13 th Ti layer, and plating the Ti layer at a plating rate of 2A/S to obtain a plating film with the thickness of 500A.

By the technical scheme, the performance of the flip electrode chip in the thimble test experiment can be improved, and the use cost can be reduced.

Drawings

FIG. 1 is a schematic diagram of a flip chip electrode according to an embodiment;

FIG. 2 is a schematic diagram illustrating a batch result of a thimble experiment according to an embodiment;

FIG. 3 is a diagram illustrating the results of a small batch repeat experiment according to an embodiment.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

A method for manufacturing a flip-chip electrode comprises the following steps,

manufacturing a 1 st Cr layer; the Cr layer is used for realizing ohmic contact and improving the adhesion with a substrate,

manufacturing a 2 nd AlCu alloy layer; the AlCu alloy layer is used for increasing the reflectivity and the reliability of the chip.

Alternately evaporating 3 Ti layers and 3 Pt layers to form a TiPt composite layer of the 3 rd to 8 th layers; wherein the Ti layer can increase the adhesion between metal layers, and the Pt layer is used for improving the aging capability.

Manufacturing a 9 th Au layer; the Au layer can enhance the electric conduction capability,

evaporating a 10 th Ti layer and an 11 th Pt layer; the Ti layer can increase the adhesion between metal layers, and the Pt layer is used to improve the aging capability.

Manufacturing a 12 th Au layer; the Au layer can enhance the electric conduction capability,

manufacturing a 13 th Ti layer; the Ti layer can increase adhesion to the chip DBR layer.

As can be seen from the figure 1, the layers are arranged in a mode of 1-13 layers from bottom to top, and the Ti layer cladding is realized on the most surface through the arrangement design, so that the top layer of the electrode and the DBR layer of the chip can be combined more tightly, and the strength of the thimble resistance experiment of the chip is improved. Meanwhile, the design of adding the TiPt layer between the two Au layers reduces the thickness of the Au layer while ensuring the structural strength, thereby reducing the use of Au and further reducing the overall design cost.

In the results of the thimble experiment batch shown in fig. 2, it can be seen that the results of the thimble experiment on the chip manufactured by the above scheme are that the serious breakage is 12.5%, the slight breakage is 48.75%, and the non-breakage rate is 38.75%. Compared with the conventional method, the method has the advantage that the lossless rate of 6.75 is greatly improved. In the small batch repeat validation results shown in fig. 3, the severe damage was 2.5%, the slight damage was 50%, and the non-damage rate was 47.5%.

In particular, it includes the steps of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S;

manufacturing a 2 nd AlCu alloy layer, and coating at a plating rate of 5A/S;

alternately evaporating 3 Ti layers and 3 Pt layers, plating Ti layers at the plating rate of 1A/S, and plating Pt layers at the plating rate of 1A/S to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;

evaporating a 10 th Ti layer and an 11 th Pt layer, plating a Ti layer at a plating rate of 1A/S, and plating a Pt layer at a plating rate of 1A/S;

manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;

a13 th Ti layer was formed, and the Ti layer was plated at a plating rate of 1A/S.

Through the setting of the plating rate, the inside of each film layer is more compact, the combination between the film layers is more compact while the performance is ensured, and therefore the experimental performance of the ejector pin is improved.

Specifically, the method comprises the steps of manufacturing a 1 st Cr layer, and coating the surface of a chip at a coating rate of 0.2A/S;

manufacturing a 2 nd AlCu alloy layer, and coating at a plating rate of 5A/S;

alternately evaporating 3 Ti layers and 3 Pt layers, plating Ti layers at the plating rate of 2A/S, and plating Pt layers at the plating rate of 1A/S to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;

evaporating a 10 th Ti layer and an 11 th Pt layer, plating a Ti layer at a plating rate of 2A/S, and plating a Pt layer at a plating rate of 1A/S;

manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;

a13 th Ti layer was formed, and the Ti layer was plated at a plating rate of 2A/S.

Through the setting of different plating rates, can let each rete inside compacter, can let the combination between each rete more inseparable when guaranteeing the performance to promote thimble experimental performance.

Manufacturing a 1 st Cr layer, wherein the thickness of a plated film is 30A;

manufacturing a 2 nd AlCu alloy layer, wherein the coating thickness is 1500A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein the thickness of each Ti layer is 600A, and the thickness of each Pt layer is 500A, so as to form a TiPt composite layer of the 3 rd to 8 th layers;

manufacturing a 9 th Au layer, wherein the thickness of a plated film is 11000A;

evaporating a 10 th Ti layer with the coating thickness of 1500A and evaporating an 11 th Pt layer with the coating thickness of 700A;

manufacturing a 12 th Au layer, wherein the thickness of a plated film is 1000A;

and (5) manufacturing a 13 th Ti layer, wherein the thickness of the plated film is 500A. The thickness scheme allows for a 15% error adjustment, and the overall performance of the electrode can be better played through the thickness design of each layer.

In other embodiments, the method includes the step of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S, wherein the coating thickness is 30A;

manufacturing a 2 nd AlCu alloy layer, and plating at a plating rate of 5A/S, wherein the plating thickness is 1500A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein each Ti layer is 600A in thickness, each Ti layer is firstly plated at 300A at a plating rate of 1A/S and then plated at 300A at a plating rate of 2A/S, and each Pt layer is 500A in thickness to form a 3-8 th TiPt composite layer; each layer of Ti is 600A in thickness, each layer of Pt is 500A in thickness, and a TiPt composite layer of 3-8 layers is formed;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 11000A;

evaporating a 10 th Ti layer, performing Ti layer coating at a coating rate of 1A/S, wherein the coating thickness is 1500A, evaporating an 11 th Pt layer, and performing Pt layer coating at a coating rate of 1A/S, wherein the coating thickness is 700A;

manufacturing a 12 th Au layer, and plating a film with the plating rate of 10A/S, wherein the thickness of the plated film is 1000A;

and (3) preparing a 13 th Ti layer, and plating the Ti layer at a plating rate of 2A/S to obtain a plating film with the thickness of 500A.

According to the scheme, the Ti film is formed at different rates in the composite layer of the Ti layer and the Pt layer, so that the formed Ti is more compact, the performance is better, and the thimble resistance experiment performance is stronger.

In still other further embodiments, a 1 st Cr layer is prepared, and the surface of the chip is plated with a plating rate of 0.2A/S, wherein the plating thickness is 27A;

manufacturing a 2 nd AlCu alloy layer, and coating at a coating rate of 5A/S, wherein the coating thickness is 1350A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein each Ti layer is 540A thick, each Ti layer is firstly coated with 270A at a coating rate of 1A/S, then coated with 270A at a coating rate of 2A/S, and each Pt layer is 450A thick to form a 3-8 TiPt composite layer; each layer of Ti is 540A in thickness, and each layer of Pt is 450A in thickness, so that a TiPt composite layer of 3-8 layers is formed;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 9900A;

evaporating a 10 th Ti layer, performing Ti layer coating at a coating rate of 1A/S, wherein the coating thickness is 1350A, evaporating an 11 th Pt layer, and performing Pt layer coating at a coating rate of 1A/S, wherein the coating thickness is 630A;

manufacturing a 12 th Au layer, and plating at a plating rate of 10A/S, wherein the plating thickness is 900A;

and (3) preparing a 13 th Ti layer, and plating the Ti layer at a plating rate of 2A/S to obtain a plated film with the thickness of 450A.

According to the scheme, the Ti film is formed at different rates in the composite layer of the Ti layer and the Pt layer, so that the formed Ti is more compact, the performance is better, and the thimble resistance experiment performance is stronger.

In other embodiments, the method includes the step of,

manufacturing a 1 st Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S, wherein the coating thickness is 33A;

manufacturing a 2 nd AlCu alloy layer, and plating a film at a plating rate of 5A/S, wherein the thickness of the plated film is 1650A;

alternately evaporating 3 Ti layers and 3 Pt layers, wherein each Ti layer is 660A in thickness, each Ti layer is subjected to 330A film plating at the plating rate of 1A/S, then the 330A film plating is performed at the plating rate of 2A/S, and each Pt layer is 500A in thickness to form a 3-8 TiPt composite layer; each layer of Ti is 660A in thickness, and each layer of Pt is 550A in thickness, so that a TiPt composite layer of the 3 rd to 8 th layers is formed;

manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 12100A;

evaporating a 10 th Ti layer, plating a Ti layer at a plating rate of 1A/S to obtain a plated film with a thickness of 1650A, evaporating an 11 th Pt layer, plating a Pt layer at a plating rate of 1A/S to obtain a plated film with a thickness of 770A;

manufacturing a 12 th Au layer, and plating a film with the plating rate of 10A/S, wherein the thickness of the plated film is 1100A;

and (3) preparing a 13 th Ti layer, and plating the Ti layer at a plating rate of 2A/S to obtain a plated film with the thickness of 550A.

According to the scheme, the Ti film is formed at different rates in the composite layer of the Ti layer and the Pt layer, so that the formed Ti is more compact, the performance is better, and the thimble resistance experiment performance is stronger.

It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present patent.