阅读说明：本技术 中央运算装置、gpgpu、包含存储器的三维层叠集成电路的利用制冷剂的冷却方式、使用该冷却方式的三维层叠集成电路、以及供电方式 (Central processing unit, GPGPU, cooling method using refrigerant for three-dimensional stacked integrated circuit including memory, three-dimensional stacked integrated circuit using the cooling metho) 是由 筒井多圭志 今仲滋宜 古谷智彦 于 2019-01-24 设计创作，主要内容包括：本发明的三维层叠集成电路,在三维层叠集成电路各自的集成电路之间以及最下面的集成电路下方分别具备内插器；多个所述内插器分别设置有制冷剂的移动路径；设置于多个所述内插器的多个所述制冷剂的移动路径相互连接。或者,利用浸液构成,并利用设置至内插器的端部为止的凹槽使制冷剂在各层与外部交流,从而简化了系统的结构。该情况下,不需要层方向的供制冷剂流通的回路。(The three-dimensional stacked integrated circuit of the present invention is provided with interposers between the integrated circuits of the three-dimensional stacked integrated circuits and below the lowest integrated circuit; a plurality of the interposers are respectively provided with a moving path of a refrigerant; the paths of the refrigerant flowing through the plurality of interposers are connected to each other. Alternatively, the system is simplified in structure by being constituted by a liquid immersion material and communicating the refrigerant to the outside at each layer by a groove provided up to the end of the interposer. In this case, a circuit through which the refrigerant flows in the layer direction is not necessary.)

1. A three-dimensional stacked integrated circuit is provided with a plurality of interposers between respective integrated circuits of the three-dimensional stacked integrated circuit and below a lowermost integrated circuit, the plurality of interposers are provided with respective paths for moving a refrigerant, and the paths for moving the refrigerant provided in the plurality of interposers are connected to each other.

2. The three-dimensional stacked integrated circuit of claim 1,

a plurality of the interpolators have:

a first interposer provided with a groove; and

a second interposer disposed between a surface of the first interposer where the groove is provided and a lower surface of the integrated circuit, the second interposer sealing the groove provided in the first interposer,

a moving path of the refrigerant is formed by a space sandwiched between the groove formed at each of the first interposers and the second interposer and holes passing through the integrated circuit, the first interposers, and the second interposers;

the refrigerant flows in a space formed by a space sandwiched between the groove and the second interposer and a hole penetrating the plurality of integrated circuits, the first interposer, and the second interposer.

3. The three-dimensional stacked integrated circuit of claim 1,

a moving path of the refrigerant is formed by heat pipes extending in grooves sandwiched between grooves formed respectively in the plurality of interposers and the integrated circuits;

the movement path is a path through which the heat pipe disposed in the recess passes outside the three-dimensional stacked integrated circuit to reach the heat pipe of the interposer of the next layer, and the refrigerant flows through the movement path.

4. The three-dimensional stacked integrated circuit of claim 3,

the grooves formed in at least one of the plurality of interposers include a first groove and a second groove formed to an edge of the interposer;

the heat pipe has:

a first portion disposed in the first recess;

a second portion disposed in the second recess; and

a third portion that is bent at an outside of the interposer and connects the first portion and the second portion.

5. The three-dimensional stacked integrated circuit of any one of claims 2 to 4,

in the plurality of interposers, the grooves inscribed in adjacent interposers are substantially orthogonal to each other between adjacent interposers.

6. The three-dimensional stacked integrated circuit of any one of claims 1 to 5,

the integrated circuits are connected through vias.

7. The three-dimensional stacked integrated circuit of any one of claims 1 to 6,

the plurality of integrated circuit layers and the interposer layer formed with the groove are bonded or pressure-bonded with an adhesive including a die adhesive or an adhesive tape.

8. The three-dimensional stacked integrated circuit of any one of claims 1 to 7,

the three-dimensional stacked integrated circuit includes:

a substrate;

an HBM (high bandwidth memory) provided to the substrate; and

a plurality of computing devices disposed on the substrate, a plurality of general purpose GPUs, and a three-dimensional array of general purpose DSP devices,

the substrate is disposed between the plurality of arithmetic devices, the plurality of general purpose GPUs, and the plurality of general purpose DSP devices, and the HBM, or the HBM is disposed between the plurality of arithmetic devices, the plurality of general purpose GPUs, and the plurality of general purpose DSP devices, and the substrate.

9. The three-dimensional stacked integrated circuit of any one of claims 1 to 8,

the cooling pipe is not used, and a groove through which a refrigerant flows is formed in a copper or aluminum plate or a silicon substrate, and the upper and lower layers are connected by a hole in the vertical direction to form a pipe line.

10. The three-dimensional stacked integrated circuit of claim 1,

by forming longitudinal and transverse grooves through which a refrigerant flows on a copper, aluminum, or silicon substrate without using a cooling pipe, and opening the grooves to extend to the end of the substrate, the refrigerant is allowed to penetrate into and be released from each layer from the peripheral surface of the semiconductor by immersion liquid to cool the inside of the semiconductor, and there is no need to form a pipe through which the refrigerant flows in the layer direction,

the vertical and horizontal grooves avoid the portions constituting the TSVs,

by circulating the refrigerant to the outside at each layer by using the grooves provided up to the end of the interposer, the structure of the cooling system is simplified,

in the case where a layer of copper or aluminum is inserted as a member constituting the recess, it is necessary to fill the hole portion of the copper or aluminum plate constituting the portion of the TSV in the vertical direction with a silicon substrate.

11. The three-dimensional stacked integrated circuit of claim 9 or 10,

grooves for passing the refrigerant are formed by etching, engraving, cutting by a computer NC, or punching grooves in a longitudinal and transverse direction on the substrate layer,

the groove for passing the refrigerant is V-shaped, U-shaped or コ -shaped.

12. The three-dimensional stacked integrated circuit according to any one of claims 1 to 11,

in the case of immersion liquid, only the inlet is provided in one direction or in an open type in a vertical and horizontal direction, and the discharge port is opened in the liquid, so that cavitation is prevented by applying positive pressure from the inlet.

13. A three-dimensional stacked integrated circuit, wherein,

mounting an independent semiconductor in an independent BGA or semiconductor package based on the same, wherein the independent semiconductor package can be vertically stacked in a vertical direction by providing a geometric-shaped pad for connecting terminals of the BGA on an upper surface of the package; cooling by immersion using gaps of ball grids of the stacked BGA terminals or the like; the semiconductor packaging and cooling method, the ball grid of BGA is installed on the lower part of the semiconductor, the welding pad of the geometry shape contacting with BGA is installed on the upper surface, and the presupposition is immersion liquid; stacking the stacked integrated circuits designed as described above one on top of another to form a three-dimensional stacked integrated circuit on the premise of an immersion liquid;

each semiconductor package is stacked up and down and kept pressed to prevent dislocation; the holding mechanism may have a guide to prevent the stacked semiconductors from being misaligned; the coolant flows through the gaps of the ball grid of the BGA terminal or the like; in addition, the cooling liquid does not flow between the interposers, and each semiconductor is formed by the current semiconductor package except that a geometrical welding pad is added on the upper surface, so the difficulty in manufacturing is not increased; since the data path corresponds to the thickness in the vertical direction including the contact, high-speed interconnection can be realized, and the essence of the present invention can be realized without changing the conventional semiconductor manufacturing method.

14. The three-dimensional stacked integrated circuit of claim 13,

the pads are contacted by springs.

15. The method for cooling a three-dimensional semiconductor device according to claim 13 or 14,

the vertical connection of the semiconductors stacked via the pads is used as a vertical bus line, thereby speeding up the operation of the stacked memory and processor.

16. The three-dimensional stacked integrated circuit of any one of claims 1 to 15,

not only the CPU, GPGPU, and the computation portion of the central processing unit for virtual currency mining, but also the HBM is mounted on the three-dimensional semiconductor of the cooling method of this embodiment, or a memory layer is inserted between layers.

17. An apparatus and method for constructing an arithmetic device, wherein,

in the case of sandwiching the memory layer according to claim 16, only the operation layer and the memory layer need be connected by the TSV, and therefore, stray capacitance of the memory bus line is minimized, and ultra-high speed operation is possible.

18. The three-dimensional stacked integrated circuit of any one of claims 1 to 17,

as a member which not only contacts with the BGA but also prevents the three-dimensional cooling semiconductor from being decomposed by the pressure of the cavitation, metal plates including aluminum plates are prepared on the upper and lower sides (the back surface of the PCB and the back surface of the semiconductor) and are clamped at four or more points by clamps,

the aluminum plate and the PCB sandwich a member including an insulator therebetween.

19. The three-dimensional stacked integrated circuit of any one of claims 1 to 18,

by providing TSVs for redundant data paths at a plurality of locations and overlapping a plurality of processor arrays including defective locations, defective locations may be present in the data paths, and the processor elements may be used so that the defective locations gradually increase in three-dimensional mounting of a fine semiconductor that initially includes defective locations.

20. The three-dimensional stacked integrated circuit of any one of claims 1 to 19,

the operation is carried out at a temperature at which cavitation is not caused by the immersion liquid.

21. The three-dimensional stacked integrated circuit of any one of claims 1 to 20,

in spite of the immersion liquid, cavitation is prevented by mounting a connector on either side of the semiconductor and injecting the solution under a positive pressure by means of a pump.

22. The three-dimensional stacked integrated circuit of any one of claims 1 to 21,

an acoustic sensor is provided, and the clock frequency is controlled using the output of the acoustic sensor to prevent cavitation from occurring and to operate the acoustic sensor.

23. The three-dimensional stacked integrated circuit of claim 22,

as a means for preventing the decomposition of the three-dimensional cooling semiconductor for preventing the cavitation, a metal plate including an aluminum plate is prepared on the upper and lower sides (the back surface of the PCB and the back surface of the semiconductor), and is clamped at four or more points by a clamp,

the aluminum plate and the PCB sandwich a member including an insulator therebetween.

24. The three-dimensional stacked integrated circuit of claim 23,

the whistle generated by the boiling of the refrigerant is detected by the sound sensor, and the frequency is controlled within a range that does not cause the whistle.

25. The three-dimensional stacked integrated circuit of claim 24,

the depth and length of the groove are changed to prevent resonance, so as to prevent whistling resonance,

in this case, in order to change the length of the groove, the semiconductor is trapezoidal,

in the case where the longitudinal and lateral grooves are present, the trapezoidal shape is irregular in order to prevent the longitudinal and lateral resonances from occurring.

26. The semiconductor of claim 13,

electrodes are provided at the corners or edges or both of a semiconductor formed by stacking BGA packages, and electrodes in the shape of metal bars are brought into contact with the electrodes to supply GND and a power supply potential which have low impedance and are stable,

the metal rod-like electrode may have a structure in which a capacitor is provided between both the positive electrode and the negative electrode.

27. The semiconductor of claim 26,

in order to press the stacked semiconductors and supply a stable potential with low impedance, a cover may be provided which has a function of connecting the electrodes to each other,

for pressing the semiconductor, the cover may also be provided with a spring or the like,

in addition, the cover may have a path for connecting the respective potentials of the positive electrode and the negative electrode to each other.

28. The semiconductor of claim 10, 11, or 12,

the substrate of the first layer may also be a typical FC-BGA substrate without a recess,

the semiconductor of the first layer is connected with the interposer of the first layer through the TSV,

between the FC-BGA substrate of the first layer and the semiconductor of the first layer, in order to prevent water from entering into the FC pad between the FC pad and the semiconductor of the first layer, the periphery of the FC pad is reinforced with underfill or the like.

29. The semiconductor of claim 28,

the laminated portion of the substrate and the semiconductor chip is reinforced with an underfill or the like to prevent the FC pad from being impregnated with a refrigerant.

30. The semiconductor of claims 10, 11, 12, 28, and 29, wherein,

the grooves through which the refrigerant passes and the regions having the FC pads of the TSVs do not necessarily have to be present alternately with each other, and since the regions constituting the semiconductor disappear if the TSV regions in the vertical direction are excessive, the regions having the FC pads of the TSVs may also be a limited number,

the groove and the recess may also be adjacent.

31. The semiconductor of claims 10, 11, 12, 28, 29, and 30,

as in claims 26 and 27, electrodes are provided at corners or edges of a semiconductor or both, and a metal rod-shaped electrode is brought into contact with the electrodes to supply GND having low impedance and stable power supply potential, and the metal rod-shaped electrode may have a structure having a capacitor between both a positive electrode and a negative electrode; in order to press the stacked semiconductors and supply a stable potential with low impedance, a cover may be provided that has a function of connecting the electrodes to each other; the cover may also be provided with a spring or the like for pressing the semiconductor; in addition, the cover may have a path for connecting the respective potentials of the positive electrode and the negative electrode to each other.

32. The semiconductor of claim 13,

a package having pads on the upper surface thereof, as claimed in claim 13, for upper and lower connection with the BGA terminals of the upper layer, comprising a FC-BGA substrate having a recess for receiving a semiconductor in the package itself and a lid of a heat sink,

a part different from a general FC-BGA substrate is that a pad electrode (pad) having a geometric shape for connection with a BGA package of an upper layer is provided on an upper surface except for a dimple; the portion of the pit has an FC bump bonded to the semiconductor; a portion to be added to a normal FC-BGA substrate is a portion in which a substrate having a hole in the center for receiving a semiconductor is added, and a pad (land) extending upward in the form of a through hole and connected to a BGA bump of an upper package is provided on the surface;

the BGA bonding pad is not arranged on the upper surface of the part of the semiconductor surface, in order to arrange a radiator on the pit of the substrate of the semiconductor part and form a cover by coating a compound;

the pit portion may be configured as follows: a state in which a substrate having a hole for receiving a semiconductor opened at the center thereof in a manufacturing process of the substrate is bonded, and a substrate constituting a lower portion of the package and a pad (pad) portion constituting an upper portion are connected to each other by formation of a through hole; when the distances between the BGA bumps of the first layer and the second layer and thereafter and the pads (bonding pads) are the same, the BGA bumps of all layers and the pads may be vertically connected through the through holes to constitute the internal bus of the three-dimensional semiconductor constituted this time;

alternatively, the semiconductor chip may be directly bonded to the FC-BGA substrate of the upper cover by FC balls, and the substrate and the semiconductor chip may be vertically bonded by FC balls.

33. The semiconductor of claim 13, 32,

the semiconductor itself may also be the same in all layers; a welding pad connected with the upper layer is arranged on the FC-BGA substrate of the first layer, and the substrate of the upper cover is provided with the welding pad in a penetrating way; the BGA of the second layer and the edge part of the FC-BGA substrate behind the second layer is provided with a welding pad which longitudinally penetrates through the substrate and is connected with the upper cover;

the second and subsequent layers soldered to the PCB other than the first layer may also be formed of BGA with small bumps;

the BGA welding pad on the upper surface of the first layer, the second layer and the BGA convex blocks and welding pads behind the second layer are used for interlayer coupling, and convex blocks and convex block intervals smaller than those of the first layer can also be adopted; the BGA pads on the upper surface of the first layer and the second and subsequent BGA bumps and pads may or may not include external bus connections;

the interconnection with the external bus can also be undertaken only by the bottommost chip; when the BGA connection of the small bump does not include an external bus connection, the signal propagation distance becomes extremely short, and thus a high-speed clock operation can be performed; in addition, since the signal is not connected to the terminal, the signal becomes an operation mode in which reflection is considered as in the PCI bus; since the BGA is formed of small bumps, holes may be formed in the upper FC-BGA substrate and the lower FC-BGA substrate to allow stacking by a guide pin or the like in order to improve the alignment accuracy of the stacking;

in the power supply method according to claim 26 or 27, an electrode may be provided in the hole of the leader pin by plating, and the leader pin may be used as a rod for supplying power.

34. The semiconductor of claims 13, 32, and 33,

forming a package from the FC-BGA substrate with the same semiconductor chip receiving cavity as the first layer in the second and subsequent layers by not using the small-bumped BGA bumps of claim 33 but using BGA bumps of the same size in all layers, and enclosing the package with a heat sink together with the compound; by removing the BGA bumps covering the part of the package and the heat sink, while disposing the BGA bumps for external connection bus on the inner side of the lower part of the chip which is blocked by the chip and cannot penetrate vertically, and disposing the BGA bumps for interconnection between the chips on the outer side, it is possible to remove only a part of the BGA bumps for external connection, and to constitute the second layer and the subsequent layers by using a package based on the same semiconductor in all layers and the same substrate in all layers except for the absence of a part of the BGA bumps.

35. The semiconductor of claims 10, 11, 12, 28, 29, and 30,

grooves for passing the refrigerant are not necessarily cut in the interposer, but may be cut in the back surface of the semiconductor; in this case, the interposer serves to pass the TSV and protect the semiconductor surface coated with the compound; the stacked semiconductors and interposers may be fixed to each other by means of an underfill, an adhesive (coating), an adhesive film, or the like; thus, the semiconductor becomes thinner corresponding to the absence of the grooves in the interposer, and the thermal resistance of the interposer decreases.

Technical Field

The invention relates to a semiconductor device and a computer.

This application is related to the international applications described below. This application is filed in the united states for continuation in part of the following international applications. The present application is based on the application for which the following international application claims priority, and the contents described in the following international application are incorporated into the present application by reference with respect to the approval of the designated country introduced by reference as a part of the present application.

1. International application PCT/JP2018/002310 application date 2018, 1 month 25

2. International application PCT/JP2018/038379 application date 2018, 10 and 15

3. International application PCT/JP2018/041184 application date 2018, 11 and 6

Background

A technique for releasing heat from a SiP type semiconductor element is known (for example, see patent document 1).

Disclosure of Invention

Technical problem to be solved by the invention

In order to further improve the computing performance of the computing device, not only HBM (high bandwidth Memory) in which Memory elements are vertically stacked but also a plurality of semiconductor chips that generate heat such as CPU and GPU are vertically stacked to form a stacked three-dimensional computing circuit, and if a cooling technique for effectively releasing the heat generated at this time is not available, a stacked three-dimensional integrated circuit cannot be formed except for the Memory, a higher-performance computing device used in a cloud server or the like cannot be realized, and the performance of the computing device is improved to the limit. If a three-dimensional integrated circuit is configured by using the cooling method proposed by the present invention, the performance improvement limit can be easily broken.

According to a first aspect of the present invention, a semiconductor device is provided. The semiconductor device may include a plurality of stacked semiconductor chips. The semiconductor device may include an interposer between each of the plurality of semiconductor chips or between each of the plurality of three-dimensionally mounted semiconductor chips. Each of the interposers may be provided with a moving path of the refrigerant. The moving paths of the refrigerants provided in the interposers may be connected to each other.

The plurality of interposers may also include a first interposer provided with a groove, and a second interposer provided between a surface of the first interposer provided with the groove and a lower surface of the integrated circuit and blocking the groove provided in the first interposer. The moving path of the refrigerant may be formed by holes penetrating the integrated circuit, the first interposer, and the second interposer, which are sandwiched between the grooves formed in the respective first interposers and the second interposers. The refrigerant flows through a space formed by the space passing through the groove and the second interposer and the holes of the integrated circuits, the first interposer, and the second interposer.

The refrigerant moving path may be provided by a heat pipe disposed in the groove.

The heat pipe may connect between the plurality of interposers obliquely across the layers outside the semiconductor device.

The groove formed in the first interposer of the plurality of interposers may include a plurality of first groove portions extending in the first direction. The groove formed in the second interposer of the plurality of interposers may include a plurality of first groove portions extending in a second direction different from the first direction.

The first direction and the second direction may also be substantially orthogonal.

The plurality of semiconductor chips may be connected between the grooves passing through the plurality of stages through the via holes. The via hole may be provided at a position surrounded by the recess when viewed from the stacking direction of the plurality of semiconductor chips. Further, the via hole may be formed at a corresponding position of the semiconductor, and may be formed between the grooves of the interposer where the grooves through which the refrigerant passes are formed, to bond the layers.

The plurality of semiconductor chips may be connected between upper and lower layers through via holes. A surrounding groove surrounding the via hole may be formed on the plurality of interposers. Each of the plurality of semiconductor chips may be bonded to an adjacent interposer by an adhesive disposed in the surrounding groove.

The plurality of semiconductor chips may be arithmetic devices such as CPUs and GPUs. A logic block including a plurality of logic chips and a plurality of interposers may be mounted on the first major surface side of the substrate. The semiconductor device may further include one or more three-dimensional memory chips provided on a second main surface of the substrate opposite to the first main surface, or between the logic block and the first main surface. With this configuration, by configuring the shortest circuit between the three-dimensional integrated circuit including the arithmetic devices of a plurality of layers and the three-dimensional memory chip, it is possible to suppress heat generation and realize data communication among the memory, the CPU, and the GPU using a high-speed clock.

Cooling is performed without using a cooling pipe by forming a groove through which a coolant flows in a copper or aluminum plate or a silicon substrate and connecting upper and lower layers by a hole in a vertical direction to form a cooling line.

Further, in another aspect proposed here, a cooling pipe is formed by forming vertical and horizontal grooves through which a coolant flows in a copper, aluminum, or silicon substrate without using a cooling pipe, and opening the grooves to extend to the end of the substrate, whereby the coolant is cooled from the inside of the semiconductor by entering the coolant from the side surface through the immersion liquid, and it is not necessary to form a vertical pipe through a vertical hole. The vertical and horizontal grooves avoid the portions constituting the TSV. In the case of inserting a layer of copper or aluminum, the portion of the TSV in the vertical direction of the structure other than the groove requires a silicon substrate in the hole portion of the copper or aluminum plate.

The grooves through which the refrigerant passes are formed by vertically and horizontally digging grooves on the substrate layer by etching, CNC engraving, laser engraving, or punching, and the grooves through which the refrigerant passes may be V-shaped, U-shaped, or "コ" shaped.

According to the second aspect of the present invention, in mounting an independent semiconductor in an independent BGA or semiconductor package based on the same conventional BGA, the independent semiconductor package can be vertically stacked in any layer in the vertical direction by providing a geometric pad for connecting terminals of the BGA on the upper surface of the package. The stacked BGA terminals are cooled by immersion liquid in the gaps of the ball grids. A semiconductor package and a cooling method are provided, in which a ball grid of BGA is mounted on the lower part of a semiconductor, a geometrical pad contacting with the BGA is mounted on the upper surface, and immersion is used as a precondition. The laminated integrated circuit designed as described in this item is stacked up and down, and a three-dimensional laminated integrated circuit is configured on the premise of an immersion liquid.

The semiconductor packages are stacked one on top of the other and held pressed against misalignment. The holding mechanism may have a guide so that the stacked semiconductors do not shift. The coolant flows through the gaps of the ball grid of the BGA terminal or the like. Further, since the cooling liquid does not flow between the interposers, and each semiconductor is formed of a conventional semiconductor package except for adding a geometric pad to the upper surface, the difficulty in manufacturing is not increased. Since the data path corresponds to the thickness in the vertical direction including the contact, high-speed interconnection can be realized, and the essence of the present invention can be realized without changing the conventional semiconductor manufacturing method.

The three-dimensional semiconductor device according to claim 13, wherein the three-dimensional semiconductor device has a structure in which, in order to increase the impedance when power is supplied,

in claim 26, the power feeding electrode is provided at the edge portion, and the impedance can be reduced to feed a large current.

In claim 27, a cap is provided on the power supply electrode of claim 26 to further reduce the impedance. A laminated ceramic capacitor may be mounted between the positive and negative electrodes.

In addition, the summary of the invention does not list all necessary features of the invention. In addition, a sub-combination of these feature groups can also be an invention.

Means for solving the problems

The three-dimensional stacked integrated circuit as set forth in claim 1, wherein a plurality of interposers are provided between the respective integrated circuits of the three-dimensional stacked integrated circuit and below the lowermost integrated circuit; a plurality of the interposers are respectively provided with a moving path of a refrigerant; the paths of the refrigerant flowing through the plurality of interposers are connected to each other.

The three-dimensional stacked integrated circuit shown in claim 2 is the three-dimensional stacked integrated circuit of claim 1, wherein a plurality of the interposers have: a first interposer provided with a groove, and a second interposer provided between a surface of the first interposer provided with the groove and a lower surface of the integrated circuit, the second interposer sealing the groove provided in the first interposer; a moving path of the refrigerant is formed by a space formed between the groove formed at each of the first interposers and the second interposer and a hole passing through the integrated circuit, the first interposer, and the second interposer; the refrigerant flows in a space formed by a space sandwiched between the groove and the second interposer and a hole penetrating the plurality of integrated circuits, the first interposer, and the second interposer.

The three-dimensional laminated integrated circuit shown in claim 3 is the three-dimensional laminated integrated circuit described in claim 1, wherein the moving path of the refrigerant is formed by a heat pipe extending in grooves sandwiched between grooves formed respectively in the plurality of interposers and the integrated circuit; the movement path is a path through which the heat pipe disposed in the recess passes outside the three-dimensional stacked integrated circuit to reach the heat pipe of the interposer of the next layer, and the refrigerant flows through the movement path.

The three-dimensional stacked integrated circuit shown in claim 4 is the three-dimensional stacked integrated circuit of claim 3, wherein the groove formed in at least one of the plurality of interposers includes a first groove and a second groove formed to an edge of the interposer; the heat pipe has: a first portion disposed in the first recess; a second portion disposed in the second recess; and a third portion bent at an outside of the interposer and connecting the first portion and the second portion.

The three-dimensional stacked integrated circuit shown in claim 5 is the three-dimensional stacked integrated circuit described in any one of claims 2 to 4, wherein, among the plurality of interposers, the grooves engraved in adjacent interposers are substantially orthogonal to each other between adjacent interposers.

The three-dimensional stacked integrated circuit described in claim 6 is the three-dimensional stacked integrated circuit described in any one of claims 1 to 5, wherein a plurality of the integrated circuits are connected via a via hole.

The three-dimensional laminated integrated circuit described in claim 7 is the three-dimensional laminated integrated circuit described in any one of claims 1 to 6, wherein the plurality of integrated circuit layers and the interposer layer having the groove formed therein are bonded with an adhesive including a die adhesive, an adhesive tape, or pressure-bonding.

The three-dimensional stacked integrated circuit shown in claim 8 is the three-dimensional stacked integrated circuit described in any one of claims 1 to 7, the three-dimensional stacked integrated circuit including: a substrate; an HBM (high bandwidth memory) provided to the substrate; and a three-dimensional array of a plurality of computing devices, a plurality of general purpose GPUs, and a plurality of general purpose DSP devices disposed on the substrate; the substrate is disposed between the plurality of arithmetic devices, the plurality of general purpose GPUs, and the plurality of general purpose DSP devices, and the HBM, or the HBM is disposed between the plurality of arithmetic devices, the plurality of general purpose GPUs, and the plurality of general purpose DSP devices, and the substrate.

The three-dimensional stacked integrated circuit according to claim 9 is the three-dimensional stacked integrated circuit according to any one of claims 1 to 8, wherein the channel is formed by forming a groove for flowing a refrigerant in a copper or aluminum plate or a silicon substrate without using a cooling pipe and connecting upper and lower layers by a hole in a vertical direction.

The three-dimensional stacked integrated circuit according to claim 10 is the three-dimensional stacked integrated circuit according to claim 1, wherein longitudinal and transverse grooves through which a refrigerant flows are formed in the copper, aluminum, or silicon substrate without using a cooling pipe, and the grooves are extended to an end portion of the substrate and are opened, whereby the refrigerant is made to penetrate into each layer from a peripheral surface of the semiconductor by the immersion liquid and is released from each layer to cool an inner side of the semiconductor, and there is no need to form a pipe through which the refrigerant flows in a layer direction. The vertical and horizontal grooves avoid the portions constituting the TSV. The structure of the cooling system is simplified by circulating the refrigerant to the outside at each layer by the grooves provided up to the end of the interposer.

In the case where a layer of copper or aluminum is inserted as a member constituting the recess, it is necessary to fill the portion of the hole of the copper or aluminum plate constituting the portion of the TSV in the vertical direction with a silicon substrate.

The three-dimensional laminated integrated circuit shown in claim 11 is the three-dimensional laminated integrated circuit described in claim 9 or 10, wherein the grooves for refrigerant to pass are formed by cutting with etching, engraving or computer NC on the substrate layer, or by punching and vertically and horizontally digging out the grooves, and the grooves for refrigerant to pass are V-shaped, U-shaped, or "コ".

The three-dimensional stacked integrated circuit according to claim 12 is the three-dimensional stacked integrated circuit according to any one of claims 1 to 11, wherein the sealing material is attached in a case where the recess is formed in only one direction, and the three-dimensional semiconductor cooling apparatus and the method prevent the liquid from being immersed in the recess, the three-dimensional stacked integrated circuit being provided with the inlet and the outlet. In the case of an immersion liquid, the discharge port is opened in the liquid by having only the injection port in one direction or in a vertically and horizontally open type, and cavitation is prevented by applying a positive pressure from the injection port.

In claim 13, when mounting an individual semiconductor in an individual BGA or semiconductor package based on the former, the individual semiconductor packages can be stacked vertically in any layer by providing a geometric pad for connecting terminals of the BGA on the upper surface of the package. The stacked BGA terminals are cooled by immersion liquid in the gaps of the ball grids. A semiconductor package and a cooling method are provided, in which a ball grid of a BGA is mounted on a lower portion of a semiconductor, a pad having a geometric shape which is in contact with the BGA is mounted on an upper surface of the semiconductor, and an immersion liquid is used as a precondition. The laminated integrated circuit designed as described in this item is stacked up and down, and a three-dimensional laminated integrated circuit is configured on the premise of an immersion liquid.

The semiconductor packages are stacked one on top of the other and held pressed against misalignment. The holding mechanism may have a guide so that the stacked semiconductors do not shift. The coolant flows through the gaps of the ball grid of the BGA terminal or the like. Further, since the cooling liquid does not flow between the interposers, and each semiconductor is formed of a conventional semiconductor package except for adding a geometric pad to the upper surface, the difficulty in manufacturing is not increased. Since the data path corresponds to the thickness in the vertical direction including the contact, high-speed interconnection can be realized, and the essence of the present invention can be realized without changing the conventional semiconductor manufacturing method.

The three-dimensional stacked integrated circuit shown in claim 14 is the three-dimensional stacked integrated circuit described in claim 13, wherein the pads are contacted by springs.

The method described in claim 15 is a method for cooling the three-dimensional semiconductor described in claims 13 and 14, wherein the operation of the stacked memory and processor is speeded up by using the vertical connection of the semiconductors stacked on the pads as a vertical bus.

The three-dimensional stacked integrated circuit according to claim 16 is the three-dimensional stacked integrated circuit according to any one of claims 1 to 15, and not only the CPU, the GPGPU, and the computing section of the virtual currency mining central computing unit, but also the HBM is mounted on the three-dimensional semiconductor of the cooling method of this embodiment, or a memory layer is interposed between layers.

The apparatus and method for constructing an arithmetic device according to claim 17, wherein the memory layer according to claim 16 is sandwiched between the arithmetic layer and the memory layer, and thus only the arithmetic layer and the memory layer need to be connected by TSVs.

The three-dimensional stacked integrated circuit described in claim 18 is the three-dimensional stacked integrated circuit described in any one of claims 1 to 17, wherein, as a member which is not only in contact with the BGA but also prevents the three-dimensional cooling semiconductor from being decomposed by the pressure of the cavitation, metal plates including aluminum plates are prepared on the upper and lower sides (the back surface of the PCB and the back surface of the semiconductor), and are held at four or more points by clips. The aluminum plate and the PCB sandwich a member including an insulator therebetween.

The three-dimensional stacked integrated circuit described in claim 19 is the three-dimensional stacked integrated circuit described in any one of claims 1 to 18, wherein TSVs for redundant data paths are provided at a plurality of locations, and a plurality of processor arrays including defective locations are overlapped, whereby defective locations may exist in the data paths, and the processor elements may be used so that the defective locations gradually increase in three-dimensional mounting of a fine semiconductor initially including defective locations.

The three-dimensional stacked integrated circuit according to claim 20 is used at a temperature at which cavitation is not caused by the immersion liquid in the three-dimensional stacked integrated circuit according to any one of claims 1 to 19.

The three-dimensional laminated integrated circuit according to claim 21 is the three-dimensional laminated integrated circuit according to any one of claims 1 to 20, wherein cavitation is prevented by mounting a connector on any one side of the semiconductor in spite of an immersion liquid and injecting the solution under a positive pressure by a pump.

The three-dimensional stacked integrated circuit described in claim 22 is the three-dimensional stacked integrated circuit described in any one of claims 1 to 21, wherein an acoustic sensor is provided, and a clock frequency is controlled using an output of the acoustic sensor to prevent occurrence of cavitation and to operate the three-dimensional stacked integrated circuit.

The three-dimensional stacked integrated circuit described in claim 23 is the three-dimensional stacked integrated circuit described in claim 22, wherein a metal plate including an aluminum plate is prepared on the upper and lower sides (the back surface of the PCB and the back surface of the semiconductor) as a member for preventing decomposition of the three-dimensional cooling semiconductor for preventing cavitation, and is sandwiched at four or more points by clips. The aluminum plate and the PCB sandwich a member including an insulator therebetween.

The three-dimensional laminated integrated circuit according to claim 24 is the three-dimensional laminated integrated circuit according to claim 23, wherein a whistle generated by boiling of the refrigerant is detected by the sound sensor, and the frequency is controlled within a range in which the whistle is not generated.

The three-dimensional stacked integrated circuit shown in claim 25 is the three-dimensional stacked integrated circuit according to claim 24, wherein the depth and length of the groove are changed to prevent resonance, thereby preventing whistling resonance. In this case, the semiconductor has a trapezoidal shape in order to change the length of the groove. In the case where the longitudinal and lateral grooves are present, the trapezoidal shape is irregular in order to prevent the longitudinal and lateral resonances from occurring.

The semiconductor device according to claim 26, wherein electrodes are provided at corners or edges or both of the semiconductor device formed by stacking BGA packages, and electrodes having a metal rod shape are brought into contact with the electrodes, thereby supplying GND having low impedance and stable power supply potential. The metal rod-like electrode may have a structure in which a capacitor is provided between both the positive electrode and the negative electrode.

In the semiconductor device according to claim 26, a cover having a function of connecting the electrodes to each other may be provided in order to press the stacked semiconductor device and supply a stable potential with low impedance. The cover may also be provided with a spring or the like for pressing the semiconductor. In addition, the cover may have a path for connecting the respective potentials of the positive electrode and the negative electrode to each other.

Claim 28 is the semiconductor of claim 10, claim 11, or claim 12, wherein the substrate of the first layer may be a normal FC-BGA substrate without a recess. The semiconductor of the first layer is connected with the interposer of the first layer through the TSV. Between the FC-BGA substrate of the first layer and the semiconductor of the first layer, in order to prevent water from entering into the FC pad between the FC pad and the semiconductor of the first layer, the periphery of the FC pad is reinforced with underfill or the like.

Claim 29 is the semiconductor device of claim 28, wherein the laminated portion of the interposer and the semiconductor chip is reinforced with underfill or the like for preventing the FC pad from being impregnated with the refrigerant.

In claim 30, in the case of the semiconductor device according to claim 28 or claim 29, the grooves through which the refrigerant passes and the regions having the FC pads of the TSVs do not necessarily have to be present alternately with each other, and since the regions constituting the semiconductor device disappear if the TSV regions in the vertical direction are too large, the number of the regions having the FC pads of the TSVs may be limited. The groove and the recess may also be adjacent.

The semiconductor device according to claim 31 is the semiconductor device according to claim 10, claim 11, claim 12, claim 28, claim 29, or claim 30, wherein electrodes are provided at corners or edges of the semiconductor device or both of them, and electrodes having a metal rod shape are brought into contact with the electrodes, as in claims 26 and 27, thereby supplying GND having low impedance and stable power supply potential. The metal rod-like electrode may have a structure in which a capacitor is provided between both the positive electrode and the negative electrode. In order to press the stacked semiconductors and supply a stable potential with low impedance, a cover may be provided that has a function of connecting the electrodes to each other. The cover may also be provided with a spring or the like for pressing the semiconductor. In addition, the cover may have a path for connecting the respective potentials of the positive electrode and the negative electrode to each other.

The semiconductor device of claim 13, wherein the package having pads on the upper surface thereof according to claim 13 for vertical connection to the BGA terminals of the upper layer is composed of a FC-BGA substrate having a cavity for receiving the semiconductor device and a lid of the heat sink.

A part different from the typical FC-BGA substrate is that a geometrically shaped pad electrode (pad) for connection with the BGA package of the previous layer is provided on the upper surface except the dimple. The portion of the dimple has an FC bump bonded to the semiconductor. The portion to be added to a normal FC-BGA substrate is a portion in which a substrate having a hole in the center for receiving a semiconductor is added, and a pad (land) extending upward in the form of a through hole and connected to a BGA bump of an upper package is provided on the surface.

The reason why no BGA pad is provided on the upper surface of the portion of the semiconductor surface is to provide a heat sink on the recess of the substrate of the semiconductor portion and to form a cap by applying a compound.

The pit portion may be configured as follows: in the manufacturing process of the substrate, a substrate having a hole for receiving a semiconductor in the center is bonded, and the substrate constituting the lower portion of the package and a pad (land) portion constituting the upper portion are connected to each other by formation of a through hole. When the distances between the BGA bumps of the first layer and the second layer and thereafter and the pads (pads) are the same, the BGA bumps of all layers and the pads may be vertically connected through the through holes to constitute the internal bus lines of the three-dimensional semiconductor of this configuration.

Alternatively, the semiconductor chip may be directly bonded to the FC-BGA substrate of the upper cover by FC balls, and the substrate and the semiconductor chip may be vertically bonded by FC balls.

Claim 33 is the semiconductor of claim 32, which itself may be the same in all layers. The first layer of FC-BGA substrate has pads connected to the upper layer of the FC-BGA substrate, and the upper cover of the FC-BGA substrate has pads through it. The BGA of the second layer and the edge portion of the FC-BGA substrate after the second layer has a pad longitudinally penetrating the substrate and connected to the upper lid.

The second layer and the subsequent layers soldered to the first layer of the PCB may be formed of BGA with small bumps.

The BGA pads on the upper surface of the first layer and the second and subsequent BGA bumps and pads are used for interlayer coupling, and smaller bumps and bump spacings than the first layer may also be used. The BGA pads on the upper surface of the first layer and the BGA bumps and pads of the second and subsequent layers may or may not include external bus connections.

The interconnection to the external bus may also be undertaken by only the lowest chip. When the BGA connection of the small bump does not include the external bus connection, the signal propagation distance becomes extremely short, and thus a high-speed clock operation can be performed. Since the signal is not connected to the terminal, the signal is operated in consideration of the reflection similar to the PCI bus. Since the BGA is formed of small bumps, holes may be formed in the upper FC-BGA substrate and the lower FC-BGA substrate to allow stacking by means of guide pins or the like in order to improve the alignment accuracy of the stacking.

In the power supply method according to claim 26 or 27, an electrode may be provided in the hole of the leader pin by plating, and the leader pin may be used as a rod for supplying power.

Claim 34 is the semiconductor device of claim 32 or claim 33, wherein the package is formed by using the FC-BGA substrate having the same recess for receiving the semiconductor chip as the first layer in the second and subsequent layers, and the package is sealed with a heat sink together with the compound, by using the BGA bumps of the same size as the small bumps of claim 33 in all layers, instead of the BGA bumps of the small bumps of claim 33. By removing the BGA bumps covering the part of the package and the heat sink, while disposing the BGA bumps for external connection bus on the inner side of the lower part of the chip which is blocked by the chip and cannot penetrate vertically, and disposing the BGA bumps for interconnection between the chips on the outer side, it is possible to remove only a part of the BGA bumps for external connection, and to constitute the second layer and the subsequent layers by using a package based on the same semiconductor in all layers and the same substrate in all layers except for the absence of a part of the BGA bumps.

In the case of the semiconductor device according to claim 35, which is described in claim 10, claim 11, claim 12, claim 28, claim 29, or claim 30, grooves for passing a refrigerant are not necessarily formed in the interposer, and grooves may be formed in the back surface of the semiconductor device. In this case, the interposer serves to pass the TSV and protect the surface of the compound-coated semiconductor. The stacked semiconductors and interposers may be fixed to each other by water-proofing with an underfill adhesive, an adhesive (coating), an adhesive film, or the like. Thus, the semiconductor becomes thinner corresponding to the absence of the grooves in the interposer, and the thermal resistance of the interposer decreases.

Drawings

Fig. 1 schematically shows an exploded perspective view of a semiconductor device 10.

Fig. 2 schematically shows a perspective view of the substrate 240, the logic block 50 and the memory block 60.

Fig. 3 is a perspective view schematically showing a state in which the interposer 100, the interposer 110, and the interposer 120 are stacked in the stacking direction.

Fig. 4 schematically shows a cross section of the semiconductor device 10.

Fig. 5 is a perspective cross-sectional view showing a flow path of the coolant for the semiconductor chip.

Fig. 6 shows a schematic perspective view of the interposer 100, the interposer 110, and the interposer 120.

Fig. 7 schematically shows a plan view of the interposer 120 as viewed from the stacking direction.

Fig. 8 schematically shows a cross-sectional view of a semiconductor device 600 according to a second embodiment together with a heat pipe 500.

Fig. 9 shows a schematic perspective view of interposer 420 forming semiconductor device 600.

Fig. 10 is a schematic perspective view of a portion of a semiconductor device 600 including an interposer 420, a semiconductor chip 220, and an interposer 410.

Fig. 11 is a schematic perspective view showing an arrangement structure of heat pipes.

Fig. 12 is a perspective view showing a modification of the arrangement structure of the heat pipe.

Fig. 13 shows an interposer 1100, an interposer 1110, an interposer 1120, and a heat pipe 1500 in a modification of the semiconductor device 600.

Fig. 14 is a front view showing the arrangement of the interposer 1100, the interposer 1110, the interposer 1120, the heat pipe 1500, and the semiconductor chip 200 in the modification.

Fig. 15 schematically shows a perspective view of a semiconductor device 1700 in another embodiment.

Fig. 16 schematically shows an exploded perspective view of the semiconductor device 1700.

Fig. 17 schematically shows a perspective view of a computer 1810 provided with a semiconductor device 1700.

Fig. 18 schematically shows a computer system 1840 provided with a computer unit 1800 and a cooling system 1850.

Fig. 19 schematically shows the structure of the groove.

Fig. 20 schematically shows a structure for preventing decomposition of the three-dimensionally cooled semiconductor.

Fig. 21 schematically shows a structure for preventing cavitation of the refrigerant.

Fig. 22 schematically shows a structure for preventing cavitation of the refrigerant.

Fig. 23 schematically shows a structure for preventing cavitation of the refrigerant.

Fig. 24 schematically shows a structure used for preventing cavitation.

Fig. 25 schematically shows a structure for preventing resonance of a whistle.

Fig. 26 schematically shows another structure for preventing whistle resonance.

Fig. 27 schematically shows another structure for preventing whistle resonance.

Fig. 28 schematically shows a semiconductor package for cooling a three-dimensional stacked integrated circuit by immersion.

Fig. 29 shows a case where power is supplied to a corner portion of a semiconductor in which BGA packages are stacked.

Fig. 30 shows a case where power is supplied to a side surface of a semiconductor in which BGA packages are stacked.

Fig. 31 shows a case where power is supplied to the positive electrode and the negative electrode on the side surface of the semiconductor in which BGA packages are stacked.

Fig. 32 shows a structure of a metal rod-like electrode.

Fig. 33 shows the structure (surface) of a cover having a function of connecting electrodes to each other.

Fig. 34 shows the structure (back) of the cover.

Fig. 35 shows a case where a spring and a capacitor are mounted on the structure (back surface) of the cover.

Fig. 36 shows a structure (upper side) of a slotted laminated semiconductor.

Fig. 37 shows a structure (lower side) of a slotted laminated semiconductor.

Fig. 38 shows a case where the TSV periphery is covered with an adhesive or the like in the interposer portion of the grooved semiconductor.

Fig. 39 shows a structure of one layer of the BGA laminated semiconductor.

Fig. 40 shows a structure of a BGA laminated semiconductor with respect to a lid.

Fig. 41 shows a structure of the BGA laminated semiconductor viewed from the lateral direction.

Fig. 42 shows the structure of the first layer of the BGA laminated semiconductor as viewed from the back surface.

Fig. 43 shows the structure of the second layer of the BGA laminated semiconductor as viewed from the back surface.

Fig. 44 shows an interposer in which the width of the groove of the grooved semiconductor is changed.

Fig. 45 shows a structure of a stacked semiconductor using BGA bumps in which the first layer and the second layer and layers subsequent thereto have the same size when viewed from the lateral direction.

Fig. 46 shows an example of mounting a laminated semiconductor with a groove provided on the semiconductor side.

Detailed Description

The present invention will be described below with reference to embodiments of the invention, but the following embodiments do not limit the invention according to the claims. All combinations of the features described in the embodiments are not essential to the means for solving the problems of the present invention.

Fig. 1 is an exploded perspective view schematically showing a substrate 240, a logic block 50, and a memory block 60 included in the semiconductor device 10. Fig. 2 schematically shows a perspective view of the substrate 240, the logic block 50 and the memory block 60. In fig. 1 and 2, a part of components constituting the semiconductor device 10 is shown in perspective. Fig. 3 is a perspective view schematically showing a state in which the interposer 100, the interposer 110, and the interposer 120 are stacked in the stacking direction. In fig. 3, interposer 100, interposer 110, and interposer 120 are shown in perspective. Fig. 4 schematically shows a cross section of the semiconductor device 10. Fig. 5 is a perspective cross-sectional view showing a flow path of the coolant for cooling the semiconductor chip 200, the semiconductor chip 210, and the semiconductor chip 220. Fig. 6 is a schematic perspective view of the interposer 100, the interposer 110, and the interposer 120. The semiconductor device 10 is provided in a computer. The semiconductor device 10 is a three-dimensional stacked integrated circuit.

The semiconductor device 10 includes a substrate 240, a semiconductor chip 200, a semiconductor chip 210, a semiconductor chip 220, an interposer 100, an interposer 110, an interposer 120, an interposer 150, an interposer 160, an interposer 170, a memory chip 250, a memory chip 260, a memory chip 270, and a cooling device 190. In the drawings used in the description of the embodiments, the components are schematically depicted, not at a uniform scale, for the purpose of facilitating understanding of the components and the like. In fig. 1 to 3, the depiction of the grooves 107, 117 and the groove 127 is omitted.

Semiconductor chip 200, semiconductor chip 210, semiconductor chip 220, interposer 100, interposer 110, interposer 120, interposer 150, interposer 160, and interposer 170 are included in logic block 50. Memory chip 250, memory chip 260, and memory chip 270 are included in memory block 60. The memory block 60 may also be an HBM. The cooling device 190 is disposed at an upper portion of the logic block 50.

The memory chips 250, 260, and 270 function as a main memory of the computer. Each of the semiconductor chip 200, the semiconductor chip 210, and the semiconductor chip 220 may have a cache memory therein.

The semiconductor chip 200, the semiconductor chip 210, and the semiconductor chip 220 are logic chips each including an integrated circuit. For example, the semiconductor chip 200, the semiconductor chip 210, and the semiconductor chip 220 are a DSP, a GPU, and a CPU, respectively. The DSP may also be a general purpose DSP. The GPU may also be a general purpose GPU. The semiconductor device 10 may include one or more CPUs, one or more DSPs, and one or more GPUs. The semiconductor device 10 may include a plurality of CPUs, a plurality of DSPs, and a plurality of GPUs.

The semiconductor chip 200, the semiconductor chip 210, the semiconductor chip 220, the interposer 100, the interposer 110, the interposer 120, the interposer 150, the interposer 160, and the interposer 170 are mounted on the first main surface 241 side of the substrate 240. The memory chip 250, the memory chip 260, and the memory chip 270 are mounted on the second main surface 242 on the opposite side of the first main surface 241 of the substrate 240.

The semiconductor chip 200, the semiconductor chip 210, and the semiconductor chip 220 are stacked and mounted on the substrate 240. The semiconductor chip 200 is an integrated circuit disposed at the lowermost level. The interposer 100 and the interposer 150 are disposed between the substrate 240 and the semiconductor chip 200. The interposer 110 and the interposer 160 are disposed between the semiconductor chip 200 and the semiconductor chip 210. The interposer 120 and the interposer 170 are disposed between the semiconductor chip 210 and the semiconductor chip 220. The interposer 100, the interposer 150, the semiconductor chip 200, the interposer 110, the interposer 160, the semiconductor chip 210, the interposer 120, the interposer 170, and the semiconductor chip 220 are provided in this order from the main surface 241 side of the substrate 240. The semiconductor layers of the semiconductor chips 200, 210, and 220 and the interposer layer including the interposers 100, 110, and 120 are bonded or pressure-bonded with an adhesive including a die adhesive or an adhesive tape.

The semiconductor chip 200, the semiconductor chip 210, the semiconductor chip 220, and the memory block 60 are connected via the via 20 and the micro bump 30. The vias 20 are via holes. The vias 20 are respectively disposed in the interposer 100, the interposer 110, the interposer 120, the semiconductor chip 200, the semiconductor chip 210, the semiconductor chip 220, the memory chip 250, the memory chip 260, and the memory chip 270. The via 20 is a Through Silicon Via (TSV). Note that the illustration of the via hole 20 is omitted in fig. 1.

In this way, the semiconductor device 10 includes a substrate 240 provided with the memory block 60, and a three-dimensional array of CPU, general-purpose GPU, and general-purpose DSP devices provided above the substrate 240. A substrate 240 is disposed between the CPU, GPU, and DSP and HBM.

The interposer 100 has a recess 104 formed therein. The interposer 110 has a recess 114 formed therein. The interposer 120 has a recess 124 formed therein. Refrigerant from cooling device 190 circulates through grooves 104, grooves 114, and grooves 124. Vertical holes are provided in the interposer 150 and the semiconductor chip 200 in the stacking direction, and the refrigerant passage 131 is formed by these vertical holes. Vertical holes are provided in the interposer 160, the semiconductor chip 210, and the interposer 120 in the stacking direction, and the refrigerant passage 132 is formed by these vertical holes. Through holes are formed in each of the interposer 150, the semiconductor chip 200, the interposer 110, the interposer 160, the semiconductor chip 210, the interposer 120, the interposer 170, and the semiconductor chip 220, and the refrigerant passage 130 leading from the groove 104 to the cooling device 190 is formed through the through holes. The refrigerant returns from cooling device 190 to cooling device 190 via groove 124, refrigerant passage 132, groove 114, refrigerant passage 131, groove 104, and refrigerant passage 130.

The interposer 100 has a surface 102 opposed to the substrate 240 and a surface 101 on the opposite side of the surface 102. The interposer 100 has a groove 104 and a groove 301 formed therein. Specifically, in the interposer 100, the groove 104 and the groove 301 are formed on the surface 101 facing the semiconductor chip 200. The groove 301 is disposed along the groove 104 to surround the groove 104. The grooves 104 and the grooves 301 are formed by micromachining using laser processing, etching, NC processing, or the like.

The interposer 110 has a surface 112 facing the semiconductor chip 200 and a surface 111 on the opposite side of the surface 112. The interposer 110 is provided with grooves 114 and grooves 302. Specifically, in the interposer 110, the groove 114 and the groove 302 are formed on the face 111 opposing the semiconductor chip 210. The grooves 114 and 302 are formed by micromachining using laser processing, etching, NC processing, or the like.

Interposer 120 has a surface 122 facing semiconductor chip 210 and a surface 121 on the opposite side of surface 122. The interposer 120 has a groove 124 and a groove 303 formed therein. Specifically, in interposer 120, groove 124 and groove 303 are formed on face 121 facing semiconductor chip 220. The grooves 114 and 302 are formed by micromachining using laser processing, etching, NC processing, or the like.

The upper portions of the grooves 104, 114, 124, 301, 302, and 303 are closed by the interposers 150, 160, and 170, respectively. Interposer 150, interposer 160, and interposer 170 may have openings only in the regions through which vias 20 penetrate.

Refrigerant flows through grooves 104, 114, and 124. Specifically, the refrigerant flows through a space formed by the groove 104 and the interposer 150. Similarly, the refrigerant flows through the space formed by groove 114 and interposer 160 and the space formed by groove 124 and interposer 170. Semiconductor chip 200, semiconductor chip 210, and semiconductor chip 220 are cooled by the refrigerant flowing through grooves 104, 114, and 124. The refrigerant may also be a liquid. The refrigerant is, for example, an ammonia-based liquid. The refrigerant may also be a perfluorocarbon. The refrigerant is preferably substantially non-corrosive.

A through hole penetrating the semiconductor chip 220 in the stacking direction is formed in the semiconductor chip 220, and the refrigerant from the cooling device 190 flows through the through hole and is guided to the one end 123 of the concave groove 124.

At the other end of the concave groove 124 of the interposer 120, a through hole 129 penetrating to the surface 122 is formed. Further, the semiconductor chip 210 is formed with a through hole penetrating the semiconductor chip 210 in the stacking direction, and the refrigerant flowing through the groove 124 of the interposer 120 is guided to the one end 113 of the groove 114 of the interposer 110 by passing through the through hole 129 and the through hole of the semiconductor chip 210.

At the other end of the concave groove 114 of the interposer 110, a through hole 119 penetrating to the surface 112 is formed. The semiconductor chip 200 is formed with a through hole penetrating the semiconductor chip 200 in the stacking direction, and the refrigerant flowing through the recess 114 of the interposer 110 is guided to the one end 103 of the recess 104 of the interposer 100 through the through hole 119 and the through hole of the semiconductor chip 200.

The refrigerant guided to one end 103 of the groove 104 of the interposer 100 flows in the groove 104 toward the other end 109. In the interposer 110 and the interposer 120, a through-hole 118 and a through-hole 128 are formed, respectively, at positions corresponding to the other ends 109 of the grooves 104 of the interposer 100. In addition, through-holes are formed in the semiconductor chip 200, the semiconductor chip 210, and the semiconductor chip 220 at positions corresponding to the other ends 109 of the recesses 104, respectively. The refrigerant guided to the other end 109 of the interposer 100 returns to the cooling device 190 through these through holes. Thus, the movement path of the refrigerant supplied from the cooling device 190 is formed by the grooves 104, 114, and 124. That is, grooves 104, 114, and 124 provide a flow path for the refrigerant.

In this way, the movement flow paths of the refrigerant formed by the grooves 104, 114, and 124 are provided in the interposers 100, 110, and 120, respectively. The plurality of paths for moving the refrigerant provided in each of the interposers 100, 110, and 120 are connected to each other. The refrigerant is supplied from cooling device 190 to pocket 124, circulates through pocket 124, pocket 114, and pocket 104 in this order, and returns to cooling device 190. The cooling device 190 has a heat sink or the like and cools the refrigerant. Thereby, the logic block 50 is cooled by the refrigerant circulating in the logic block 50. The refrigerant may be supplied from cooling device 190 to through hole 128, pass through hole 118 to reach the other end 109 of pocket 104, and flow in the order of pocket 104, one end 103 of pocket 104, through hole 119, pocket 114, one end 113 of pocket 114, through hole 129, pocket 124, and one end 123 of pocket 124 and return to cooling device 190.

In the semiconductor device 10 of the first embodiment, the refrigerant flow path is formed by the space between the groove formed in each of the plurality of interposers including the interposer 100, the interposer 110, and the interposer 120 and the adjacent one of the interposers 150, the interposer 160, and the interposer 170, and the hole passing through the semiconductor chip 200, the semiconductor chip 210, the semiconductor chip 220, the interposer 150, the interposer 110, the interposer 160, the interposer 120, and the interposer 170, and the space between the groove formed in each of the plurality of interposers including the interposer 100, the interposer 110, and the interposer 120 and the adjacent one of the interposers 150, the interposer 160, and the interposer 170, and the space passing through the semiconductor chip 200, the semiconductor chip 210, the semiconductor chip 220, the interposer 150, and the interposer 170, and the space between the groove formed in each of the plurality of interposers including the interposer 100, the interposer 110, and the adjacent one of the interposers, and the semiconductor chip 210, the semiconductor chip 220, the interposer 150, the, The holes of the interposers 110, 160, 120 and 170 are formed to flow through the space. The interpolators 100, 110, and 120 are examples of a first interpolator, and the interpolators 150, 160, and 170 are examples of a second interpolator.

According to the semiconductor device 10, the semiconductor chip 200, the semiconductor chip 210, the semiconductor chip 220, the memory chip 250, the memory chip 260, and the memory chip 270 can be stacked in the direction perpendicular to the main surface 241 of the substrate 240. Therefore, the physical length of the bus lines from the logic block 50 to the memory block 60 can be shortened as compared with the case where the memory block 60 is arranged in the parallel direction on the main surface 241 of the substrate 240. In addition, the wrapping of the bus within the interposer 100 can be simplified. Therefore, an increase in power consumption can be suppressed, and heat generation in the bus can be suppressed. Further, since the physical length of the bus from the logic block 50 to the memory block 60 can be shortened, it is not necessary to provide a high-order cache memory in the semiconductor chip 200, the semiconductor chip 210, and the semiconductor chip 220 in some cases. This may reduce the snooping cost (snooping cost). In addition, the error correction cost of the memory can be reduced. This can improve the performance of the semiconductor device.

In addition, according to the semiconductor device 10, since the stacked semiconductor chip 200, the semiconductor chip 210, and the semiconductor chip 220 can be efficiently cooled, the semiconductor chips of the arithmetic device that generates heat can be stacked three-dimensionally. Therefore, according to the semiconductor device 10, the performance of the semiconductor device can be dramatically improved by packaging without significantly modifying the processor technology.

An adhesive for adhering the interposer 100 and the interposer 150 is disposed in the groove 301. Also, an adhesive for adhering the interposer 110 and the interposer 160 is disposed in the groove 302. An adhesive for adhering the interposer 120 and the interposer 170 is disposed in the groove 303. The refrigerant flowing through grooves 104, 114, and 124 can be prevented from flowing to the outside of grooves 301, 302, and 303.

The interposer 100 has a groove 107 formed therein surrounding the groove 104. An adhesive for adhering the interposer 100 and the interposer 150 is disposed in the groove 107. Similarly, a groove 117 surrounding groove 114 is formed in interposer 110, and an adhesive for bonding interposer 110 and interposer 160 is disposed in groove 117. In addition, a groove 127 surrounding the groove 124 is formed in the interposer 120, and an adhesive for adhering the interposer 120 and the interposer 170 is disposed in the groove 127.

Fig. 7 schematically shows a plan view of the interposer 120 viewed in the stacking direction.

In the interposer 120, a surrounding groove 300 surrounding the via group 22 including the plurality of vias 20 is formed around the via group 22. For example, one via group 22 may include 9 vias 20 arranged in 3 rows and 3 columns. An adhesive for adhering the interposer 120 and the interposer 170 is disposed in the surrounding groove 300. This allows the gap between the interposer 120 and the semiconductor chip 220 to be closed by the adhesive disposed in the surrounding groove 300 around the via hole 20. This can seal the through hole 20, and therefore, the refrigerant flowing through the groove 124 can be reliably prevented from reaching the through hole 20. A plurality of surrounding grooves 300 surrounding each through hole group are similarly formed in the interposer 110, and an adhesive for attaching the interposer 110 and the interposer 160 is disposed in the surrounding grooves 300. In addition, a plurality of peripheral grooves 300 surrounding each through-hole group are similarly formed in the interposer 100, and an adhesive for adhering the interposer 100 and the interposer 150 is disposed in the surrounding grooves 300.

As shown in fig. 6, each of the interposer 100, the interposer 110, and the interposer 120 is formed with a meandering groove. As shown in fig. 7, the groove 124 of the interposer 120 has a plurality of first groove portions 125 extending linearly and a curved second groove portion 126. The first groove portion 125 is a portion of the groove 124 extending in a direction substantially orthogonal to a direction connecting one end 123 and the other end of the groove 124.

In fig. 7, the groove 114 formed on the interposer 110 below the interposer 120 is shown by a dotted line. The shape of the groove 114 has a shape in which the groove 124 is rotated by 90 °. The groove 114 of the interposer 110 has a first groove portion 115 extending linearly and a second groove portion 116 in a curved shape. The first groove portion 115 is a portion of the groove 114 extending in a direction substantially orthogonal to a direction connecting one end 113 and the other end of the groove 114. The direction in which the first groove portion 125 extends is substantially orthogonal to the direction in which the first groove portion 115 extends.

Likewise, the shape of the groove 104 formed on the interposer 100 generally has a shape that rotates the groove 114 formed on the interposer 110 by 90 °. Thus, in interposer 100, interposer 110, and interposer 120, the grooves inscribed in adjacent interposers are substantially orthogonal to one another between the layers. Therefore, there is a region 330 surrounded by the grooves 104, 114, and 124 of the interposer when viewed from the stacking direction of the semiconductor chips. The region 330 does not interfere with any of the interposers included in the semiconductor device 10 when viewed from the stacking direction of the semiconductor chips. Specifically, the region 330 is a quadrangular region surrounded by the first groove portion 125 and the first groove portion 115 that are orthogonal to each other. Vias 20 are disposed in region 330. As described above, the via hole 20 is provided at a position not obstructed by the recessed groove 104, the recessed groove 114, and the recessed groove 124 when viewed from the stacking direction of the semiconductor chip 200, the semiconductor chip 210, and the semiconductor chip 220. Therefore, the groove through which the refrigerant circulates does not interfere with the via hole 20.

In this way, the direction in which the plurality of first groove portions 125 formed in interposer 120 extend is different from the direction in which the plurality of first groove portions 115 formed in interposer 110 extend. The via hole 20 is provided at a position surrounded by the recess 104, the recess 114, and the recess 124 when viewed from the stacking direction of the semiconductor chips. Therefore, the grooves of the interposer do not interfere with the vias 20.

In addition, as described above, in the semiconductor device 10, the refrigerant flowing from the cooling device 190 to the concave groove 104 of the interposer 100 returns to the cooling device 190 through the through-hole 118 and the through-hole 128. Alternatively, a flow path communicating with the recess 104 of the interposer 100 may be formed in the substrate 240, and the coolant may be taken out to the outside of the logic block 50 from a coolant outlet provided in the substrate 240 through the flow path and returned to the cooling device 190. The semiconductor device 10 may be provided with a pump for circulating a refrigerant.

Fig. 8 schematically shows a cross-sectional view of a semiconductor device 600 according to a second embodiment together with a heat pipe 500. Fig. 9 shows a schematic perspective view of interposer 420 forming semiconductor device 600. Fig. 10 is a schematic perspective view of a portion of a semiconductor device 600 including an interposer 420, a semiconductor chip 220, and an interposer 410.

The semiconductor device 600 has a structure in which the heat pipe 500 is disposed in the groove instead of a structure in which the refrigerant flows in the groove formed in the interposer, and does not include the interposer 150, the interposer 160, and the interposer 170. Interposer 400, interposer 410, and interposer 420 of semiconductor device 600 do not have through-hole 118, through-hole 119, through-hole 128, and through-hole 129, and grooves 107, 117, and 127. Interposer 400, interposer 410, and interposer 420 have grooves 404, 414, and 424, respectively, that are shaped differently than grooves 104, 114, and 124. The semiconductor device 600 in the second embodiment is different from the semiconductor device 10 in the first embodiment in these points. The semiconductor device 600 according to the second embodiment is mainly explained about differences from the semiconductor device 10, and other explanations may be omitted.

The interposer 420 is a component corresponding to the interposer 120. The interposer 410 is a component corresponding to the interposer 110. The interposer 400 is a component corresponding to the interposer 100.

As shown in fig. 9, both ends of the groove 424 of the interposer 420 are located at the outer edge of the interposer 420. Specifically, one end 423 and the other end 429 of the groove 424 of the interposer 420 are located at the edge of the interposer 420. Similarly, interposer 410 has a groove with both ends located at the outer edge of interposer 410.

As shown in fig. 10, the heat pipe 500 inserted into the groove 424 of the interposer 420 extends from one end 423 and the other end 429 to the outside of the interposer 420. The heat pipe 500 extending from the other end 429 of the interposer 420 is disposed in a state of being inserted into the interposer 410 from one end of the groove formed on the rim portion of the interposer 410. As shown in fig. 6, the heat pipe 500 is configured to: the directions of the portions of the heat pipe 500 extending linearly are substantially orthogonal between the adjacent interposers.

In this way, in the semiconductor device 600 of the second embodiment, the moving path of the refrigerant is provided by the heat pipe 500 disposed in the groove formed on the interposer. The heat pipe 500 connects between the plurality of interposers outside the semiconductor device 600. Further, in the case where the heat pipe 500 is provided in the groove as in the second embodiment, it is necessary to bring the heat pipe 500 into reliable contact with the semiconductor chip. Therefore, it is preferable that the lower surface of the semiconductor chip and the upper surface of the adjacent interposer are directly strongly bonded.

As shown in the semiconductor device 600, the moving path of the refrigerant may also be formed by a heat pipe extending in grooves sandwiched between grooves formed respectively in the plurality of interposers and the integrated circuits. The path of the refrigerant may be a path in which the heat pipe disposed in the recess passes through the outside of the semiconductor device and becomes the heat pipe of the next stage, and the refrigerant flows.

Fig. 11 is a schematic perspective view showing an arrangement structure of heat pipes. The heat pipe 540 shown in fig. 11 is provided as the heat pipe 500 shown in fig. 8 to 10: the three-layer interposer extends to form a single refrigerant flow path.

Fig. 12 is a perspective view showing a modification of the arrangement structure of the heat pipe. The heat pipe 500 described above is configured to: the directions of the plurality of portions extending linearly in the heat pipe 500 are substantially orthogonal between the adjacent interposers. In contrast, in the heat pipe 550 of the present modification, the heat pipe portions disposed in the respective interposers have the same shape, and the heat pipe portions provided in the respective interposers are disposed in parallel.

In heat pipe 550, when viewed from the stacking direction of semiconductor chip 200, semiconductor chip 210, and semiconductor chip 220, a rectangular region is formed that is long with a straight portion of the heat pipe and does not overlap with any of the heat pipes. If the via hole 20 is formed in the rectangular area, the heat pipe does not interfere with the via hole 20. In the case where the refrigerant flow paths are provided in parallel between the interposers, the through holes 20 may be formed in a rectangular region that does not overlap with any of the flow paths in the stacking direction.

Heat pipe 500 and heat pipe 550 may be inserted from a gap of the interposer and disposed in the interposer. The interposers may be stacked in a state where the heat pipes are arranged in the grooves of the interposers in advance, and after the interposers are stacked, the heat pipes of the adjacent interposers may be connected to each other outside the semiconductor device 600.

Fig. 13 is a perspective view showing an interposer 1100, an interposer 1110, an interposer 1120, and a heat pipe 1500 in a modification of the semiconductor device 600. Fig. 14 is a front view showing the arrangement of the interposer 1100, the interposer 1110, the interposer 1120, the heat pipe 1500, and the semiconductor chip 200 in the modification. In this modification, the interposers 1100, 1110, 1120 have a plurality of grooves formed to respective edges. In addition, the heat pipe 1500 has a curved portion at the outside of the interposer. In these respects, this modification is different from the semiconductor device 600. Here, differences from the semiconductor device 600 will be mainly described, and other descriptions may be omitted.

As shown in fig. 13, the interposer 1120 has a plurality of grooves 1300a, 1300b, 1300c, 1300d, 1300e, 1300f, 1300g, 1300h, and 1300i extending linearly. Further, the grooves 1300a, 1300b, 1300c, 1300d, 1300e, 1300f, 1300g, 1300h, and 1300i may be collectively referred to as a groove 1300. The groove 1300 is formed from one edge of the interposer 1120 to the other edge. The grooves 1300 extend linearly and are arranged substantially in parallel. Heat pipe 1500, which extends within interposer 1120, has straight portions 1510 disposed in groove 1300a, straight portions 1520 disposed in groove 1300b, and curved portions 1530 that curve outside interposer 1120 and connect straight portions 1510 and straight portions 1520. The same is true in the other grooves 1300, and the bent portions connecting between adjacent grooves in the heat pipe 1500 exist outside the interposer. The same applies to the other interpolators 1110 and 1100. Since the bent portion of the heat pipe can be disposed outside the interposer and the semiconductor chip, the degree of freedom of curvature of the heat pipe can be improved.

The semiconductor device described above may be provided with a temperature detection circuit for detecting the temperature of the refrigerant, and a heater for adjusting the temperature of the liquid-phase refrigerant cooled by the heat sink to a boiling point just before the liquid-phase refrigerant is returned from the bottom surface of the three-dimensional semiconductor again, and returning the liquid-phase refrigerant to the bottom surface in a gaseous phase. By providing the temperature adjustment mechanism for the coolant, the coolant can be returned without boiling the coolant in the semiconductor and without causing vibration or the like in the semiconductor due to a cavitation effect or the like.

Fig. 15 schematically shows a perspective view of a semiconductor device 1700 in another embodiment. Fig. 16 schematically shows an exploded perspective view of the semiconductor device 1700.

As shown in fig. 15, the semiconductor device 1700 includes a semiconductor chip 1610, a semiconductor chip 1620, a semiconductor chip 1630, a semiconductor chip 1640, a semiconductor chip 1650, and a semiconductor chip 1660, and an interposer 1710, an interposer 1720, an interposer 1730, an interposer 1740, an interposer 1750, and an interposer 1760.

The semiconductor chip 1610, the semiconductor chip 1620, the semiconductor chip 1630, the semiconductor chip 1640, the semiconductor chip 1650, and the semiconductor chip 1660 are components corresponding to the semiconductor chip 200 described above. Semiconductor chip 1610, semiconductor chip 1620, semiconductor chip 1630, semiconductor chip 1640, semiconductor chip 1650, and semiconductor chip 1660 are each a DSP, a GPU, a CPU, or the like. Interposer 1710, interposer 1720, interposer 1730, interposer 1740, interposer 1750, and interposer 1760 are formed from a copper, aluminum, or silicon substrate, or the like.

In the semiconductor device 1700, an interposer 1710, a semiconductor chip 1610, an interposer 1720, a semiconductor chip 1620, an interposer 1730, a semiconductor chip 1630, an interposer 1740, a semiconductor chip 1640, an interposer 1750, a semiconductor chip 1650, an interposer 1760, and a semiconductor chip 1660 are stacked in this order from bottom to top. That is, the interposer 1710 is disposed below the semiconductor chip 1610. The interposer 1720 is disposed between the semiconductor chip 1610 and the semiconductor chip 1620. Interposer 1730 is disposed between semiconductor chip 1620 and semiconductor chip 1630. Interposer 1740 is disposed between semiconductor chip 1630 and semiconductor chip 1640. The interposer 1750 is disposed between the semiconductor chip 1640 and the semiconductor chip 1650. The interposer 1760 is disposed between the semiconductor chip 1650 and the semiconductor chip 1660.

Specifically, the lower surface 1612 of the semiconductor chip 1610 is bonded to or pressure-bonded to the upper surface 1711 of the interposer 1710. The upper surface 1611 of the semiconductor chip 1610 is bonded or pressure-bonded to the lower surface 1722 of the interposer 1720. Similarly, the lower surfaces of semiconductor chip 1620, semiconductor chip 1630, semiconductor chip 1640, semiconductor chip 1650, and semiconductor chip 1660 are bonded or pressure-bonded to the upper surface of the lower one of interposer 1720, interposer 1730, interposer 1740, interposer 1750, and interposer 1760, and the upper surfaces of the upper ones of interposer 1730, interposer 1740, interposer 1750, and interposer 1760 are bonded or pressure-bonded to the lower surface of the upper one of interposer 1730, interposer 1740, interposer 1750, and interposer 1760.

A plurality of TSVs and a plurality of micro bumps are formed on the semiconductor chip 1610, the semiconductor chip 1620, the semiconductor chip 1630, the semiconductor chip 1640, the semiconductor chip 1650, and the semiconductor chip 1660 in the same manner as in the semiconductor device 10 shown in fig. 4 and the like. For example, the semiconductor chip 1660 is connected to the interposer 1760 via TSVs and microbumps, and the interposer 1760 is connected to the semiconductor chip 1650 via TSVs and microbumps. Similarly, semiconductor chip 1610, semiconductor chip 1620, semiconductor chip 1630, semiconductor chip 1640, and semiconductor chip 1650 are connected to the lower one of interposer 1720, interposer 1730, interposer 1740, interposer 1750, and interposer 1760 via a plurality of TSVs and a plurality of micro bumps. Further, in the exploded perspective view of fig. 16, the positions of the TSVs of the via group 1601 including a plurality of TSVs are schematically illustrated, and the microbumps are omitted in fig. 16.

On the upper surface 1711 of the interposer 1710, a plurality of grooves 1791 including the grooves 1791a, 1791b, 1791c, and 1791d, and a plurality of grooves 1792 including the grooves 1792a, 1792b, 1792c, and 1792d are formed. The grooves 1791 and 1792 can be formed by microfabrication using engraving, press working, or the like based on etching, NC, or laser processing.

The recess 1791 extends through from the side surface 1713 substantially perpendicular to the upper surface 1711 to the side surface on the opposite side. Thus, the side surface 1713 has a plurality of openings 1793 including an opening 1793a, an opening 1793b, an opening 1793c, and an opening 1793 d. The recess 1792 extends through the side surface 1714 substantially perpendicular to the upper surface 1711 and the side surface 1713 to the opposite side surface. Thus, the side 1714 has a plurality of openings 1794 including an opening 1794a, an opening 1794b, an opening 1794c, and an opening 1794 d. The side surfaces 1713 and 1714 form part of the outer side surfaces of the semiconductor device 1700.

The grooves 1791a, 1791b, 1791c and 1791d extend substantially parallel. The recesses 1792a, 1792b, 1792c and 1792d extend substantially parallel. The extending direction of the recess 1791 is substantially orthogonal to the extending direction of the recess 1792. Each of the recesses 1791 intersects any one of the recesses 1792. The via group 1601 penetrates through a region of the upper surface 1711 where the grooves 1791 and 1792 are not formed, specifically, a rectangular region surrounded by the grooves 1791 and 1792, in the stacking direction.

Interposer 1720, interposer 1730, interposer 1740, interposer 1750, and interposer 1760 have the same structure as interposer 1710. The interposer 1720, the interposer 1730, the interposer 1740, the interposer 1750, and the interposer 1760 are stacked in such a manner that the positions of the recess 1791 and the recess 1792 are aligned in the stacking direction. The through-hole group 1601 is formed in the regions where the grooves 1791 and 1792 are not formed in the interposer 1720, the interposer 1730, the interposer 1740, the interposer 1750, and the interposer 1760 in the entire stacking direction.

Thus, interposer 1710, interposer 1720, interposer 1730, interposer 1740, interposer 1750, and interposer 1760 each have a plurality of recesses 1791 or recesses 1792. Interposer 1710, interposer 1720, interposer 1730, interposer 1740, interposer 1750, and interposer 1760 each have a plurality of openings 1793 or openings 1794 formed in side 1713 or side 1714, which is a different surface from upper surface 1711 in which recess 1791 or recess 1792 is formed, and communicating with recess 1791 or recess 1792 formed in upper surface 1711.

The grooves 1791 and 1792 form a moving path of the refrigerant. The refrigerant flows into at least any one of the grooves 1791 and 1792 from the outside of the semiconductor device 1700 through at least any one of the openings 1793 and 1794, and flows out of at least any one of the grooves 1791 and 1792 to the outside of the semiconductor device 1700 through at least any one of the openings 1793 and 1794. As the refrigerant, a liquid refrigerant having high insulation and being inert, such as a fluorine compound, can be used. According to the semiconductor device 1700, the semiconductor chip 1610, the semiconductor chip 1620, the semiconductor chip 1630, the semiconductor chip 1640, the semiconductor chip 1650, and the semiconductor chip 1660 can be cooled from below.

Fig. 17 schematically shows a perspective view of a computer 1810 provided with a semiconductor device 1700. As shown in fig. 17, a semiconductor device 1700 is mounted on a substrate 1702. The board 1702 is mounted on the main board 1812. On the main substrate 1812, in addition to the semiconductor device 1700, electronic circuits such as various IC chips, a power supply circuit, and a memory are mounted; electronic components such as resistors and capacitors; and an electronic component such as a connector for mounting an external device such as an external memory.

Fig. 18 schematically shows a computer system 1840 provided with a computer unit 1800 and a cooling system 1850. The computer unit 1800 includes a plurality of computers having the same configuration as the computer 1810 and a mount 1820 on which the plurality of computers are mounted. The cooling system 1850 includes an immersion fluid tank 1860 and a refrigerant 1870. The computer unit 1800 is immersed in a refrigerant 1870 that fills the immersion fluid tank 1860. The arrow 1890 in fig. 18 indicates the direction in which the computer unit 1800 is immersed in the immersion fluid tank 1860.

In the computer unit 1800, the recess 1791 or the recess 1792 of the semiconductor device 1700 are fluidly connected to each other through the inner space of the immersion fluid tank 1860 filled with the refrigerant 1870. Therefore, the refrigerant 1870 in the immersion liquid tank 1860 flows from the outside of the semiconductor device 1700 into the groove 1791 or the groove 1792 through at least any one of the opening 1793 and the opening 1794 of the semiconductor device 1700, and flows out from the groove 1791 or the groove 1792 to the outside of the semiconductor device 1700 through any one of the opening 1793 and the opening 1794.

The refrigerant 1870 can flow in the immersion fluid tank 1860 by natural convection using heat generated in the computer unit 1800. Refrigerant 1870 can also be pumped to flow within the dip tank 1860. In the semiconductor device 1700, openings including the opening 1793 and the opening 1794 are formed in four side surfaces of the semiconductor device 1700 including the side surface 1713 and the side surface 1714, and each of the openings communicates with any one of the grooves 1791 and 1792. Therefore, regardless of the direction of flow of the refrigerant 1870 in the immersion groove 1860, the refrigerant 1870 can flow into the semiconductor device 1700 from any one of the openings and flow out of the semiconductor device 1700 from any one of the openings.

According to the semiconductor device 1700 described in association with fig. 15 to 18, the concave grooves 1791 and 1792 can be used as a moving path of the immersion refrigerant, and thus a cooling pipe using a heat pipe or the like is not required. In addition, it is not necessary to form the refrigerant path in the stacking direction. In addition, it is not necessary to provide the semiconductor device 1700 with a pump for moving the refrigerant in the semiconductor device 1700.

In the semiconductor device described above, the semiconductor chip and the interposer may be bonded by pressure bonding without using an adhesive. In addition, from the viewpoint of yield, it is often preferable that the groove serving as a moving path of the refrigerant is formed in the interposer. However, in the semiconductor device described above, a recess serving as a moving path of the refrigerant may be formed in a surface of the semiconductor chip opposite to the surface on which the circuit is mounted.

As described above, there is provided a three-dimensional laminated integrated circuit in which a groove through which a refrigerant passes is formed in a copper or aluminum plate or a silicon substrate without using a cooling pipe, and upper and lower layers are connected to each other through a hole in a vertical direction, thereby forming a pipe. Further, by forming longitudinal and transverse grooves through which a coolant passes without using a cooling pipe on a copper, aluminum, or silicon substrate and opening the grooves to extend to the end of the substrate, the coolant is allowed to enter and be released from each layer from the peripheral surface of the semiconductor by immersion liquid to cool the inside of the semiconductor, and there is no need to form a pipe through which the coolant flows in the layer direction.

The vertical and horizontal grooves avoid the portions constituting the TSV. Provided is a three-dimensional laminated integrated circuit wherein the structure of a cooling system is simplified by circulating a refrigerant between each layer and the outside by means of a groove provided up to the end of an interposer. In the case where a layer of copper or aluminum is inserted as a member constituting the recess, it is necessary to fill the portion of the hole of the copper or aluminum plate constituting the portion of the TSV in the vertical direction with a silicon substrate.

Not only the CPU, GPGPU, and the computation portion of the central processing unit for virtual currency mining, but also the HBM is mounted on the three-dimensional semiconductor of the cooling method of this embodiment, or a memory layer is inserted between layers. When the memory layer is sandwiched, only the operation layer and the memory layer need to be connected by the TSV, so that the stray capacitance of the memory bus is minimized, and ultra-high speed operation is possible.

Particularly, when used for excavation or the like, as in a large-scale apartment, by providing TSVs for redundant data paths at a plurality of locations and overlapping a plurality of processor arrays including defective locations, defective locations may be present in the data paths, and the processor elements may be used so that the defective locations gradually increase in three-dimensional mounting of a fine semiconductor such as 5nm that initially includes the defective locations.

Fig. 19 schematically outputs the structure of the above-described groove. The grooves through which the refrigerant passes are formed by cutting the substrate layer by etching, engraving, or computer NC, or by punching grooves into the substrate layer in a longitudinal and transverse direction, and the grooves through which the refrigerant passes are V-shaped, U-shaped, or "コ" shaped.

Fig. 20 schematically shows a structure for preventing the decomposition of the three-dimensional cooling semiconductor. As a member that not only contacts the BGA but also prevents the three-dimensional cooling semiconductor from being decomposed by the pressure of cavitation or the like, metal plates such as aluminum plates are prepared on the upper and lower sides (the back surface of the PCB and the back surface of the semiconductor) and are clamped at four or more points with clips. An insulator or the like is interposed between the aluminum plate and the PCB.

Fig. 21 schematically shows a structure for preventing cavitation of the refrigerant. In spite of the immersion liquid, cavitation is prevented by mounting a connector on either side of the semiconductor and injecting the solution under a positive pressure by means of a pump. The operation can be performed at a temperature at which cavitation is not caused by the immersion liquid.

Fig. 22 schematically shows a structure for preventing cavitation of the refrigerant. In the case of a groove having only one direction, a seal is attached, and an inlet and an outlet are provided to prevent cavitation in a sealed manner rather than immersion liquid. Fig. 23 schematically shows a structure for preventing cavitation of the refrigerant. In the case of an immersion liquid, the discharge port is opened in the liquid by having only the injection port in one direction or in a vertically and horizontally open type, and cavitation is prevented by applying a positive pressure from the injection port.

Fig. 24 schematically shows a structure for preventing occurrence of cavitation and working. An acoustic sensor is provided, and the output of the acoustic sensor is used to control the clock frequency to prevent cavitation erosion from occurring and to operate the device. As a member for preventing the three-dimensional cooling of the semiconductor from being decomposed by the positive pressure generated by the injection of the coolant for preventing the cavitation, metal plates such as aluminum plates are prepared on the upper and lower sides (the back surface of the PCB and the back surface of the semiconductor), and are clamped at four or more points by clamps. An insulator or the like is interposed between the aluminum plate and the PCB. The whistle generated by the boiling of the refrigerant is detected by the sound sensor, and the frequency is controlled within a range where the whistle is not generated.

Fig. 25 schematically shows a structure for preventing whistling resonance. Fig. 26 schematically shows another configuration for preventing whistling resonance. Fig. 27 schematically shows another configuration for preventing whistling resonance. In order to prevent resonance, the depth and length of the groove can be changed to prevent whistling resonance. In this case, the semiconductor may have a trapezoidal shape in order to change the length of the groove. In the case where the longitudinal and lateral grooves are present, the trapezoidal shape is irregular in order to prevent the longitudinal and lateral resonances from occurring.

Fig. 28 schematically shows a semiconductor package for cooling a three-dimensional stacked integrated circuit by immersion. The semiconductor package is a BGA or quasi-BGA package, and has a structure in which pads of a geometric shape (circular, quadrangular, triangular, star-shaped, etc.) that contact the BGA are also provided on the surface of the semiconductor package and can be stacked up and down, and is mounted by immersion using the gaps of the contact grid. A semiconductor package and a cooling method are provided, in which a ball grid of a BGA is mounted on the lower part of a semiconductor, and a pad having a geometrical shape (circular, quadrangular, triangular, star-shaped, etc.) in contact with the BGA is mounted on the upper surface of the semiconductor. The single-layer laminated integrated circuit thus designed was stacked one on top of another, and a three-dimensional laminated integrated circuit was configured on the premise of immersion. The semiconductors are stacked one on top of the other and held pressed against misalignment. The coolant flows in the gaps of the ball grid of the metal contacts. Since the data path corresponds to the thickness in the vertical direction including the contact, high-speed interconnection can be realized, and the essence of the present invention can be realized without changing the conventional semiconductor manufacturing method. The pads may also be contacted by springs.

The shape of the semiconductor shown in fig. 28 is intended to connect vertical buses of a central processing unit, a GPGPU, a semiconductor memory, and an HBM for cooling by immersion liquid, and although there are cases where pads such as pads are mounted on the semiconductor, it is merely placed on the semiconductor in a mother-and-child manner, but this is not the case in the present invention, in which immersion liquid is actively used in gaps of ball grids of BGAs, and thus, as a cooling structure, it is intended to cool by immersion liquid using gaps of BGA packages stacked in a mother-and-child structure, and the connection of terminals and contacts of vertical BGAs, etc., constitutes a data bus in the vertical direction. Therefore, the data bus is extended to the outside of the semiconductor, but only a minimum distance is required, and a high-frequency bus operation can be performed. That is, the object of the method for cooling a three-dimensional semiconductor according to the present invention is to increase the speed of the operation of a stacked memory or processor by using the vertical connection of semiconductors stacked on pads as a vertical bus.

Fig. 29, 30, and 31 show an example of the embodiment according to claim 26. The cooling method by a refrigerant for the three-dimensional stacked integrated circuit according to claim 26 and the three-dimensional stacked integrated circuit using the cooling method are the semiconductor according to claim 13, wherein electrodes are provided at corners or edges or both of the semiconductor in which BGA packages are stacked, and the electrodes are brought into contact with the electrodes, whereby GND having low impedance and stable power supply potential are supplied. The metal rod-like electrode may have a structure in which a capacitor is provided between both the positive electrode and the negative electrode.

Fig. 31 is the semiconductor device according to claim 26, which may be provided with a cap having a function of connecting electrodes to each other in order to press the stacked semiconductor devices and supply a stable potential with low impedance. The cover may also be provided with a spring or the like for pressing the semiconductor. In addition, the cover may have a path for connecting the respective potentials of the positive electrode and the negative electrode to each other.

Fig. 36 and 37 show an example of the embodiment of claim 28. The cooling method by a refrigerant for the three-dimensional stacked integrated circuit according to claim 28 and the three-dimensional stacked integrated circuit using the cooling method are the semiconductors according to claim 10, claim 11, or claim 12, and the first layer may be a normal FC-BGA substrate without a groove. The semiconductor of the first layer and the FC-BGA substrate of the first layer are connected by a normal FC pad. Between the FC-BGA substrate of the first layer and the semiconductor of the first layer, in order to prevent water from entering into the FC pad between the FC pad and the semiconductor of the first layer, the periphery of the FC pad is reinforced with underfill (underfill) or the like.

Fig. 38 is the semiconductor device according to claim 10, claim 11, or claim 12, in which the stacked portion of the interposer and the semiconductor chip is reinforced with underfill or the like for preventing the FC pad from being impregnated with the refrigerant.

In addition, FIG. 39, FIG. 40, FIG. 41, FIG. 42, FIG. 43 and FIG. 45 are the semiconductor of claim 32,

the semiconductor device according to claim 13, wherein the package having pads on the upper surface thereof according to claim 13 for vertical connection to the BGA terminals of the upper layer is composed of an FC-BGA substrate having a cavity for housing the semiconductor device and a lid of the heat sink.

A part different from the typical FC-BGA substrate is that a geometrically shaped pad electrode (pad) for connection with the BGA package of the previous layer is provided on the upper surface except the dimple. The portion of the dimple has an FC bump bonded to the semiconductor. The portion to be added to a normal FC-BGA substrate is a portion in which a substrate having a hole in the center for receiving a semiconductor is added, and a pad (land) extending upward in the form of a through hole and connected to a BGA bump of an upper package is provided on the surface.

The reason why no BGA pad is provided on the upper surface of the portion of the semiconductor surface is to provide a heat sink on the recess of the substrate of the semiconductor portion and to form a cap by applying a compound.

The pit portion may be configured as follows: in the manufacturing process of the substrate, a substrate having a hole for receiving a semiconductor in the center is bonded, and the substrate constituting the lower portion of the package and a pad (land) portion constituting the upper portion are connected to each other by formation of a through hole. When the distances between the BGA bumps of the first layer and the second layer and thereafter and the pads (pads) are the same, the BGA bumps of all layers and the pads may be vertically connected through the through holes to constitute the internal bus lines of the three-dimensional semiconductor of this configuration.

Alternatively, the semiconductor chip may be directly bonded to the FC-BGA substrate of the upper cover by FC balls, and the substrate and the semiconductor chip may be vertically bonded by FC balls.

In addition, fig. 39 and 41 show the semiconductor according to claim 13, and the semiconductor itself may be the same in all layers. The first layer of FC-BGA substrate has pads connected to the upper layer of the FC-BGA substrate, and the upper cover of the FC-BGA substrate has pads through it. The BGA of the edge portion of the FC-BGA substrate has a pad which penetrates vertically in the substrate and is connected to the upper cover. The upper cover has an electrically through pad. In the second and subsequent layers, the pads of the power supply of claim 26 may also be provided on the side of the substrate.

Fig. 39, 40, 41, 42, 43, and 45 illustrate an example of the semiconductor according to claim 33, and the semiconductor itself may be the same in all layers in the semiconductor according to claim 32. The first layer of FC-BGA substrate has pads connected to the upper layer of the FC-BGA substrate, and the upper cover of the FC-BGA substrate has pads through it. The BGA of the second layer and the edge portion of the FC-BGA substrate after the second layer has a pad longitudinally penetrating the substrate and connected to the upper lid.

The second layer and the subsequent layers soldered to the first layer of the PCB may be formed of BGA with small bumps.

The BGA pads on the upper surface of the first layer and the second and subsequent BGA bumps and pads are used for interlayer coupling, and smaller bumps and bump spacings than the first layer may also be used. The BGA pads on the upper surface of the first layer and the BGA bumps and pads of the second and subsequent layers may or may not include external bus connections.

The interconnection to the external bus may also be undertaken by only the lowest chip. When the BGA connection of the small bump does not include the external bus connection, the signal propagation distance becomes extremely short, and thus a high-speed clock operation can be performed. Since the signal is not connected to the terminal, the signal is operated in consideration of the reflection similar to the PCI bus. Since the BGA is formed of small bumps, holes may be formed in the upper FC-BGA substrate and the lower FC-BGA substrate to allow stacking by means of guide pins or the like in order to improve the alignment accuracy of the stacking.

In the power supply method according to claim 26 or 27, an electrode may be provided in the hole of the leader pin by plating, and the leader pin may be used as a rod for supplying power.

As stated in claim 33, the second and subsequent layers of the semiconductor of claim 32 other than the first layer soldered to the PCB may also be comprised of BGA of small bumps. The FC pads may pass only signals for the internal bus lines on the upper side of the substrate of the first layer and on the second and subsequent layers. The interconnection to the external bus may also be undertaken by the lowest chip. Since the BGA is formed of small bumps, holes may be formed in the upper FC-BGA substrate and the lower FC-BGA substrate to allow stacking by means of guide pins or the like in order to improve the alignment accuracy of the stacking.

An electrode may be provided in the hole of the leader pin by plating, and the leader pin may also serve as a rod for supplying power. As shown in fig. 40, in the power supply method for reducing the impedance generated by the pressing cap according to claim 27, a guide pin may be used as the electrode.

(Here, 31 is mentioned alongside 32 because of noise)

In addition, fig. 39 and 41 show the semiconductor of claim 31 or claim 32, and a hole may be formed in the FC-BGA substrate of the upper lid, a heat sink may be mounted for cooling, and a compound may be applied between the semiconductor and the heat sink.

Fig. 39, 40 and 41 show the semiconductor device according to claim 31, 32 and 34, wherein the BGA bumps with small bumps according to claim 33 are not used, the second layer and the subsequent layers are the same as the first layer, and the BGA bumps on the heat sink portion are removed from the BGA with the package, whereby the BGA bumps for external connection buses are arranged on the inner side and the outer side is the BGA bumps for internal connection.

Fig. 40 shows an example of mounting the semiconductor device according to claim 27. The semiconductor device according to claim 26, wherein a cover having a function of connecting the electrodes to each other may be provided in order to press the stacked semiconductor device and supply a stable potential with low impedance. The cover may also be provided with a spring or the like for pressing the semiconductor. In addition, the cover may have a path for connecting the respective potentials of the positive electrode and the negative electrode to each other.

Fig. 41 shows an example of mounting the semiconductor device according to claim 32. A structure in which the substrate of the upper cover is longitudinally connected to the substrate of the lower cover is shown, but the connection of the first layer is omitted. In addition, the connection to the semiconductor chip is omitted in each connection.

The semiconductor device according to claim 13, wherein the package having pads on the upper surface thereof according to claim 13 for vertical connection to the BGA terminals of the upper layer is composed of an FC-BGA substrate having a cavity for housing the semiconductor device and a lid of the heat sink.

A part different from the typical FC-BGA substrate is that a geometrically shaped pad electrode (pad) for connection with the BGA package of the previous layer is provided on the upper surface except the dimple. The portion of the dimple has an FC bump bonded to the semiconductor. The portion to be added to a normal FC-BGA substrate is a portion in which a substrate having a hole in the center for receiving a semiconductor is added, and a pad (land) extending upward in the form of a through hole and connected to a BGA bump of an upper package is provided on the surface.

The reason why no BGA pad is provided on the upper surface of the portion of the semiconductor surface is to provide a heat sink on the recess of the substrate of the semiconductor portion and to form a cap by applying a compound.

The pit portion may be configured as follows: in the manufacturing process of the substrate, a substrate having a hole for receiving a semiconductor in the center is bonded, and the substrate constituting the lower portion of the package and a pad (land) portion constituting the upper portion are connected to each other by formation of a through hole. When the distances between the BGA bumps of the first layer and the second layer and thereafter and the pads (pads) are the same, the BGA bumps of all layers and the pads may be vertically connected through the through holes to constitute the internal bus lines of the three-dimensional semiconductor of this configuration.

Fig. 42 shows an example of mounting the semiconductor device according to claim 32. Although the structure of the BGA package one layer is shown as viewed from the back surface, all BGA bump electrodes are mounted on the package of the first layer, but the BGA bump electrodes are not mounted on the second layer and the layers subsequent thereto of the semiconductor package at the central portion of the second layer and the layers subsequent thereto where the heat sink is present, thereby avoiding contact with the heat sink.

The reason why no BGA pad is provided on the upper surface of the portion of the semiconductor surface is to provide a heat sink on the recess of the substrate of the semiconductor portion and to form a cap by applying a compound.

The pit portion may be configured as follows: in the manufacturing process of the substrate, a substrate having a hole for receiving a semiconductor in the center is bonded, and the substrate constituting the lower portion of the package and a pad (land) portion constituting the upper portion are connected to each other by formation of a through hole. When the distances between the BGA bumps of the first layer and the second layer and thereafter and the pads (pads) are the same, the BGA bumps of all layers and the pads may be vertically connected through the through holes to constitute the internal bus lines of the three-dimensional semiconductor of this configuration.

Fig. 43 shows an example of mounting the semiconductor device according to claim 32. The structure of the second layer of the BGA laminated semiconductor is shown viewed from the back side.

The semiconductor device according to claim 13, wherein the package having pads on the upper surface thereof according to claim 13 for vertical connection to the BGA terminals of the upper layer is composed of an FC-BGA substrate having a cavity for housing the semiconductor device and a lid of the heat sink.

A part different from the typical FC-BGA substrate is that a geometrically shaped pad electrode (pad) for connection with the BGA package of the previous layer is provided on the upper surface except the dimple. The portion of the dimple has an FC bump bonded to the semiconductor. The portion to be added to a normal FC-BGA substrate is a portion in which a substrate having a hole in the center for receiving a semiconductor is added, and a pad (land) extending upward in the form of a through hole and connected to a BGA bump of an upper package is provided on the surface.

The reason why no BGA pad is provided on the upper surface of the portion of the semiconductor surface is to provide a heat sink on the recess of the substrate of the semiconductor portion and to form a cap by applying a compound.

The pit portion may be configured as follows: in the manufacturing process of the substrate, a substrate having a hole for receiving a semiconductor in the center is bonded, and the substrate constituting the lower portion of the package and a pad (land) portion constituting the upper portion are connected to each other by formation of a through hole. When the distances between the BGA bumps of the first layer and the second layer and thereafter and the pads (pads) are the same, the BGA bumps of all layers and the pads may be vertically connected through the through holes to constitute the internal bus lines of the three-dimensional semiconductor of this configuration.

Fig. 44 shows an example of mounting the semiconductor device according to claim 30.

In the case of the semiconductor device according to claim 10, claim 11, or claim 12, the grooves through which the refrigerant passes and the regions having the FC pads of the TSVs do not necessarily have to be present alternately with each other, and since the regions constituting the semiconductor device disappear if the TSV regions in the vertical direction are too large, the number of the regions having the FC pads of the TSVs may be limited. It is also possible to have the groove adjacent to the groove.

Fig. 45 shows an example of mounting the semiconductor device according to claim 34. The semiconductor device of claim 32 or claim 33, wherein the package is formed by an FC-BGA substrate having the same recess for receiving the semiconductor chip as the first layer in the second and subsequent layers, and the package is sealed with a heat sink together with the compound by using BGA bumps of the same size as the small bumps of claim 33 in all layers instead of using BGA bumps of the small bumps of claim 33. By removing the BGA bumps of the portion of the heat sink covered by the package, disposing the BGA bumps for external connection bus lines inside the lower portion of the chip which is blocked by the chip and does not penetrate vertically, and disposing the BGA bumps for interconnection between the chips outside, it is possible to remove only a part of the BGA bumps for external connection, and to constitute the second layer and the subsequent layers by the package based on the same semiconductor in all the layers and the same substrate in all the layers except that a part of the BGA bumps is not present.

Fig. 46 shows an example of mounting the semiconductor device according to claim 35. In the case of the semiconductor device according to claim 10, claim 11, claim 12, claim 28, claim 29, or claim 30, grooves for passing a refrigerant are not necessarily formed in the interposer, and grooves may be formed in the back surface of the semiconductor device. In this case, the interposer serves to pass the TSV and protect the surface of the compound-coated semiconductor. The stacked semiconductors and interposers may be fixed to each other by water-proofing with an underfill adhesive, an adhesive (coating), an adhesive film, or the like. Thus, the semiconductor becomes thinner corresponding to the absence of the grooves in the interposer, and the thermal resistance of the interposer decreases.

According to the semiconductor device described above, the stacked plurality of semiconductor chips can be efficiently cooled. Therefore, a plurality of semiconductor chips can be stacked. This can shorten the physical distance of the bus line connecting the semiconductor chips, thereby improving the processing capability of the semiconductor device and suppressing an increase in power consumption and a significant increase in temperature.

The present invention has been described above with reference to the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes and modifications can be made to the above embodiments. It is apparent from the description of the claims that the embodiments in which the above modifications or improvements are performed are also included in the technical scope of the present invention.

The execution order of the operations, steps, and stages in the devices, systems, programs, and methods shown in the claims, the description, and the drawings is not particularly explicitly indicated as "before", "first", and the like, and it should be noted that the execution order can be arbitrarily realized unless the output of the previous process is used in the subsequent process. Even if the description is made using "first", "next", and the like for convenience sake in the operation flows in the claims, the description, and the drawings, it does not mean that the operations are necessarily performed in this order.

Description of the reference numerals

10: a semiconductor device; 20: a via hole; 22: a group of through holes; 30: a micro-bump; 50: a logic block; 60: a memory block; 100: an interpolator; 101. 102: kneading; 103: one end; 104. 107: a groove; 109: the other end; 110: an interpolator; 111. 112, 112: kneading; 113: one end; 114: a groove; 115: a first groove portion; 116: a second groove portion; 117: a groove; 118. 119: a through hole; 120: an interpolator; 121. 122: kneading; 123: one end; 124: a groove; 125: first groove portion, 126: a second groove portion; 127: a groove; 128. 129: a through hole; 130. 131, 132: a refrigerant passage; 150. 160, 170: an interpolator; 190: a cooling device; 200. 210, 220: a semiconductor chip; 240: a substrate; 241. 242: a main face; 250. 260, 270: a memory chip; 300: a surrounding groove; 301. 302, 303: a groove; 330: an area; 400. 410, 420: an interpolator; 423: one end; 404. 414, 424: a groove; 429: the other end; 500. 540 and 550: a heat pipe; 600: a semiconductor device; 1100. 1110, 1120: an interpolator; 1300: a groove; 1500: a heat pipe; 1510. 1520: a straight line portion; 1530: a curved portion; 1610. 1620, 1630, 1640, 1650, 1660: a semiconductor chip; 1601: a group of through holes; 1611: an upper surface; 1612: a lower surface; 1700: a semiconductor device; 1702: a substrate; 1711: an upper surface; 1713. 1714: a side surface; 1722: a lower surface; 1710. 1720, 1730, 1740, 1750, 1760: an interpolator; 1791. 1792, and (2) preparing: a groove; 1793. 1794: an opening; 1800: a computer unit; 1810: a computer; 1812: a main substrate; 1820: a mounting seat; 1840: a computer system; 1850: a cooling system; 1860: a liquid immersion tank; 1870: a refrigerant; 1890: an arrow; 2900: a cover; 2910: an electrode holding member; 3020: a clamping member; 3030: an electrode; 3200: a positive electrode; 3210: a negative electrode; 3220: an electrode holding member; 3240: a capacitor; 3500: a spring; 3600: an interposer without covers, grooves, and electrodes; 3610: a slotted interposer; 3620: a first layer of FC-BGA conversion substrate; 3630: a semiconductor chip of a first layer; 3770: BGA bumps; 3800: underfill adhesive; 3810: an FC pad; 3820: an interpolator; 3900: an FC-BGA conversion substrate, an open upper portion of a semiconductor; 3910: FC-BGA conversion substrate, lower portion; 3930: a semiconductor chip; 3940: BGA bumps; 3950: a hole for passing a metal rod for alignment or a metal rod having a power supply function; 3960: a quadrangular hole is formed below the radiator and the radiator; 4000: a cover; 4010: a hole into which the metal plate spring is inserted; 4020: an electrode; 4030: a spring; 4040: a capacitor; 4100: a semiconductor package of a first layer; 4110: a semiconductor package of a second layer; 4120: a small BGA bump; 4130: a metal bar for alignment; 4140: a heat sink; 4150: a complex; 4200: a first FC-BGA conversion substrate; 4210: BGA bumps; 4220: the location of the heat sink; 4230: a hole for passing the metal rod for alignment; 4300: areas that avoid the heat spreader and do not have a BGA; 4400: a groove; 4410: an FC ball; 4420: underfill adhesive; 4430: an interpolator; 4610: an interposer without a groove capable of connecting the TSV; 4620: the back surface avoids the semiconductor with the groove for the refrigerant to pass through, which is chiseled on the TSV.