阅读说明：本技术 功率覆盖结构及其制作方法 (Power covering structure and manufacturing method thereof ) 是由 A.V.高达 S.S.乔汉 P.A.麦康奈利 于 2014-03-14 设计创作，主要内容包括：本发明涉及功率覆盖结构及其制作方法。一种功率覆盖(POL)结构,包括POL子模块。POL子模块包括介电层和具有附接到介电层上的顶表面的半导体装置。半导体装置的顶表面具有形成在其上的至少一个接触垫。POL子模块还包括金属互连结构,其延伸穿过介电层,且电性地联接到半导体装置的至少一个接触垫上。传导垫片联接到半导体装置的底表面上,且热界面的第一侧联接到传导垫片上。散热件联接到电绝缘的热界面的第二侧上。(A power overlay (PO L) structure includes a PO L sub-module, the PO L sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer, the top surface of the semiconductor device having at least one contact pad formed thereon, the PO L sub-module further includes a metal interconnect structure extending through the dielectric layer and electrically coupled to the at least one contact pad of the semiconductor device.)

1. A module for a power overlay structure, comprising:

a dielectric layer;

a first member having a height defined between a first surface and a second surface thereof, wherein the first surface of the first member is attached to the dielectric layer;

at least one additional component having a height defined between a first surface and a second surface thereof, wherein the first surface of the at least one additional component is attached to the dielectric layer; and

a conductive pad assembly having a top surface, a bottom surface, and at least one conductive contact layer, wherein a first portion of the bottom surface of the conductive pad assembly is coupled to the second surface of the first component via the at least one conductive contact layer, and a second portion of the bottom surface of the conductive pad assembly is coupled to the second surface of the at least one additional component via the at least one conductive contact layer;

wherein a first portion of a bottom surface of the conductive shim assembly is positioned at a first elevation within the module and a second portion of the bottom surface of the conductive shim assembly is positioned at a second elevation within the module, the first elevation being different than the second elevation; and is

Wherein only one of the at least one conductive contact layer is positioned between the top surface of the conductive patch assembly and the second surface of the at least one additional component.

2. The module of claim 1, wherein the first member and the at least one additional member comprise semiconductor devices.

3. The module of claim 1, wherein the first surface of the first member has at least one contact pad formed thereon; and is

Wherein the first surface of the at least one further component has at least one contact pad formed thereon.

4. The module of claim 3, further comprising a metal interconnect structure extending through the dielectric layer and electrically coupled to the at least one contact pad of the first member and the at least one contact pad of the at least one additional member.

5. The module of claim 1, wherein only one of the at least one conductive contact layer is positioned between a top surface of the conductive gasket assembly and the second surface of the first member.

6. The module of claim 1, wherein the conductive patch assembly includes at least one conductive patch having a conductive element; and is

Wherein the at least one conductive contact layer is coupled to the at least one conductive pad and comprises one of a solder material, a conductive adhesive, and a sintered silver layer.

7. The module of claim 1, further comprising a thermal interface coupled to a top surface of the conductive shim assembly.

8. The module of claim 7, wherein the thermal interface is thermally conductive.

9. The module of claim 7, further comprising: an enclosure positioned around the first member, the at least one additional member, and the conductive pad assembly in a space between the dielectric layer and the thermal interface.

10. The module of claim 1, wherein the at least one additional component comprises:

a second member coupled to the conductive pad assembly; and

an electrical device decoupled from the conductive pad assembly.

11. The module of claim 1, wherein the first member comprises a first semiconductor device;

wherein the at least one further member comprises:

a second semiconductor device coupled to a second portion of the bottom surface of the conductive pad assembly; and

a third semiconductor device coupled to a third portion of the bottom surface of the conductive pad assembly; and is

Wherein the first semiconductor device, the second semiconductor device, and the third semiconductor device have different heights.

12. The module of claim 11, wherein the conductive gasket assembly comprises:

a first conductive pad coupled to the first semiconductor device;

a second conductive pad coupled to the second semiconductor device and the first conductive pad; and

a third conductive pad coupled to a third semiconductor device and the first conductive pad;

wherein a thickness of the second conductive pad is different from a thickness of the third conductive pad.

13. The module of claim 1, wherein the conductive pad assembly comprises a conductive pad having a stepped configuration; and is

Wherein the at least one conductive contact layer comprises:

a first conductive contact layer coupling the first member to the conductive pad; and

a second conductive contact layer coupling the at least one additional component to the conductive pad.

14. The module of claim 13, wherein the conductive pad comprises a first portion and a second portion; the second portion comprises a second portion;

wherein the first portion of the conductive pad is substantially aligned with the first member within the module;

wherein the second portion of the conductive pad is substantially aligned with the at least one additional component within the module; and is

Wherein the first portion of the conductive pad has a thickness different from a thickness of the second portion of the conductive pad.

15. The module of claim 14, wherein a top surface of the first portion of the conductive pad and a top surface of the second portion of the conductive pad are coplanar.

16. The module of claim 1, wherein the conductive gasket assembly comprises:

a first conductive pad having a bottom surface coupled to the second surface of the first member; and

a second conductive pad having a bottom surface coupled to the second surface of the at least one additional component;

wherein a bottom surface of the second conductive pad is coupled to a top surface of the first conductive pad.

17. The module of claim 16, wherein a width of the second conductive pad is different than a combined width of the first member and the at least one additional member.

18. The module of claim 16, wherein a top surface of the second conductive pad is flat.

19. A module for a power overlay structure, comprising:

a first member having a height defined between a first surface and a second surface thereof;

a second member having a height defined between a first surface and a second surface thereof; and

a conductive pad having a stepped configuration, wherein a first portion of the conductive pad has a thickness that is different from a thickness of a second portion of the conductive pad;

wherein a bottom surface of the first portion of the conductive pad is coupled to the second surface of the first member;

wherein a bottom surface of the second portion of the conductive pad is coupled to the second surface of the second member; and is

Wherein a height of the first member is different from a height of the second member.

20. The module of claim 19, wherein the first member and the second member comprise semiconductor devices.

21. The module of claim 19, wherein the first surface of the first member has at least one contact pad formed thereon; and is

Wherein the first surface of the second member has at least one contact pad formed thereon.

22. The module of claim 19, wherein the conductive gasket comprises a conductive element.

23. The module of claim 19, further comprising a conductive contact layer coupling the conductive gasket to the first member and the second member.

24. A module for a power overlay structure, comprising:

a conductive pad assembly including a first conductive pad coupled to a second conductive pad;

a first member having a first surface and a second surface, the second surface coupled to the bottom surface of the first conductive pad; and

a second member having a first surface and a second surface, the second surface coupled to the bottom surface of the second conductive pad;

wherein the first member and the second member have different heights.

25. The module of claim 24, wherein the first member and the second member comprise semiconductor devices.

26. The module of claim 24, wherein the first surface of the first member includes at least one contact pad; and is

Wherein the first surface of the second member comprises at least one contact pad.

27. The module of claim 24, wherein the width of the second conductive pad is different than the width of the first conductive pad.

28. The module of claim 24, wherein the first and second conductive pads comprise one of copper, molybdenum, and aluminum.

29. The module of claim 24, wherein the second surface of the second member and the top surface of the first conductive pad are substantially coplanar.

30. The module of claim 24, further comprising:

a first conductive contact layer coupling the first member to the first conductive pad; and

a second conductive contact layer coupling the second conductive pad to the second member and the first conductive pad.

Technical Field

Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices, and more particularly to power overlay (PO L) package structures including improved thermal interfaces.

Background

Many power semiconductor devices are used in high voltage power applications and are designed to carry large amounts of current and support large voltages.

The overall structure of a prior art power overlay (PO L) structure 10 is shown in fig. 1. a standard manufacturing process for the PO L structure 10 generally begins with one or more power semiconductor devices 12 being placed on a dielectric layer 14 by an adhesive 16. metal interconnects 18 (e.g., copper interconnects) are then electroplated onto the dielectric layer 14 to form direct metal connections with the power semiconductor devices 12. the metal interconnects 18 may be in the form of low profile (e.g., less than 200 microns thick) planar interconnect structures that provide for the formation of input/output (I/O) systems 20 to and from the power semiconductor devices 12. for connection to external circuits, such as BGA, by creating a second level interconnect to a printed circuit board, for example, current PO L packages use Ball Grid Arrays (BGA) or land grid arrays (L GA).

The heat sink 22 is also typically included in the PO L structure 10 to provide a means of removing heat generated by the semiconductor device 12 and protecting the device 12 from the external environment the heat sink 22 is thermally coupled to the device 12 using a direct copper clad (DBC) substrate 24 as shown, the DBC substrate 24 is positioned between the upper surface of the semiconductor device 12 and the lower surface of the heat sink 22.

The DBC substrate 24 is a prefabricated component that includes a non-organic ceramic substrate 26, such as alumina, with an upper copper sheet 28 and a lower copper sheet 30 bonded to both sides thereof by a direct copper-clad interface or braze layer 31. The lower copper sheet 30 pattern of the DBC substrate 24 is determined to form a number of conductive contact areas before the DBC substrate 24 is attached to the semiconductor device 12. Typically, the DBC substrate may have an overall thickness of about 1 mm.

During the manufacturing process of the PO L structure 10, solder 32 is applied to the surface of the semiconductor device 12 the DBC substrate 24 is then dropped onto the solder 32 to align the patterned portion of the lower copper sheet 30 with the solder 32 after the DBC substrate 24 is coupled to the semiconductor device 12, an underfill technique is used to apply a dielectric organic material 34 into the space between the adhesive layer 16 and the DBC substrate 24 to form the PO L sub-module 36 the thermal pad or grease 38 is then applied to the upper copper layer 28 of the DBC substrate 24.

The use of DBC substrates in the PO L structure 10 has a number of limitations, first, the material properties of the copper and ceramic materials of the DBC substrate impose inherent limitations on the design of the DBC substrate, for example, due to the inherent rigidity of the ceramic and the difference in the coefficient of thermal expansion of the copper and ceramic materials of the DBC substrate 24, the copper sheets 28,30 must be kept relatively thin to avoid excessive stress placed on the ceramic caused by large temperature fluctuations in the copper material, furthermore, the DBC substrate 24 does not facilitate the manufacture of PO L packages for semiconductor devices having different heights because the surface of the lower copper layer facing the DBC substrate 24 of the semiconductor device 12 is flat.

Additionally, because the DBC substrate 24 is fabricated prior to assembly with the remainder of the components of the PO L structure, the dielectric filler or epoxy substrate surrounding the semiconductor device 12 is applied using an underfill technique after the DBC substrate 24 is coupled to the semiconductor device 12.

It would therefore be desirable to provide a PO L structure having an improved thermal interface that overcomes the aforementioned structural and processing limitations of known PO L structures incorporating DBC substrates it would also be desirable for such PO L structures to address semiconductor devices of varying thicknesses while minimizing the cost of the PO L structure.

Disclosure of Invention

Embodiments of the present invention overcome the foregoing deficiencies by providing a power overlay (PO L) structure that eliminates the use of DBC substrates as the thermal interface between the PO L sub-module and the heat sink.

According to one aspect of the invention, a power overlay (PO L) structure includes a PO L sub-module, a PO L sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer, the top surface of the semiconductor device having at least one contact pad formed thereon, the PO L sub-module further includes a metal interconnect structure extending through the dielectric layer and electrically coupled to the at least one contact pad of the semiconductor device.

In accordance with another aspect of the present invention, a method of forming a power overlay (PO L) structure includes providing a semiconductor device, attaching a first surface of the semiconductor device to a dielectric layer, forming a via through the dielectric layer, and forming a metal interconnect structure extending through the via in the dielectric layer to electrically connect to the semiconductor device.

According to yet another aspect of the invention, a power overlay (PO L) package structure includes a PO L sub-module, the PO L sub-module includes a dielectric layer, a first semiconductor device attached to the dielectric layer, and an interconnect structure electrically coupled to a first side of the first semiconductor device.

According to yet another aspect of the present invention, a semiconductor device package includes a first semiconductor device, a second semiconductor device having a thickness greater than a thickness of the first semiconductor device, and an insulating substrate coupled to first surfaces of the first and second semiconductor devices. The metallization layer extends through the insulating base such that a first surface of the metallization layer is coupled to the contact pads of the first and second semiconductor devices. A first conductive pad having a first side is coupled to the first semiconductor device via a conductive contact layer; a second conductive pad having a first side is coupled to the first semiconductor device via a conductive contact layer. The first conductive pad has a thickness greater than a thickness of the second conductive pad, and second sides of the first and second conductive pads are coplanar.

According to still another aspect of the present invention, a semiconductor device package includes: the semiconductor device includes a dielectric layer having a plurality of vias formed therethrough, and a semiconductor device having a first surface coupled to a top surface of the dielectric layer. The semiconductor device package also includes a metal interconnect structure coupled to a bottom surface of the dielectric layer. The metal interconnect structure extends through the plurality of vias of the dielectric layer to connect to the first surface of the semiconductor device. The semiconductor device package also includes a conductive pad having a bottom surface coupled to the second surface of the semiconductor device, and an organic thermal interface coupled to the top surface of the conductive pad without a direct copper clad (DBC) substrate positioned between the organic thermal interface and the conductive pad.

A power overlay (PO L) structure, comprising:

the PO L submodule and the PO L submodule include:

a dielectric layer;

a semiconductor device having a top surface attached to the dielectric layer, the top surface having at least one contact pad formed thereon;

a metal interconnect structure extending through the dielectric layer and electrically coupled to at least one contact pad of the semiconductor device;

a conductive pad coupled to a bottom surface of the semiconductor device; and

a thermal interface having a first side coupled to a conductive pad; and

a heat spreader coupled to a second side of the electrically isolated thermal interface.

Preferably, the thermal interface is thermally conductive.

Preferably, the PO L structure further includes an encapsulant positioned in the space between the dielectric layer and the thermal interface around the semiconductor device and the conductive pads.

Preferably, the thermal interface is coupled to the conductive pad without a direct copper clad (DBC) substrate positioned therebetween.

Preferably, the conductive pad comprises at least one of copper, molybdenum and aluminum.

Preferably, the PO L structure further includes one of a solder material, a conductive adhesive, and a sintered silver layer positioned between the semiconductor device and the conductive pad to secure the conductive pad to the semiconductor device.

Preferably, the PO L structure further includes a printed circuit board, and

wherein the PO L sub-module is attached to the printed circuit board by input/output connections.

Preferably, the PO L structure further includes a lead frame electrically coupled to the PO L sub-module, and

wherein the lead frame is directly attached to the conductive pad.

A method of forming a power overlay (PO L) structure, comprising:

providing a semiconductor device;

attaching a first surface of a semiconductor device to the dielectric layer;

forming a via through the dielectric layer;

forming a metal interconnect structure extending through the via in the dielectric layer to electrically connect to the semiconductor device;

attaching a first surface of a conductive pad to a second surface of a semiconductor device;

forming a thermal interface on top of the second surface of the conductive pad; and

the heat sink is thermally coupled to the conductive pad without a direct copper clad (DBC) substrate positioned between the heat sink and the conductive pad.

Preferably, the method further comprises encapsulating the semiconductor device and at least a portion of the conductive pad with a polymeric molding compound prior to forming the thermal interface.

Preferably, the method further comprises applying an underfill between the dielectric layer and the thermal interface to encapsulate the semiconductor device and at least a portion of the conductive pads.

Preferably, forming the thermal interface comprises: the top surface of the first conductive pad is coated with one of a thermally conductive liquid and a thermally conductive paste.

Preferably, the method further comprises curing the thermal interface.

Preferably, the method further comprises attaching the first surface of the conductive pad to the second surface of the semiconductor device using a conductive paste.

Preferably, the method further comprises attaching the metal interconnect structure to an external circuit structure.

Preferably, the method further comprises providing a leadframe assembly coupled to the conductive pads, the leadframe forming an interconnect between the PO L structure and the external circuit structure.

A power overlay (PO L) package structure, comprising:

the PO L submodule and the PO L submodule include:

a dielectric layer;

a first semiconductor device attached to the dielectric layer;

an interconnect structure electrically coupled to the first side of the first semiconductor device, the interconnect structure extending through the dielectric layer to electrically connect the at least one contact pad to the first semiconductor device;

a first conductive pad having a bottom surface coupled to a second side of the first semiconductor device; and

a thermal interface coupled to a top surface of the first conductive pad without a direct copper clad (DBC) substrate positioned therebetween; and

a heat sink coupled directly to the thermal interface.

Preferably, the first conductive pad comprises copper.

Preferably, the PO L packaging structure further includes a filler material surrounding the first semiconductor device and at least a portion of the first conductive pad.

Preferably, the PO L package structure further includes a second semiconductor device having a first side attached to the dielectric layer.

Preferably, the bottom side of the first conductive pad is coupled to the second side of the second semiconductor device.

Preferably, the second semiconductor device has a vertical height different from that of the first semiconductor device;

wherein the first portion of the first conductive pad is coupled to the first semiconductor device;

wherein the second portion of the first conductive pad is coupled to the second semiconductor device; and is

Wherein an overall vertical height of the first portion of the first conductive pad and the first semiconductor device is substantially equal to an overall vertical height of the second portion of the first conductive pad and the second semiconductor device.

Preferably, the PO L package structure further includes a second conductive pad having a bottom surface coupled to the second semiconductor device.

Preferably, the PO L package structure further includes:

a printed circuit board; and

a lead frame coupled to the first conductive pad, the lead frame configured to electrically connect the PO L submodule to the printed circuit board.

A semiconductor device package, comprising:

a first semiconductor device;

a second semiconductor device having a thickness greater than a thickness of the first semiconductor device;

an insulating substrate coupled to first surfaces of the first and second semiconductor devices;

a metallization layer extending through the insulating base such that a first surface of the metallization layer is coupled to the contact pads of the first and second semiconductor devices;

a first conductive pad having a first side coupled to the first semiconductor device via a conductive contact layer,

a second conductive pad having a first side coupled to the first semiconductor device via a conductive contact layer; and

wherein the first conductive pad has a thickness greater than a thickness of the second conductive pad; and

wherein the second sides of the first and second conductive pads are coplanar.

Preferably, the package includes a thermal interface layer coupled to the second side of the first conductive pad and the second side of the second conductive pad.

Preferably, the thermal interface layer is electrically insulating and thermally conductive.

Preferably, the thermal interface layer is electrically and thermally conductive.

Preferably, the thermal interface layer comprises a plurality of conductive fibers suspended in a resin matrix.

Preferably, a first portion of the thermal interface layer is coupled to the first conductive pad and a second portion of the thermal interface layer is coupled to the second conductive pad; and is

Wherein a gap is formed between the first portion and the second portion of the thermal interface layer such that the first portion of the thermal interface layer is electrically insulated from the second portion of the thermal interface layer.

Preferably, the thermal interface layer comprises a multilayer substrate comprising:

a first thermal interface layer comprising an electrically insulating and thermally conductive material having a first side directly coupled to the first and second conductive pads;

a ceramic substrate having a first side directly coupled to a second side of the first thermal interface layer; and

a second thermal interface layer, comprising an electrically insulating and thermally conductive material, is directly coupled to the second side of the ceramic substrate.

Preferably, the thermal interface layer comprises a multilayer substrate comprising:

a first thermal interface layer comprising an electrically insulating and thermally conductive material having a first side directly coupled to the first and second conductive pads;

a ceramic substrate having a first side directly coupled to a second side of the first thermal interface layer; and

a second thermal interface layer, comprising an electrically and thermally conductive material, is directly coupled to the second side of the ceramic substrate.

A semiconductor device package, comprising:

a dielectric layer having a plurality of vias formed therethrough;

a semiconductor device having a first surface coupled to a top surface of a dielectric layer;

a metal interconnect structure coupled to a bottom surface of the dielectric layer, the metal interconnect structure extending through the plurality of vias of the dielectric layer to connect to the first surface of the semiconductor device;

a conductive pad having a bottom surface coupled to the second surface of the semiconductor device; and

an organic thermal interface coupled to the top surface of the conductive pad without a direct copper clad (DBC) substrate positioned between the organic thermal interface and the conductive pad.

Preferably, the organic thermal interface is thermally and electrically conductive.

Preferably, the organic thermal interface is thermally conductive and electrically insulating.

Preferably, the organic thermal interface layer comprises a plurality of conductive fibers suspended in a resin matrix.

Preferably, the semiconductor device package further includes an insulating underfill material between the dielectric layer and the thermal interface.

Preferably, the conductive pad comprises a thermally and electrically conductive material.

Preferably, the organic thermal interface comprises a multilayer substrate comprising:

a first layer comprising an organic material having a first side coupled to a conductive pad;

a ceramic substrate having a first side directly coupled to a second side of the first layer; and

a second layer comprising an electrically insulating and thermally conductive material coupled directly to the second side of the ceramic substrate.

Preferably, the organic thermal interface comprises a multilayer substrate comprising:

a first layer comprising an organic material having a first side coupled to a conductive pad;

a ceramic substrate having a first side directly coupled to a second side of the first layer; and

a second layer, comprising an electrically and thermally conductive material, is directly coupled to the second side of the ceramic substrate.

These and other advantages and features will be more readily understood from the following detailed description of the preferred embodiments of the invention provided in conjunction with the accompanying drawings.

Drawings

The drawings illustrate embodiments presently contemplated for carrying out the invention.

In the drawings:

fig. 1 is a schematic cross-sectional side view of a prior art power overlay (PO L) structure incorporating a DBC substrate.

Fig. 2 is a schematic cross-sectional side view of a PO L structure according to an embodiment of the invention.

Fig. 3 is a schematic cross-sectional side view of a PO L structure according to another embodiment of the invention.

Fig. 4 is a schematic cross-sectional side view of a PO L structure according to yet another embodiment of the invention.

Fig. 5 is a schematic cross-sectional side view of a PO L assembly according to an embodiment of the invention.

Fig. 6-16 are schematic cross-sectional side views of the PO L submodule during various stages of a manufacturing/build process according to an embodiment of the invention.

Fig. 17 is a schematic cross-sectional side view of a portion of a leaded PO L sub-module in accordance with another embodiment of the invention.

Fig. 18 is a schematic cross-sectional side view of a portion of a leaded PO L sub-module in accordance with another embodiment of the invention.

Fig. 19 is a schematic cross-sectional side view of a portion of a PO L submodule having stepped conductive pads according to an embodiment of the invention.

Fig. 20 is a schematic cross-sectional side view of a portion of a PO L submodule having a multi-layer conductive shim assembly in accordance with an embodiment of the present invention.

Detailed Description

Embodiments of the present invention provide a power overlay (PO L) structure having an improved thermal interface included therein, and methods for forming such a PO L structure the PO L structure includes a thermal interface layer that addresses the conductive pads of semiconductor devices of different heights and increases the choice of encapsulation materials and methods.

Referring to fig. 2, a semiconductor device assembly or power overlay (PO L) structure 40 according to an embodiment of the invention is shown, the PO L structure 40 includes a PO L sub-module 42 having one or more semiconductor devices 43,44,45 therein, which may be in the form of dies, diodes, or other power electrical devices according to various embodiments, as shown in fig. 2, three semiconductor devices 43,44,45 are provided in the PO L sub-module 42, although it will be appreciated that a greater or lesser number of semiconductor devices 43,44,45 may be included in the PO L sub-module 42, the PO L sub-module 42 may include any number of additional circuit components 46, e.g., gate drivers, in addition to the semiconductor devices 43,44, 45.

The dielectric layers 48 may be in the form of a laminate or film according to various embodiments, and may be formed from one of a variety of dielectric materials, such as Kapton @, Ultem @, Polytetrafluoroethylene (PTFE), Utilix @, polysulfone material (e.g., Udel, Radel) or another polymer film, such as liquid crystal polymer (L CP) or polyimide material.

The PO L sub-module 42 also includes a metallization layer or interconnect structure 52 that forms a direct metal connection to the semiconductor devices 43,44,45 through metal interconnects 54, the metal interconnects 54 extending through vias 56 formed in the dielectric layer 48 to connect to contact pads 58 on the respective semiconductor devices 43,44, 45.

The PO L submodule 42 also includes one or more conductive plates or pads 60 that are secured to the semiconductor devices 43,44,45 with a thermally and electrically conductive contact layer 62 according to various embodiments, for example, the conductive contact layer 62 may be a solder material, a conductive adhesive, or sintered silver, the conductive pads 60 are metal and alloy materials, such as copper, aluminum, molybdenum, or combinations thereof, e.g., copper molybdenum or copper tungsten, and composite materials, such as aluminum silicon, aluminum silicon carbide, aluminum-graphite, copper-graphite, and the like.

Dielectric filler material 64 is also provided in the PO L submodule 42 to fill gaps between and around the semiconductor devices 43,44,45 and the conductive pads 60 in the PO L submodule 42 to provide additional structural integrity to the PO L submodule 42 according to various embodiments, the dielectric filler material 64 may be in the form of a polymeric material, such as an underfill (e.g., a capillary underfill or a non-flowing underfill), an encapsulant, silicone, or a molding compound.

The PO L structure 40 also includes heat sinks 66 that facilitate cooling of the semiconductor devices 43,44,45, the heat sinks 66 include a material having a high thermal conductivity, such as copper, aluminum, or a composite material, the heat sinks 66 are coupled to the PO L sub-module 42 by a thermal interface substrate or layer 68 formed on the conductive pads 60 and the dielectric filler material 64.

Thermal interface layer 68 is a thermally conductive, electrically insulating polymeric or organic material, such as a thermal pad, thermal paste, thermal grease, or thermal adhesive. Thermal interface layer 68 electrically insulates heat spreader 66 from conductive pads 60. According to one embodiment, thermal interface layer 68 includes conductive fillers, particles, or fibers suspended in a matrix of resin or epoxy. For example, thermal interface layer 68 may be an epoxy or silicone filled with a thermally conductive, electrically insulating filler such as alumina and/or boron nitride. According to one embodiment, thermal interface layer 68 has a thickness of approximately 100 μm. However, those skilled in the art will recognize that the thickness of thermal interface layer 68 may vary based on design specifications. Thermal interface layer 68 provides superior thermal performance compared to a DBC substrate because thermal interface layer 68 does not experience the thermal resistance of the ceramic layers included within the DBC substrate.

In embodiments where thermal interface layer 68 is a thermal paste, thermal grease, or thermal pad (e.g., a preformed sheet or film of organic material), heat spreader 66 is secured to PO L sub-module 42 using screws or other fastening devices (not shown) at a number of locations around the perimeter of PO L sub-module 42, causing thermal interface layer 68 to be sandwiched between conductive gasket 60 and heat spreader 66 alternatively, in embodiments where thermal interface layer 68 is a polymeric adhesive, thermal interface layer 68 is applied in a tacky state to PO L sub-module 42 and cured after heat spreader 66 is positioned on top of thermal interface layer 68, thereby bonding heat spreader 66 to PO L sub-module 42 without additional fasteners.

As described in greater detail with reference to fig. 5, the PO L sub-module 42 also includes input-output (I/O) connections 70 that enable the PO L structure 40 to be surface mounted to an external circuit, such as a Printed Circuit Board (PCB). according to an exemplary embodiment, the I/O connections 70 are formed by solder Ball Grid Array (BGA) solder pads 72 that are configured to be attached/affixed to the PCB to electrically couple the PO L structure 40 to the PCB, although other suitable second level solder interconnects, such as a land grid array (36ga 36). BGA solder pads 72 provide a highly reliable interconnect structure that is resistant to failure in high stress conditions.

Referring now to fig. 3, it is shown that the PO L structure 76 and PO L sub-module 78. PO L structure 76 and PO L sub-module 78 according to an alternative embodiment of the invention includes a number of components similar to the components shown in the PO L structure 40 and PO L sub-module 42 in fig. 2, and thus the numbers used to refer to the components in fig. 2 will be used to refer to the similar components in fig. 3.

As shown, the PO L submodule 78 includes a multi-layer thermal interface 80 positioned between the conductive pad 60 and the heat sink 66. the multi-layer thermal interface 80 includes a first thermal interface layer 82, a ceramic insulation layer 84, and a second thermal interface layer 86. the inclusion of the ceramic insulation layer 84 provides additional electrical insulation between the PO L submodule 78 and the heat sink 66 for high voltage applications. for example, the insulation layer 84 may be constructed of a ceramic material such as alumina or aluminum nitride.

As shown, a first thermal interface layer 82 is sandwiched between conductive pad 60 and ceramic insulating layer 84. According to one embodiment, first thermal interface layer 82 of fig. 3 comprises a thermally conductive, electrically insulating material similar to thermal interface layer 68 of fig. 2, allowing heat to transfer from conductive gasket 60 to heat sink 66 while electrically insulating conductive gasket 60 from heat sink 66. In an exemplary embodiment, first thermal interface layer 82 includes an epoxy or silicone filled with a thermally conductive but electrically insulating filler such as alumina or boron nitride.

In an alternative embodiment, the first thermal interface layer 82 includes a conductive material, such as solder, conductive adhesive, or sintered silver, formed as a number of discrete pads 88 on top of the conductive pads 60, as shown in fig. 4. According to various embodiments, lateral spaces 90 between adjacent pads 88 may be left as air gaps, or filled with dielectric filler material 64.

Referring now to fig. 3 and 4 together, a second thermal interface layer 86 is sandwiched between the ceramic insulating layer 84 and the heat spreader 66. According to one embodiment, second thermal interface layer 86 includes a thermally conductive, electrically insulating material similar to thermal interface layer 68 in fig. 2. In an alternative embodiment, second thermal interface layer 86 is a material that is both thermally and electrically conductive, such as a silver-filled epoxy or silicone.

Fig. 5 illustrates a PO L0 assembly 92 incorporating a PO L structure 40 (fig. 2) and a PO L structure 76 (fig. 3, 4) in accordance with an embodiment of the invention, as shown, the respective I/O connections 70 of the PO L1 structures 40,76 are coupled to an external circuit member 94, such as a Printed Circuit Board (PCB) — although two PO L structures 40,76 are illustrated in the PO L assembly 92, one skilled in the art will recognize that the PO L assembly 92 may include any number of PO L structures in accordance with various embodiments of the invention, furthermore, the PO L assembly 92 may include a single type of multiple PO L structures, such as two or more PO L structures 40, or two or more PO L structures 76.

Referring now to fig. 6-16, a detailed view of the process steps of the fabrication technique of the PO L sub-module 42 of fig. 2 and the PO L sub-module 78 of fig. 3 and 4 is provided in accordance with an embodiment of the present invention, referring first to fig. 6, the build process of the PO L sub-module 42,78 begins with the application of an adhesive layer 50 onto the dielectric layer 48. in the next step of the technique, as shown in fig. 7, one or more semiconductor devices 44,45 (e.g., two semiconductor devices) are secured to the dielectric layer 48 by the adhesive layer 50, in order to secure the semiconductor devices 44,45 to the dielectric layer 48, the top surfaces 96 of the semiconductor devices 44,45 are placed on the adhesive layer 50, the adhesive 50 is then cured to secure the semiconductor devices 44,45 to the dielectric layer 48.

As shown in fig. 8, a plurality of vias 56 are then formed through the adhesive layer 50 and the dielectric layer 48. According to embodiments of the present invention, the vias 56 may be formed by a laser ablation or laser drilling process, plasma etching, photo-definition (photo-definition), or mechanical drilling process.

Although forming the vias 56 through the adhesion layer 50 and the dielectric layer 48 is shown in fig. 8 as being performed after placing the semiconductor devices 44,45 on the adhesion layer 50, it will be appreciated that the placement of the semiconductor devices 44,45 may occur after the vias are formed. Alternatively, depending on the constraints imposed by the via size, the semiconductor devices 44,45 may be first placed on the adhesion layer 50 and the dielectric layer 48, with the vias 56 subsequently formed at locations corresponding to the plurality of metallized circuit and/or connection pad contact pads 58 formed on the semiconductor devices 44, 45. Further, a combination of pre-drilled and post-drilled vias may be used.

Referring now to fig. 9 and 10, in securing the semiconductor devices 44,45 to the dielectric layer 48 and forming the vias 56, the vias 56 are cleaned (e.g., by a Reactive Ion Etch (RIE) de-dusting process) and subsequently metallized to form a metallization layer or interconnect layer 54. The metallization layer 54 is typically formed by a combination of sputtering and electroplating applications, although it is recognized that other electroless methods of metal deposition may also be used. For example, the titanium adhesion layer and the copper seed layer may be first applied via a sputtering process, followed by an electroplating process that increases the thickness of the copper to a desired level. The applied metal material pattern is then determined to have the desired shape of the metal interconnects 54 and functions as a vertical feedthrough formed through the dielectric layer 48 and the adhesion layer 50. The metal interconnects 54 extend from the circuit and/or connection pad contact pads 58 of the semiconductor devices 44,45, through the vias/openings 56, and out through the top surface 98 of the dielectric layer 48.

As shown in fig. 11, a solder mask layer 74 is applied over the patterned metal interconnects 54 to provide a protective coating and define interconnect pads. In alternative embodiments, it will be appreciated that the interconnect pads may have a metal finish that facilitates solderability, such as Ni or Ni/Au.

Referring now to fig. 12, in a next step of the fabrication technique, a conductive contact layer 62 is applied to the bottom surface 100 of the semiconductor devices 44, 45. The bottom surface 102 of the conductive pad 60 is then coupled to the semiconductor devices 44,45 through the conductive contact layer 62.

According to one embodiment of the present invention, and as shown in fig. 12, the semiconductor devices 44,45 may have varying thicknesses/heights. To balance the overall height of the respective semiconductor devices 44,45, conductive pad 60 may be of different heights, such that the overall thickness/height of each semiconductor device 44, 45/conductive pad pair 60 is equal, and the back surface of conductive pad 60 is "planarized".

As shown in FIG. 13, the build-up technique of fabricating the PO L sub-modules 42,78 continues with the application of the dielectric filler material 64 to fill the gap between and around the semiconductor devices 44,45 and the conductive pads 60 in the PO L sub-modules 42,78 to confine the dielectric layer 48 and provide additional electrical insulation and structural integrity to the PO L sub-modules 42, 78. in one embodiment, the dielectric filler material 64 is applied and cured using an overmolding technique. after the dielectric filler material 64 is cured, a portion 104 of the dielectric filler material 64 is removed using a grinding operation to expose the conductive pads 60. as shown in FIG. 14, the grinding operation may also be used to remove any variation in the height of the conductive pads 60 so that the top surfaces 106 of the conductive pads 60 and the top surfaces 108 of the dielectric filler material 64 are coplanar.

In the next step of the fabrication process, as shown in FIG. 15, a first side 110 of a thermal interface 112 is applied to the respective top surfaces 106,108 of the conductive pad 60 and the dielectric filler material 64. In embodiments where thermal interface 112 includes a single thermal interface layer 68 (fig. 2), thermal interface 112 is applied to top surfaces 106,108 of conductive pad 60 and dielectric filler material 64 in one step. Alternatively, the thermal interface 112 may be a multi-layer thermal interface 80 as shown in fig. 3 and 4. Referring also to fig. 3 and 4, the individual layers of multilayer thermal interface 80 are applied sequentially onto top surfaces 106,108 of conductive pad 60 and dielectric filler material 64 using a build-up technique, with first thermal interface layer 82 applied on top of dielectric filler material 64 and conductive pad 60, ceramic insulation layer 84 next applied on top of first thermal interface layer 82, and second thermal interface layer 86 finally applied on top of ceramic insulation layer 84.

In the next step of the fabrication technique, I/O connections 70 are applied to a solder mask layer 74, in one embodiment, as shown in FIG. 16, I/O connections 70 are solder pads 72, in an alternative embodiment of the build technique, as shown in FIG. 17, I/O connections 70 are configured as leads 114 for through-hole components, after the build process of PO L submodules 42,78 is complete, heat spreader 66 is attached to the second side 116 of thermal interface 112, PO L submodules 42,78 may be unitary for surface mounting to an external circuit, such as PCB94 (FIG. 5).

Referring now to FIG. 18, an alternative embodiment of the PO L sub-module 118 the PO L sub-module 118 includes a number of components similar to the components shown in the PO L sub-module 42 in FIG. 2, and thus the numbers used to refer to the components in FIG. 2 will also be used to refer to the similar components in FIG. 18.

As shown, the PO L sub-module 118 includes semiconductor devices 44 mounted to a dielectric layer 48 by an adhesive layer 50, metal interconnects 54 extend through vias 56 formed in the dielectric layer 48 to connect contact pads (not shown) to the semiconductor devices 44, conductive pads 120 are coupled to the respective semiconductor devices 44 by conductive contact layers 62 similar to the conductive pads 60 of FIG. 2, the conductive pads 120 include a metal or alloy material, such as copper, aluminum, molybdenum, or combinations thereof, a dielectric filler material 64 is provided to fill gaps between and around the semiconductor devices 44 and the conductive pads 120 in the PO L sub-module 118, a thermal interface 112, such as a thermal interface layer 68 (FIG. 2) or a multi-layer thermal interface 80 (FIG. 3), is provided on top of the dielectric filler material 64 and the conductive pads 120.

As shown in FIG. 18, the conductive pads 120 are coupled to the lead frame 122, according to embodiments of the invention, the lead frame 122 is pre-attached to the conductive pads 120 prior to placing the conductive pads 120 into the conductive contact layer 62. for example, the lead frame 122 and the lead pads 60 may be pre-fabricated from a common copper plate, or the lead frame 122 may be pre-attached to the conductive pads 60 by a high temperature coupling process, such as soldering, brazing, welding, or other similar method for assembly into the PO L sub-module 118. alternatively, it will be appreciated that the lead frame 122 may instead be post-attached after the fabrication of the PO L sub-module 118 is completed.

Referring now to fig. 19 and 20, two alternative embodiments of the PO L sub-module 124 are shown, which address the situation where the PO L sub-module 124 includes semiconductor devices 126,128 of different heights in addition, the PO L sub-module 124 includes a number of components similar to the components shown in the PO L sub-module 42 in fig. 2, and thus the numbers used to refer to the components in fig. 2 will also be used to refer to the similar components in fig. 19 and 20.

Referring first to fig. 19, an alternative embodiment including a conductive pad 130 having a stepped configuration is shown. As shown, first portion 132 of conductive pad 130 has a first height or thickness 134 and second portion 136 of conductive pad 130 has a second height or thickness 138 that accounts for the different heights of semiconductor devices 126,128 while maintaining a planar top surface 140 of conductive pad 130.

An alternative embodiment of the PO L sub-module 24 is shown in FIG. 20, in which the first conductive pad 142 is coupled to the semiconductor device 126 using a first conductive contact layer 144, the first conductive contact layer 144 being, for example, similar to the solder of the conductive contact layer 62 (FIG. 2). the first conductive pad 142 is sized such that the upper surface 146 of the first conductive pad 142 and the upper surface 148 of the semiconductor device 128 are coplanar.A second conductive contact layer 150 is then applied to the first conductive pad 142 and the top surface of the semiconductor device 128. in one embodiment, the second conductive contact layer 150 includes solder.A second conductive pad 152 sized to span at least the entire width of the semiconductor device 126,128 is then attached to the second conductive pad 152 as shown

Embodiments of the present invention thus provide a PO L package and interconnect structure that includes a thermal interface that is free of defects of a DBC substrate, for example, because thermal interface layer 68 and multi-layer thermal interface 80 may be applied in manufacturing steps that occur after dielectric filler material 64 is applied and cured, dielectric filler material 64 may be applied using encapsulation or overmolding techniques, rather than more expensive and time consuming underfill processes that are more likely to result in voids.

Although embodiments of the present invention have been described as including power semiconductor devices used in high voltage power applications, those skilled in the art will recognize that the techniques set forth herein are equally applicable to low power applications and chip packages incorporating semiconductor devices that are not power semiconductor devices or semiconductor devices having electrical connections extending only to a single side of the semiconductor device.

Thus, in accordance with one embodiment of the present invention, a power overlay (PO L) structure includes a PO L sub-module, the PO L sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer, the top surface of the semiconductor device having at least one contact pad formed thereon, the PO L sub-module further includes a metal interconnect structure extending through the dielectric layer and electrically coupled to the at least one contact pad of the semiconductor device.

According to another embodiment of the present invention, a method of forming a power overlay (PO L) structure includes providing a semiconductor device, attaching a first surface of the semiconductor device to a dielectric layer, forming a via through the dielectric layer, and forming a metal interconnect structure extending through the via in the dielectric layer to electrically connect to the semiconductor device.

According to yet another embodiment of the present invention, a power overlay (PO L) package structure includes a PO L sub-module, the PO L sub-module includes a dielectric layer, a first semiconductor device attached to the dielectric layer, and an interconnect structure electrically coupled to a first side of the first semiconductor device.

According to still another embodiment of the present invention, a semiconductor device package includes a first semiconductor device, a second semiconductor device having a thickness greater than a thickness of the first semiconductor device, and an insulating substrate coupled to first surfaces of the first and second semiconductor devices. The metallization layer extends through the insulating base such that a first surface of the metallization layer is coupled to the contact pads of the first and second semiconductor devices. A first conductive pad having a first side is coupled to the first semiconductor device via a conductive contact layer; a second conductive pad having a first side is coupled to the first semiconductor device via a conductive contact layer. The first conductive pad has a thickness greater than a thickness of the second conductive pad, and second sides of the first and second conductive pads are coplanar.

According to still another embodiment of the present invention, a semiconductor device package includes: the semiconductor device includes a dielectric layer having a plurality of vias formed therethrough, and a semiconductor device having a first surface coupled to a top surface of the dielectric layer. The semiconductor device package also includes a metal interconnect structure coupled to a bottom surface of the dielectric layer. The metal interconnect structure extends through the plurality of vias of the dielectric layer to connect to the first surface of the semiconductor device. The semiconductor device package also includes a conductive pad having a bottom surface coupled to the second surface of the semiconductor device, and an organic thermal interface coupled to the top surface of the conductive pad without a direct copper clad (DBC) substrate positioned between the organic thermal interface and the conductive pad.

While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.